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This commit is contained in:
huxi
2025-12-03 11:12:34 +08:00
parent c23ae4f24c
commit bc195654bf
8163 changed files with 3799544 additions and 92 deletions
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SDK/interface/driver/cpu/br35/asm/power/p11/ipc_spin_lock.h
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#ifndef _IPC_SPIN_LOCK_H_
#define _IPC_SPIN_LOCK_H_
#include "typedef.h"
#include "gpio.h"
enum ipc_spin_lock_event {
IPC_SPIN_LOCK_EVENT_USER0 = 0,//自定义事件名
IPC_SPIN_LOCK_EVENT_USER1,
IPC_SPIN_LOCK_EVENT_USER2,
IPC_SPIN_LOCK_EVENT_USER3,
IPC_SPIN_LOCK_EVENT_USER4,
IPC_SPIN_LOCK_EVENT_USER5,
IPC_SPIN_LOCK_EVENT_USER6,
IPC_SPIN_LOCK_EVENT_USER7,
IPC_SPIN_LOCK_EVENT_USER8,
IPC_SPIN_LOCK_EVENT_P11_GPIO,
IPC_SPIN_LOCK_EVENT_RTC,
IPC_SPIN_LOCK_EVENT_UART, //11
IPC_SPIN_LOCK_EVENT_P11_IIC,//12
IPC_SPIN_LOCK_EVENT_CBUF, //13
IPC_SPIN_LOCK_EVENT_PMU, //14
IPC_SPIN_LOCK_EVENT_SFR, //15
IPC_SPIN_LOCK_EVENT_MAX,
};
void ipc_spin_lock_init();
void ipc_spin_lock(enum ipc_spin_lock_event event);//0~15
void ipc_spin_unlock(enum ipc_spin_lock_event event);//0~15
#endif
SDK/interface/driver/cpu/br35/asm/power/p11/lp_ipc.h
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#ifndef __LP_IPC_H__
#define __LP_IPC_H__
//===========================================================================//
// P2M MESSAGE TABLE //
//===========================================================================//
//==================power=============================
#define P2M_WKUP_SRC P2M_MESSAGE_ACCESS(0)
#define P2M_WKUP_P_PND P2M_MESSAGE_ACCESS(1)
#define P2M_WKUP_N_PND P2M_MESSAGE_ACCESS(2)
#define P2M_AWKUP_P_PND P2M_MESSAGE_ACCESS(3)
#define P2M_AWKUP_N_PND P2M_MESSAGE_ACCESS(4)
#define P2M_WKUP_RTC P2M_MESSAGE_ACCESS(5)
#define P2M_WKUP_CNT0 P2M_MESSAGE_ACCESS(6)
#define P2M_WKUP_CNT1 P2M_MESSAGE_ACCESS(7)
#define P2M_WKUP_CNT2 P2M_MESSAGE_ACCESS(8)
#define P2M_WKUP_CNT3 P2M_MESSAGE_ACCESS(9)
#define P2M_OSC_CNT0 P2M_MESSAGE_ACCESS(10)
#define P2M_OSC_CNT1 P2M_MESSAGE_ACCESS(11)
#define P2M_OSC_CNT2 P2M_MESSAGE_ACCESS(12)
#define P2M_OSC_CNT3 P2M_MESSAGE_ACCESS(13)
#define P2M_RESET_FLAG P2M_MESSAGE_ACCESS(14)
//==================system===========================
#define P2M_MESSAGE_BANK_ADR_L P2M_MESSAGE_ACCESS(15)
#define P2M_MESSAGE_BANK_ADR_H P2M_MESSAGE_ACCESS(16)
#define P2M_MESSAGE_BANK_INDEX P2M_MESSAGE_ACCESS(17)
#define P2M_MESSAGE_BANK_ACK P2M_MESSAGE_ACCESS(18)
#define P2M_P11_HEAP_BEGIN_ADDR_L P2M_MESSAGE_ACCESS(19)
#define P2M_P11_HEAP_BEGIN_ADDR_H P2M_MESSAGE_ACCESS(20)
#define P2M_P11_HEAP_SIZE_L P2M_MESSAGE_ACCESS(21)
#define P2M_P11_HEAP_SIZE_H P2M_MESSAGE_ACCESS(22)
#define P2M_REPLY_SYNC_CMD P2M_MESSAGE_ACCESS(23)
#define P2M_CBUF_ADDR0 P2M_MESSAGE_ACCESS(24)
#define P2M_CBUF_ADDR1 P2M_MESSAGE_ACCESS(25)
#define P2M_CBUF_ADDR2 P2M_MESSAGE_ACCESS(26)
#define P2M_CBUF_ADDR3 P2M_MESSAGE_ACCESS(27)
#define P2M_CBUF1_ADDR0 P2M_MESSAGE_ACCESS(28)
#define P2M_CBUF1_ADDR1 P2M_MESSAGE_ACCESS(29)
#define P2M_CBUF1_ADDR2 P2M_MESSAGE_ACCESS(30)
#define P2M_CBUF1_ADDR3 P2M_MESSAGE_ACCESS(31)
//==================clock===========================
#define P2M_BTOSC_OK P2M_MESSAGE_ACCESS(35)
//==================lpctmu===========================
#define P2M_CTMU_CMD_ACK P2M_MESSAGE_ACCESS(39)
#define P2M_MASSAGE_CTMU_CH0_L_RES 40
#define P2M_MASSAGE_CTMU_CH0_H_RES 41
#define P2M_CTMU_CH0_L_RES P2M_MESSAGE_ACCESS(40)
#define P2M_CTMU_CH0_H_RES P2M_MESSAGE_ACCESS(41)
#define P2M_CTMU_CH1_L_RES P2M_MESSAGE_ACCESS(42)
#define P2M_CTMU_CH1_H_RES P2M_MESSAGE_ACCESS(43)
#define P2M_CTMU_CH2_L_RES P2M_MESSAGE_ACCESS(44)
#define P2M_CTMU_CH2_H_RES P2M_MESSAGE_ACCESS(45)
#define P2M_CTMU_CH3_L_RES P2M_MESSAGE_ACCESS(46)
#define P2M_CTMU_CH3_H_RES P2M_MESSAGE_ACCESS(47)
#define P2M_CTMU_CH4_L_RES P2M_MESSAGE_ACCESS(48)
#define P2M_CTMU_CH4_H_RES P2M_MESSAGE_ACCESS(49)
//===========================================================================//
// M2P MESSAGE TABLE //
//===========================================================================//
//==================power=============================
#define M2P_LRC_PRD M2P_MESSAGE_ACCESS(0)
#define M2P_WDVDD M2P_MESSAGE_ACCESS(1)
#define M2P_LRC_FEQ0 M2P_MESSAGE_ACCESS(2)
#define M2P_LRC_FEQ1 M2P_MESSAGE_ACCESS(3)
#define M2P_LRC_FEQ2 M2P_MESSAGE_ACCESS(4)
#define M2P_LRC_FEQ3 M2P_MESSAGE_ACCESS(5)
#define M2P_VDDIO_KEEP M2P_MESSAGE_ACCESS(6)
#define M2P_LRC_KEEP M2P_MESSAGE_ACCESS(7)
#define M2P_RCH_FEQ_L M2P_MESSAGE_ACCESS(8)
#define M2P_RCH_FEQ_H M2P_MESSAGE_ACCESS(9)
#define M2P_MEM_CONTROL M2P_MESSAGE_ACCESS(10)
#define M2P_BTOSC_KEEP M2P_MESSAGE_ACCESS(11)
#define M2P_CTMU_KEEP M2P_MESSAGE_ACCESS(12)
#define M2P_RTC_KEEP M2P_MESSAGE_ACCESS(13)
#define M2P_SF_MODE M2P_MESSAGE_ACCESS(14)
#define M2P_DCV_MODE M2P_MESSAGE_ACCESS(15)
#define M2P_LIGHT_PDOWN_DVDD_VOL M2P_MESSAGE_ACCESS(16)
#define M2P_LRC24M_MODE M2P_MESSAGE_ACCESS(17)
//==================system===========================
#define M2P_SYNC_CMD M2P_MESSAGE_ACCESS(25)
#define M2P_WDT_SYNC M2P_MESSAGE_ACCESS(26)
#define M2P_WAIT_RELEASE M2P_MESSAGE_ACCESS(27)
//==================clock===========================
#define M2P_LRC24M_CFG0 M2P_MESSAGE_ACCESS(35)
#define M2P_LRC24M_CFG1 M2P_MESSAGE_ACCESS(36)
#define M2P_BTOSC_CFG0 M2P_MESSAGE_ACCESS(37)
#define M2P_BTOSC_CFG1 M2P_MESSAGE_ACCESS(38)
#define M2P_LRC24M_FEQ0 M2P_MESSAGE_ACCESS(39)
#define M2P_LRC24M_FEQ1 M2P_MESSAGE_ACCESS(40)
#define M2P_LRC24M_FEQ2 M2P_MESSAGE_ACCESS(41)
#define M2P_LRC24M_FEQ3 M2P_MESSAGE_ACCESS(42)
//==================lpctmu===========================
/*触摸所有通道配置*/
#define M2P_CTMU_CMD M2P_MESSAGE_ACCESS(50)
#define M2P_CTMU_CH_ENABLE M2P_MESSAGE_ACCESS(51)
#define M2P_CTMU_CH_WAKEUP_EN M2P_MESSAGE_ACCESS(52)
#define M2P_CTMU_SCAN_TIME M2P_MESSAGE_ACCESS(53)
#define M2P_CTMU_LOWPOER_SCAN_TIME M2P_MESSAGE_ACCESS(54)
/*
* Must Sync to P11 code
*/
enum {
M2P_LP_INDEX = 0,
M2P_PF_INDEX,
M2P_LLP_INDEX,
M2P_P33_INDEX,
M2P_SF_INDEX,
M2P_CTMU_INDEX,
M2P_CCMD_INDEX, //common cmd
M2P_VAD_INDEX,
M2P_USER_INDEX,
M2P_WDT_INDEX,
M2P_SYNC_INDEX,
M2P_APP_INDEX,
};
enum {
P2M_LP_INDEX = 0,
P2M_PF_INDEX,
P2M_LLP_INDEX,
P2M_WK_INDEX,
P2M_WDT_INDEX,
P2M_LP_INDEX2,
P2M_CTMU_INDEX,
P2M_CTMU_POWUP,
P2M_REPLY_CCMD_INDEX, //reply common cmd
P2M_VAD_INDEX,
P2M_USER_INDEX,
P2M_BANK_INDEX,
P2M_REPLY_SYNC_INDEX,
P2M_APP_INDEX,
P2M_OSC_INDEX,
};
enum {
CLOSE_P33_INTERRUPT = 1,
OPEN_P33_INTERRUPT,
LOWPOWER_PREPARE,
M2P_SPIN_LOCK,
M2P_SPIN_UNLOCK,
P2M_SPIN_LOCK,
P2M_SPIN_UNLOCK,
};
#include "power/lp_msg.h"
#endif
SDK/interface/driver/cpu/br35/asm/power/p11/p11_api.h
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#ifndef __P11_API_H__
#define __P11_API_H__
#define P11_P2M_INT_IE P11_SYSTEM->P2M_INT_IE
#define P11_M2P_INT_IE P11_SYSTEM->M2P_INT_IE
#define P11_M2P_INT_SET P11_SYSTEM->M2P_INT_SET
#define P11_P2M_INT_SET P11_SYSTEM->P2M_INT_SET
#define P11_P2M_INT_CLR P11_SYSTEM->P2M_INT_CLR
#define P11_P2M_INT_PND P11_SYSTEM->P2M_INT_PND
enum P11_SYS_CLK_TABLE {
P11_SYS_CLK_RC16M = 0,
P11_SYS_CLK_RC250K,
P11_SYS_CLK_LRC_OSC,
P11_SYS_CLK_BTOSC_24M,
P11_SYS_CLK_BTOSC_48M,
P11_SYS_CLK_LRC24M,
P11_SYS_CLK_CLK_X2,
P11_SYS_CLK_TEST,
};
void p11_sys_clk_sel(u32 sel);
#endif
SDK/interface/driver/cpu/br35/asm/power/p11/p11_csfr.h
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//*********************************************************************************//
// Module name : csfr.h //
// Description : q32small core sfr define //
// By Designer : zequan_liu //
// Dat changed : //
//*********************************************************************************//
#ifndef __P11_Q32S_CSFR__
#define __P11_Q32S_CSFR__
#define __RW volatile // read write
#define __RO volatile const // only read
#define __WO volatile // only write
#define __u8 unsigned int // u8 to u32 special for struct
#define __u16 unsigned int // u16 to u32 special for struct
#define __u32 unsigned int
#define CPU_CORE_NUM 1
//---------------------------------------------//
// q32small define
//---------------------------------------------//
//#ifdef PMU_SYSTEM
#if 0
#define p11_q32s_sfr_base 0x00a000
#define p11_q32s_sfr_offset 0x000000 // multi_core used
#else
#define p11_q32s_sfr_base 0xf2a000
#define p11_q32s_sfr_offset 0x000000 // multi_core used
#endif
#define p11_q32s_cpu_base (p11_q32s_sfr_base + 0x00)
#define p11_q32s_mpu_base (p11_q32s_sfr_base + 0x80)
#define p11_q32s(n) ((JL_TypeDef_p11_q32s *)(p11_q32s_sfr_base + p11_q32s_sfr_offset*n))
#define p11_q32s_mpu(n) ((JL_TypeDef_p11_q32s_MPU *)(p11_q32s_mpu_base + p11_q32s_sfr_offset*n))
//---------------------------------------------//
// q32small core sfr
//---------------------------------------------//
typedef struct {
/* 00 */ __RO __u32 DR00;
/* 01 */ __RO __u32 DR01;
/* 02 */ __RO __u32 DR02;
/* 03 */ __RO __u32 DR03;
/* 04 */ __RO __u32 DR04;
/* 05 */ __RO __u32 DR05;
/* 06 */ __RO __u32 DR06;
/* 07 */ __RO __u32 DR07;
/* 08 */ __RO __u32 DR08;
/* 09 */ __RO __u32 DR09;
/* 0a */ __RO __u32 DR10;
/* 0b */ __RO __u32 DR11;
/* 0c */ __RO __u32 DR12;
/* 0d */ __RO __u32 DR13;
/* 0e */ __RO __u32 DR14;
/* 0f */ __RO __u32 DR15;
/* 10 */ __RO __u32 RETI;
/* 11 */ __RO __u32 RETE;
/* 12 */ __RO __u32 RETX;
/* 13 */ __RO __u32 RETS;
/* 14 */ __RO __u32 SR04;
/* 15 */ __RO __u32 PSR;
/* 16 */ __RO __u32 CNUM;
/* 17 */ __RO __u32 SR07;
/* 18 */ __RO __u32 SR08;
/* 19 */ __RO __u32 SR09;
/* 1a */ __RO __u32 SR10;
/* 1b */ __RO __u32 ICFG;
/* 1c */ __RO __u32 USP;
/* 1d */ __RO __u32 SSP;
/* 1e */ __RO __u32 SP;
/* 1f */ __RO __u32 PCRS;
/* 20 */ __RW __u32 BPCON;
/* 21 */ __RW __u32 BSP;
/* 22 */ __RW __u32 BP0;
/* 23 */ __RW __u32 BP1;
/* 24 */ __RW __u32 BP2;
/* 25 */ __RW __u32 BP3;
/* 26 */ __WO __u32 CMD_PAUSE;
/* */ __RO __u32 REV_30_26[0x30 - 0x26 - 1];
/* 30 */ __RW __u32 PMU_CON0;
/* 31 */ __RW __u32 PMU_CON1;
/* 32 */ __RW __u32 RST_ADDR;
/* */ __RO __u32 REV_3b_30[0x3b - 0x32 - 1];
/* 3b */ __RW __u8 TTMR_CON;
/* 3c */ __RW __u32 TTMR_CNT;
/* 3d */ __RW __u32 TTMR_PRD;
/* 3e */ __RW __u32 BANK_CON;
/* 3f */ __RW __u32 BANK_NUM;
/* 40 */ __RW __u32 ICFG00;
/* 41 */ __RW __u32 ICFG01;
/* 42 */ __RW __u32 ICFG02;
/* 43 */ __RW __u32 ICFG03;
/* 44 */ __RW __u32 ICFG04;
/* 45 */ __RW __u32 ICFG05;
/* 46 */ __RW __u32 ICFG06;
/* 47 */ __RW __u32 ICFG07;
/* 48 */ __RW __u32 ICFG08;
/* 49 */ __RW __u32 ICFG09;
/* 4a */ __RW __u32 ICFG10;
/* 4b */ __RW __u32 ICFG11;
/* 4c */ __RW __u32 ICFG12;
/* 4d */ __RW __u32 ICFG13;
/* 4e */ __RW __u32 ICFG14;
/* 4f */ __RW __u32 ICFG15;
/* 50 */ __RW __u32 ICFG16;
/* 51 */ __RW __u32 ICFG17;
/* 52 */ __RW __u32 ICFG18;
/* 53 */ __RW __u32 ICFG19;
/* 54 */ __RW __u32 ICFG20;
/* 55 */ __RW __u32 ICFG21;
/* 56 */ __RW __u32 ICFG22;
/* 57 */ __RW __u32 ICFG23;
/* 58 */ __RW __u32 ICFG24;
/* 59 */ __RW __u32 ICFG25;
/* 5a */ __RW __u32 ICFG26;
/* 5b */ __RW __u32 ICFG27;
/* 5c */ __RW __u32 ICFG28;
/* 5d */ __RW __u32 ICFG29;
/* 5e */ __RW __u32 ICFG30;
/* 5f */ __RW __u32 ICFG31;
/* 60 */ __RO __u32 IPND0;
/* 61 */ __RO __u32 IPND1;
/* 62 */ __RO __u32 IPND2;
/* 63 */ __RO __u32 IPND3;
/* 64 */ __RO __u32 IPND4;
/* 65 */ __RO __u32 IPND5;
/* 66 */ __RO __u32 IPND6;
/* 67 */ __RO __u32 IPND7;
/* 68 */ __WO __u32 ILAT_SET;
/* 69 */ __WO __u32 ILAT_CLR;
/* 6a */ __RW __u32 IPMASK;
/* 6b */ __RW __u32 GIEMASK;
/* 6c */ __RW __u32 IWKUP_NUM;
/* */ __RO __u32 REV_70_6c[0x70 - 0x6c - 1];
/* 70 */ __RW __u32 ETM_CON;
/* 71 */ __RO __u32 ETM_PC0;
/* 72 */ __RO __u32 ETM_PC1;
/* 73 */ __RO __u32 ETM_PC2;
/* 74 */ __RO __u32 ETM_PC3;
/* 75 */ __RW __u32 WP0_ADRH;
/* 76 */ __RW __u32 WP0_ADRL;
/* 77 */ __RW __u32 WP0_DATH;
/* 78 */ __RW __u32 WP0_DATL;
/* 79 */ __RW __u32 WP0_PC;
/* */ __RO __u32 REV_80_79[0x80 - 0x79 - 1];
/* 80 */ __RW __u32 EMU_CON;
/* 81 */ __RW __u32 EMU_MSG;
/* 82 */ __RO __u32 EMU_SSP_H;
/* 83 */ __RO __u32 EMU_SSP_L;
/* 84 */ __RO __u32 EMU_USP_H;
/* 85 */ __RO __u32 EMU_USP_L;
} JL_TypeDef_p11_q32s;
#undef __RW
#undef __RO
#undef __WO
#undef __u8
#undef __u16
#undef __u32
#endif
//*********************************************************************************//
// //
// end of this module //
// //
//*********************************************************************************//
SDK/interface/driver/cpu/br35/asm/power/p11/p11_io_imap.h
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//===============================================================================//
//
// input IO define
//
//===============================================================================//
#define P11_PB0_IN 1
#define P11_PB1_IN 2
#define P11_PB2_IN 3
#define P11_PB3_IN 4
#define P11_PB4_IN 5
#define P11_PB5_IN 6
#define P11_PB6_IN 7
#define P11_PB7_IN 8
#define P11_PB8_IN 9
//===============================================================================//
//
// function input select sfr
//
//===============================================================================//
typedef struct {
__RW __u8 P11_FI_GP_ICH0;
__RW __u8 P11_FI_GP_ICH1;
__RW __u8 P11_FI_GP_ICH2;
__RW __u8 P11_FI_UART0_RX;
__RW __u8 P11_FI_UART1_RX;
__RW __u8 P11_FI_SPI_DI;
__RW __u8 P11_FI_IIC_SCL;
__RW __u8 P11_FI_IIC_SDA;
} P11_IMAP_TypeDef;
#define P11_IMAP_BASE (p11_sfr_base + map_adr(0x17, 0x00))
#define P11_IMAP ((P11_IMAP_TypeDef *)P11_IMAP_BASE)
SDK/interface/driver/cpu/br35/asm/power/p11/p11_io_omap.h
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//===============================================================================//
//
// output function define
//
//===============================================================================//
#define P11_FO_GP_OCH0 ((0 << 2)|BIT(1))
#define P11_FO_GP_OCH1 ((1 << 2)|BIT(1))
#define P11_FO_GP_OCH2 ((2 << 2)|BIT(1))
#define P11_FO_UART0_TX ((3 << 2)|BIT(1)|BIT(0))
#define P11_FO_UART1_TX ((4 << 2)|BIT(1)|BIT(0))
#define P11_FO_SPI_CLK ((5 << 2)|BIT(1)|BIT(0))
#define P11_FO_SPI_DO ((6 << 2)|BIT(1)|BIT(0))
#define P11_FO_IIC_SCL ((7 << 2)|BIT(1)|BIT(0))
#define P11_FO_IIC_SDA ((8 << 2)|BIT(1)|BIT(0))
//===============================================================================//
//
// IO output select sfr
//
//===============================================================================//
typedef struct {
__RW __u8 P11_PB0_OUT;
__RW __u8 P11_PB1_OUT;
__RW __u8 P11_PB2_OUT;
__RW __u8 P11_PB3_OUT;
__RW __u8 P11_PB4_OUT;
__RW __u8 P11_PB5_OUT;
__RW __u8 P11_PB6_OUT;
__RW __u8 P11_PB7_OUT;
__RW __u8 P11_PB8_OUT;
} P11_OMAP_TypeDef;
#define P11_OMAP_BASE (p11_sfr_base + map_adr(0x16, 0x00))
#define P11_OMAP ((P11_OMAP_TypeDef *)P11_OMAP_BASE)
SDK/interface/driver/cpu/br35/asm/power/p11/p11_mmap.h
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#ifndef __P11_MMAP_H__
#define __P11_MMAP_H__
/////////////////////////////////////////////////////////////////////////////////
//#ifdef PMU_SYSTEM
#if 0
#define P11_RAM_BASE 0
#else
#define P11_RAM_BASE 0xF20000
#endif
#define P11_RAM_BEGIN (P11_RAM_BASE)
#define P11_RAM_SIZE (0x8000)
#define P11_RAM_END (P11_RAM_BASE+P11_RAM_SIZE)
/////////////////////////////////////////////////////////////////////////////////
#define MSYS_POFF_RAM_END P11_RAM_END
#define MSYS_POFF_RAM_SIZE 0x20
#define MSYS_POFF_RAM_BEGIN (MSYS_POFF_RAM_END - MSYS_POFF_RAM_SIZE)
/////////////////////////////////////////////////////////////////////////////////
#define M2P_MESSAGE_END MSYS_POFF_RAM_BEGIN
#define M2P_MESSAGE_SIZE 0xe0
#define M2P_MESSAGE_RAM_BEGIN (M2P_MESSAGE_END - M2P_MESSAGE_SIZE)
/////////////////////////////////////////////////////////////////////////////////
#define P2M_MESSAGE_END M2P_MESSAGE_RAM_BEGIN
#define P2M_MESSAGE_SIZE 0x40
#define P2M_MESSAGE_RAM_BEGIN (P2M_MESSAGE_END - P2M_MESSAGE_SIZE)
//////////////////////////////////////////////////////////////////////////////
#define P11_RAM0_END P2M_MESSAGE_RAM_BEGIN
#define P11_RAM0_BEGIN (P11_RAM_BASE+P11_ISR_SIZE)
#define P11_RAM0_SIZE (P11_RAM0_END - P11_RAM0_BEGIN)
//////////////////////////////////////////////////////////////////////////////
#define P11_ISR_END P11_RAM0_BEGIN
#define P11_ISR_SIZE 0x80
#define P11_ISR_BEGIN P11_RAM_BASE
//////////////////////////////////////////////////////////////////////////////////
#define P11_RAM_ACCESS(x) (*(volatile u8 *)(x))
#define M2P_MESSAGE_ACCESS(x) P11_RAM_ACCESS(M2P_MESSAGE_RAM_BEGIN + x)
#define P2M_MESSAGE_ACCESS(x) P11_RAM_ACCESS(P2M_MESSAGE_RAM_BEGIN + x)
#endif
SDK/interface/driver/cpu/br35/asm/power/p11/p11_sfr.h
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#ifndef __P11_SFR_H__
#define __P11_SFR_H__
//===============================================================================//
//
// sfr define
//
//===============================================================================//
//#ifdef PMU_SYSTEM
#if 0
#define p11_base 0x000000
#define p11_ram_base p11_base
#define p11_sfr_base 0x00a000
#else
#define p11_base 0xf20000
#define p11_ram_base p11_base
#define p11_sfr_base 0xf2a000
#endif
#define __RW volatile // read write
#define __RO volatile const // only read
#define __WO volatile // only write
#define __u8 unsigned int // u8 to u32 special for struct
#define __u16 unsigned int // u16 to u32 special for struct
#define __u32 unsigned int
#define __s8(x) char(x); char(reserved_1_##x); char(reserved_2_##x); char(reserved_3_##x)
#define __s16(x) short(x); short(reserved_1_##x)
#define __s32(x) int(x)
#define map_adr(grp, adr) ((64 * grp + adr) * 4) // grp(0x0-0xff), adr(0x0-0x3f)
#define P11_ACCESS(x) (*(volatile u32 *)(p11_base + x))
#define P11_RAM(x) (*(volatile u32 *)(p11_ram_base + x))
//===============================================================================//
//
// sfr address define
//
//===============================================================================//
//............. 0x0000 - 0x03ff............ for cpu
// #include ../core/csfr.h
//............. 0x0400 - 0x04ff............ for clock
typedef struct {
__RW __u32 PWR_CON;
__RW __u32 RST_SRC;
__RW __u32 WKUP_EN;
__RW __u32 WKUP_SRC;
__RW __u32 SYS_DIV;
__RW __u32 CLK_CON0;
__RW __u32 CLK_CON1;
__RW __u32 CLK_CON2;
__RW __u32 XOSC_CFG0;
__RW __u32 XOSC_CFG1;
__RW __u32 LRC24M_CFG0;
__RW __u32 CLKCFG_CFG0;
} P11_CLOCK_TypeDef;
#define P11_CLOCK_BASE (p11_sfr_base + map_adr(0x04, 0x00))
#define P11_CLOCK ((P11_CLOCK_TypeDef *)P11_CLOCK_BASE)
#define P11_PWR_CON P11_CLOCK->PWR_CON
#define P11_CLK_CON0 P11_CLOCK->CLK_CON0
//............. 0x0600 - 0x06ff............ for system
typedef struct {
__RW __u32 P2M_INT_IE;
__RW __u32 P2M_INT_SET;
__RW __u32 P2M_INT_CLR;
__RO __u32 P2M_INT_PND;
__RW __u32 P2M_CLK_CON0;
__RW __u32 M2P_INT_IE;
__RW __u32 M2P_INT_SET;
__RW __u32 M2P_INT_CLR;
__RO __u32 M2P_INT_PND;
__RW __u32 P11_SYS_CON0;
__RW __u32 P11_SYS_CON1;
__RW __u32 PMU_KEY;
} P11_SYSTEM_TypeDef;
#define P11_SYSTEM_BASE (p11_sfr_base + map_adr(0x06, 0x00))
#define P11_SYSTEM ((P11_SYSTEM_TypeDef *)P11_SYSTEM_BASE)
//............. 0x0700 - 0x07ff............ for mbist
typedef struct {
__RW __u32 CON;
__RW __u32 SEL;
__RW __u32 BEG;
__RW __u32 END;
__RW __u32 DAT_VLD0;
__RW __u32 DAT_VLD1;
__RW __u32 DAT_VLD2;
__RW __u32 DAT_VLD3;
__RO __u32 ROM_CRC;
__RW __u32 MCFG0_RF1P;
__RW __u32 MCFG0_RF2P;
__RW __u32 MCFG0_RM1P;
__RW __u32 MCFG0_RM2P;
__RW __u32 MCFG0_VROM;
__RW __u32 MCFG0_CON[3];
} P11_MBIST_TypeDef;
#define P11_MBIST_BASE (p11_sfr_base + map_adr(0x07, 0x00))
#define P11_MBIST ((P11_MBIST_TypeDef *)P11_MBIST_BASE)
//............. 0x0800 - 0x08ff............ for watch dog
typedef struct {
__RW __u32 CON;
__RW __u32 KEY;
__RW __u32 DUMMY;
} P11_WDT_TypeDef;
#define P11_WDT_BASE (p11_sfr_base + map_adr(0x08, 0x00))
#define P11_WDT ((P11_WDT_TypeDef *)P11_WDT_BASE)
#define P11_SIM_END P11_WDT->DUMMY
//............. 0x0900 - 0x0cff............ for lp timer
typedef struct {
__RW __u32 CON0;
__RW __u32 CON1;
__RW __u32 CON2;
__RW __u32 PRD;
__RW __u32 RSC;
__RO __u32 CNT;
} P11_LPTMR_TypeDef;
#define P11_LPTMR0_BASE (p11_sfr_base + map_adr(0x09, 0x00))
#define P11_LPTMR1_BASE (p11_sfr_base + map_adr(0x0a, 0x00))
#define P11_LPTMR2_BASE (p11_sfr_base + map_adr(0x0b, 0x00))
#define P11_LPTMR3_BASE (p11_sfr_base + map_adr(0x0c, 0x00))
#define P11_LPTMR0 ((P11_LPTMR_TypeDef *)P11_LPTMR0_BASE)
#define P11_LPTMR1 ((P11_LPTMR_TypeDef *)P11_LPTMR1_BASE)
#define P11_LPTMR2 ((P11_LPTMR_TypeDef *)P11_LPTMR2_BASE)
#define P11_LPTMR3 ((P11_LPTMR_TypeDef *)P11_LPTMR3_BASE)
//............. 0x0d00 - 0x0dff............ for irflt
typedef struct {
__RW __u32 CON;
} P11_IRFLT_TypeDef;
#define P11_IRFLT_BASE (p11_sfr_base + map_adr(0x0d, 0x00))
#define P11_IRFLT ((P11_IRFLT_TypeDef *)P11_IRFLT_BASE)
//............. 0x0e00 - 0x0eff............ for spi
typedef struct {
__RW __u32 CON;
__RW __u32 BAUD;
__RW __u32 BUF;
__WO __u32 ADR;
__RW __u32 CNT;
__RW __u32 CON1;
} P11_SPI_TypeDef;
#define P11_SPI_BASE (p11_sfr_base + map_adr(0x0e, 0x00))
#define P11_SPI ((P11_SPI_TypeDef *)P11_SPI_BASE)
//............. 0x0f00 - 0x10ff............ for uart
typedef struct {
__RW __u16 CON0;
__RW __u16 CON1;
__RW __u16 CON2;
__RW __u16 BAUD;
__RW __u8 BUF;
__RW __u32 OTCNT;
//__RW __u32 TXADR;
//__WO __u16 TXCNT;
//__RW __u32 RXSADR;
//__RW __u32 RXEADR;
//__RW __u32 RXCNT;
//__RO __u16 HRXCNT;
//__RO __u16 RX_ERR_CNT;
} P11_UART_TypeDef;
#define P11_UART0_BASE (p11_sfr_base + map_adr(0x0f, 0x00))
#define P11_UART1_BASE (p11_sfr_base + map_adr(0x10, 0x00))
#define P11_UART0 ((P11_UART_TypeDef *)P11_UART0_BASE)
#define P11_UART1 ((P11_UART_TypeDef *)P11_UART1_BASE)
//............. 0x1100 - 0x11ff............ for iic
typedef struct {
__RW __u32 CON ;
__RW __u32 PND ;
__RW __u32 TX_BUF ;
__RW __u32 TASK ;
__RO __u32 RX_BUF ;
__RW __u32 ADDR ;
__RW __u32 BAUD ;
__RW __u32 TSU ;
__RW __u32 THD ;
__RO __u32 DBG ;
} P11_IIC_TypeDef;
#define P11_IIC_BASE (p11_sfr_base + map_adr(0x11, 0x00))
#define P11_IIC ((P11_IIC_TypeDef *)P11_IIC_BASE)
//............. 0x1200 - 0x12ff............ for port
typedef struct {
__RW __u32 OCH_CON0 ;
__RW __u32 ICH_CON0 ;
__RW __u32 P33_PORT ;
__RW __u32 PB_SEL ;
__RO __u32 PB_IN ;
__RW __u32 PB_OUT ;
__RW __u32 PB_DIR ;
__RW __u32 PB_DIE ;
__RW __u32 PB_DIEH ;
__RW __u32 PB_PU0 ;
__RW __u32 PB_PU1 ;
__RW __u32 PB_PD0 ;
__RW __u32 PB_PD1 ;
__RW __u32 PB_HD0 ;
__RW __u32 PB_HD1 ;
__RW __u32 PB_SPL ;
} P11_PORT_TypeDef;
#define P11_PORT_BASE (p11_sfr_base + map_adr(0x12, 0x00))
#define P11_PORT ((P11_PORT_TypeDef *)P11_PORT_BASE)
//............. 0x1300 - 0x14ff............ for lp ctmu
typedef struct {
__RW __u32 CON0 ;
__RW __u32 CHEN ;
__RW __u32 CNUM ;
__RW __u32 PPRD ;
__RW __u32 DPRD ;
__RW __u32 ECON ;
__RW __u32 EXEN ;
__RW __u32 CHIS ;
__RW __u32 CLKC ;
__WO __u32 WCON ;
__RW __u32 ANA0 ;
__RW __u32 ANA1 ;
__RO __u32 RES ;
__RW __u32 DMA_START_ADR;
__RW __u32 DMA_HALF_ADR;
__RW __u32 DMA_END_ADR;
__RW __u32 DMA_CON;
__RW __u32 MSG_CON;
__RO __u32 DMA_WADR;
__RW __u32 SLEEP_CON;
} P11_LPCTM_TypeDef;
#define P11_LPCTM0_BASE (p11_sfr_base + map_adr(0x13, 0x00))
#define P11_LPCTM0 ((P11_LPCTM_TypeDef *)P11_LPCTM0_BASE)
// #define P11_LPCTM1_BASE (p11_sfr_base + map_adr(0x14, 0x00))
// #define P11_LPCTM1 ((P11_LPCTM_TypeDef *)P11_LPCTM1_BASE)
//............. 0x1500 - 0x15ff............ for lpvad
typedef struct {
__RW __u32 VAD_CON;
__RW __u32 VAD_ACON0;
__RW __u32 VAD_ACON1;
__RW __u32 AVAD_CON;
__RW __u32 AVAD_DATA;
__RW __u32 DVAD_CON0;
__RW __u32 DVAD_CON1;
__RW __u32 DMA_BADR;
__RW __u32 DMA_LEN;
__RW __u32 DMA_HPTR;
__RW __u32 DMA_SPTR;
__RW __u32 DMA_SPN;
__RW __u32 DMA_SHN;
} P11_LPVAD_TypeDef;
#define P11_LPVAD_BASE (p11_sfr_base + map_adr(0x15, 0x00))
#define P11_LPVAD ((P11_LPVAD_TypeDef *)P11_LPVAD_BASE)
//............. 0x1600 - 0x17ff............ for crossbar
#include "p11_io_omap.h"
#include "p11_io_imap.h"
//............. 0x1800 - 0x19ff............ for gp timer
typedef struct {
__RW __u32 CON;
__RW __u32 CNT;
__RW __u32 PRD;
__RW __u32 PWM;
__RW __u32 IRFLT;
} P11_GPTMR_TypeDef;
#define P11_GPTMR0_BASE (p11_sfr_base + map_adr(0x18, 0x00))
#define P11_GPTMR1_BASE (p11_sfr_base + map_adr(0x18, 0x05))
#define P11_GPTMR0 ((P11_GPTMR_TypeDef *)P11_GPTMR0_BASE)
#define P11_GPTMR1 ((P11_GPTMR_TypeDef *)P11_GPTMR1_BASE)
//............. 0x1a00 - 0x1aff............ for NFC
typedef struct {
__RW __u32 CON0;
__RW __u32 CON1;
__RW __u32 CON2;
__RW __u32 CON3;
__RW __u32 BUF0;
__RW __u32 BUF1;
__RW __u32 BUF2;
__RW __u32 BUF3;
} P11_NFC_TypeDef;
#define P11_NFC_BASE (p11_sfr_base + map_adr(0x1a, 0x00))
#define P11_NFC ((P11_NFC_TypeDef *)P11_NFC_BASE)
//............. 0x1b00 - 0x1bff............ for RESLOCK
typedef struct {
__RW __u32 LOCK[16];
} P11_RESLOCK_TypeDef;
#define P11_RESLOCK_BASE (p11_sfr_base + map_adr(0x1b,0x00))
#define P11_RESLOCK ((P11_RESLOCK_TypeDef *)P11_RESLOCK_BASE)
//............. 0x1c00 - 0x1cff............ for lp_gpcnt0
typedef struct {
__RW __u32 CON;
__RO __u32 NUM;
} P11_GPCNT_TypeDef;
#define P11_GPCNT0_BASE (p11_sfr_base + map_adr(0x1c, 0x00))
#define P11_GPCNT0 ((P11_GPCNT_TypeDef *)P11_GPCNT0_BASE)
#endif
SDK/interface/driver/cpu/br35/asm/power/p33/charge_hw.h
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#ifndef __CHARGE_HW_H__
#define __CHARGE_HW_H__
/************************P3_ANA_MFIX*****************************/
#define PMU_MFIXI_SET_1(en) p33_fast_access(P3_ANA_MFIX, BIT(1), en)
/************************P3_CHG_CON0*****************************/
#define CHARGE_EN(en) p33_fast_access(P3_CHG_CON0, BIT(0), en)
#define CHGGO_EN(en) p33_fast_access(P3_CHG_CON0, BIT(1), en)
#define IS_CHARGE_EN() ((P33_CON_GET(P3_CHG_CON0) & BIT(0)) ? 1: 0 )
#define CHG_HV_MODE(mode) p33_fast_access(P3_CHG_CON0, BIT(2), mode)
#define CHG_TRICKLE_EN(en) p33_fast_access(P3_CHG_CON0, BIT(3), en)
#define CHG_CCLOOP_EN(en) p33_fast_access(P3_CHG_CON0, BIT(4), en)
#define CHG_VILOOP_EN(en) p33_fast_access(P3_CHG_CON0, BIT(5), en)
#define CHG_VILOOP2_EN(en) p33_fast_access(P3_CHG_CON0, BIT(6), en)
#define CHG_VINLOOP_SLT(sel) p33_fast_access(P3_CHG_CON0, BIT(7), sel)
/************************P3_CHG_CON1*****************************/
#define CHARGE_mA_SEL(a) P33_CON_SET(P3_CHG_CON1, 0, 4, a)
/************************P3_CHG_CON2*****************************/
#define CHARGE_FULL_V_SEL(a) P33_CON_SET(P3_CHG_CON2, 4, 4, a)
/************************P3_CHG_CON3*****************************/
#define CHARGE_FOLLOWC_SLT(en) p33_fast_access(P3_CHG_CON3, BIT(3), en)
enum {
CHARGE_DET_VOL_365V,
CHARGE_DET_VOL_375V,
CHARGE_DET_VOL_385V,
CHARGE_DET_VOL_395V,
};
#define CHARGE_DET_VOL(a) P33_CON_SET(P3_CHG_CON3, 1, 2, a)
#define CHARGE_DET_EN(en) p33_fast_access(P3_CHG_CON3, BIT(0), en)
/************************P3_CHG_CON4*****************************/
#define CHGI_TRIM_SEL(a) P33_CON_SET(P3_CHG_CON4, 0, 4, a)
/************************P3_VPWR_CON0*****************************/
#define L5V_IO_MODE(a) p33_fast_access(P3_VPWR_CON0, BIT(2), a)
#define IS_L5V_LOAD_EN() ((P33_CON_GET(P3_VPWR_CON0) & BIT(0)) ? 1: 0)
#define L5V_LOAD_EN(a) p33_fast_access(P3_VPWR_CON0, BIT(0), a)
/************************P3_VPWR_CON1*****************************/
#define L5V_RES_DET_S_SEL(a) P33_CON_SET(P3_VPWR_CON1, 0, 2, a)
#define GET_L5V_RES_DET_S_SEL() (P33_CON_GET(P3_VPWR_CON1) & 0x03)
/************************P3_ANA_FLOW2*****************************/
#define PMU_NVDC_EN(a) p33_fast_access(P3_ANA_FLOW2, BIT(4), a)
/************************P3_AWKUP_LEVEL*****************************/
#define VBAT_DET_FILTER_GET() ((P33_CON_GET(P3_AWKUP_LEVEL) & BIT(2)) ? 1: 0)
#define LVCMP_DET_FILTER_GET() ((P33_CON_GET(P3_AWKUP_LEVEL) & BIT(1)) ? 1: 0)
#define LDO5V_DET_FILTER_GET() ((P33_CON_GET(P3_AWKUP_LEVEL) & BIT(0)) ? 1: 0)
/************************P3_ANA_READ*****************************/
#define VBAT_DET_GET() ((P33_CON_GET(P3_ANA_READ) & BIT(0)) ? 1: 0 )
#define LVCMP_DET_GET() ((P33_CON_GET(P3_ANA_READ) & BIT(1)) ? 1: 0 )
#define LDO5V_DET_GET() ((P33_CON_GET(P3_ANA_READ) & BIT(2)) ? 1: 0 )
#endif
SDK/interface/driver/cpu/br35/asm/power/p33/p33_access.h
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#ifndef __P33_ACCESS_H__
#define __P33_ACCESS_H__
//
//
// for p33 access
//
//
//
/**************************************************************/
//ROM
u8 p33_buf(u8 buf);
#define p33_xor_1byte(addr, data0) (*((volatile u8 *)&addr + 0x300*4) = data0); asm volatile ("csync")
//#define p33_xor_1byte(addr, data0) (*((volatile u8 *)&addr + 0x300*4) = data0)
// #define p33_xor_1byte(addr, data0) addr ^= (data0)
#define p33_or_1byte(addr, data0) (*((volatile u8 *)&addr + 0x200*4) = data0); asm volatile ("csync")
//#define p33_or_1byte(addr, data0) (*((volatile u8 *)&addr + 0x200*4) = data0)
// #define p33_or_1byte(addr, data0) addr |= (data0)
#define p33_and_1byte(addr, data0) (*((volatile u8 *)&addr + 0x100*4) = (data0)); asm volatile ("csync")
//#define p33_and_1byte(addr, data0) (*((volatile u8 *)&addr + 0x100*4) = (data0))
//#define p33_and_1byte(addr, data0) addr &= (data0)
// void p33_tx_1byte(u16 addr, u8 data0);
#define p33_tx_1byte(addr, data0) addr = data0
// u8 p33_rx_1byte(u16 addr);
#define p33_rx_1byte(addr) addr
#define P33_CON_SET(sfr, start, len, data) (sfr = (sfr & ~((~(0xff << (len))) << (start))) | \
(((data) & (~(0xff << (len)))) << (start)))
#define P33_CON_GET(sfr) (sfr)
#if 1
#define p33_fast_access(reg, data, en) \
{ \
if (en) { \
p33_or_1byte(reg, (data)); \
} else { \
p33_and_1byte(reg, (u8)~(data)); \
} \
}
#else
#define p33_fast_access(reg, data, en) \
{ \
if (en) { \
reg |= (data); \
} else { \
reg &= ~(data); \
} \
}
#endif
#endif
SDK/interface/driver/cpu/br35/asm/power/p33/p33_api.h
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#ifndef __P33_API_H__
#define __P33_API_H__
//
//
// vol
//
//
//
/****************************************************************/
enum DVDD_VOL {
DVDD_VOL_0840MV = 0,
DVDD_VOL_0870MV,
DVDD_VOL_0900MV,
DVDD_VOL_0930MV,
DVDD_VOL_0960MV,
DVDD_VOL_0990MV,
DVDD_VOL_1020MV,
DVDD_VOL_1050MV,
DVDD_VOL_1080MV,
DVDD_VOL_1110MV,
DVDD_VOL_1140MV,
DVDD_VOL_1170MV,
DVDD_VOL_1200MV,
DVDD_VOL_1230MV,
DVDD_VOL_1260MV,
DVDD_VOL_1290MV,
};
/*enum DVDD2_VOL {*/
/*};*/
/*enum RVDD_VOL {*/
/*};*/
/*enum RVDD2_VOL {*/
/*};*/
/*enum BTVDD_VOL {*/
/*};*/
enum DCVDD_VOL {
DCVDD_VOL_1000MV = 0,
DCVDD_VOL_1050MV,
DCVDD_VOL_1100MV,
DCVDD_VOL_1150MV,
DCVDD_VOL_1200MV,
DCVDD_VOL_1250MV,
DCVDD_VOL_1300MV,
DCVDD_VOL_1350MV,
DCVDD_VOL_1400MV,
DCVDD_VOL_1450MV,
DCVDD_VOL_1500MV,
DCVDD_VOL_1550MV,
DCVDD_VOL_1600MV,
};
enum VDDIOM_VOL {
VDDIOM_VOL_21V = 0,
VDDIOM_VOL_22V,
VDDIOM_VOL_23V,
VDDIOM_VOL_24V,
VDDIOM_VOL_25V,
VDDIOM_VOL_26V,
VDDIOM_VOL_27V,
VDDIOM_VOL_28V,
VDDIOM_VOL_29V,
VDDIOM_VOL_30V,
VDDIOM_VOL_31V,
VDDIOM_VOL_32V,
VDDIOM_VOL_33V,
VDDIOM_VOL_34V,
VDDIOM_VOL_35V,
VDDIOM_VOL_36V,
};
enum VDDIOW_VOL {
VDDIOW_VOL_21V = 0,
VDDIOW_VOL_22V,
VDDIOW_VOL_23V,
VDDIOW_VOL_24V,
VDDIOW_VOL_25V,
VDDIOW_VOL_26V,
VDDIOW_VOL_27V,
VDDIOW_VOL_28V,
VDDIOW_VOL_29V,
VDDIOW_VOL_30V,
VDDIOW_VOL_31V,
VDDIOW_VOL_32V,
VDDIOW_VOL_33V,
VDDIOW_VOL_34V,
VDDIOW_VOL_35V,
VDDIOW_VOL_36V,
};
enum WVDD_VOL {
WVDD_VOL_0500MV = 0,
WVDD_VOL_0550MV,
WVDD_VOL_0600MV,
WVDD_VOL_0650MV,
WVDD_VOL_0700MV,
WVDD_VOL_0750MV,
WVDD_VOL_0800MV,
WVDD_VOL_0850MV,
WVDD_VOL_0900MV,
WVDD_VOL_0950MV,
WVDD_VOL_1000MV,
WVDD_VOL_1050MV,
WVDD_VOL_1100MV,
WVDD_VOL_1150MV,
WVDD_VOL_1200MV,
WVDD_VOL_1250MV,
};
enum PVDD_VOL {
PVDD_VOL_0500MV = 0,
PVDD_VOL_0550MV,
PVDD_VOL_0600MV,
PVDD_VOL_0650MV,
PVDD_VOL_0700MV,
PVDD_VOL_0750MV,
PVDD_VOL_0800MV,
PVDD_VOL_0850MV,
PVDD_VOL_0900MV,
PVDD_VOL_0950MV,
PVDD_VOL_1000MV,
PVDD_VOL_1050MV,
PVDD_VOL_1100MV,
PVDD_VOL_1150MV,
PVDD_VOL_1200MV,
PVDD_VOL_1250MV,
};
void dvdd_vol_sel(enum DVDD_VOL vol);
enum DVDD_VOL get_dvdd_vol_sel();
/*void dvdd2_vol_sel(enum DVDD2_VOL vol);*/
/*enum DVDD2_VOL get_dvdd2_vol_sel();*/
/*void rvdd_vol_sel(enum RVDD_VOL vol);*/
/*enum RVDD_VOL get_rvdd_vol_sel();*/
/*void rvdd2_vol_sel(enum RVDD2_VOL vol);*/
/*enum RVDD2_VOL get_rvdd2_vol_sel();*/
void dcvdd_vol_sel(enum DCVDD_VOL vol);
enum DCVDD_VOL get_dcvdd_vol_sel();
/*void btvdd_vol_sel(enum BTVDD_VOL vol);*/
/*enum BTVDD_VOL get_btvdd_vol_sel();*/
void pvdd_config(u32 lev, u32 low_lev, u32 output);
void pvdd_output(u32 output);
void vddiom_vol_sel(enum VDDIOM_VOL vol);
enum VDDIOM_VOL get_vddiom_vol_sel();
void vddiow_vol_sel(enum VDDIOW_VOL vol);
enum VDDIOW_VOL get_vddiow_vol_sel();
u32 get_vddiom_vol();
//
//
// lvd
//
//
//
/****************************************************************/
typedef enum {
LVD_RESET_MODE, //复位模式
LVD_EXCEPTION_MODE, //异常模式，进入异常中断
LVD_WAKEUP_MODE, //唤醒模式，进入唤醒中断，callback参数为回调函数
} LVD_MODE;
typedef enum {
VLVD_SEL_166V = 0,
VLVD_SEL_177V,
VLVD_SEL_188V,
VLVD_SEL_199V,
VLVD_SEL_210V,
VLVD_SEL_221V,
VLVD_SEL_232V,
VLVD_SEL_243V,
VLVD_SEL_254V,
VLVD_SEL_265V,
VLVD_SEL_276V,
VLVD_SEL_287V,
VLVD_SEL_298V,
VLVD_SEL_309V,
VLVD_SEL_320V,
VLVD_SEL_331V,
} LVD_VOL;
void lvd_en(u8 en);
void lvd_config(LVD_VOL vol, u8 expin_en, LVD_MODE mode, void (*callback));
//
//
// pinr
//
//
//
//******************************************************************
void gpio_longpress_pin0_reset_config(u32 pin, u32 level, u32 time, u32 release, u32 pull_enable, u32 latch_en);
void gpio_longpress_pin1_reset_config(u32 pin, u32 level, u32 time, u32 release);
//
//
// dcdc
//
//
//
//******************************************************************
enum POWER_MODE {
//LDO模式
PWR_LDO15,
//DCDC模式
PWR_DCDC15,
};
enum POWER_DCDC_TYPE {
PWR_DCDC12 = 2,
PWR_DCDC18_DCDC12 = 6,
PWR_DCDC18_DCDC12_DCDC09 = 7,
};
enum {
DCDC09 = 1,
DCDC12 = 2,
DCDC18 = 4,
};
void power_set_dcdc_type(enum POWER_DCDC_TYPE type);
void power_set_mode(enum POWER_MODE mode);
enum DVD_SHORT_DCV_MODE {
DVDD_SHORT_DCVDDDIS = 0,
DVDD_SHORT_DCVDD_EN,
};
void dcvdd_level_cfg(u8 dcvdd_level_set);
void dvdd_short_dcvdd(enum DVD_SHORT_DCV_MODE short_mode, u8 dcvdd_level_set);
//每个滤波参数不一样
#define MAX_WAKEUP_PORT 8 //最大同时支持数字io输入个数
#define MAX_WAKEUP_ANA_PORT 3 //最大同时支持模拟io输入个数
#endif
SDK/interface/driver/cpu/br35/asm/power/p33/p33_sfr.h
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#ifndef __P33_SFR_H__
#define __P33_SFR_H__
//#ifdef PMU_SYSTEM
#if 0
#define P33_ACCESS(x) (*(volatile u32 *)(0xc000 + x*4))
#else
#define P33_ACCESS(x) (*(volatile u32 *)(0xf20000 + 0xc000 + x*4))
#endif
//#ifdef PMU_SYSTEM
#if 0
#define RTC_ACCESS(x) (*(volatile u32 *)(0xd000 + x*4))
#else
#define RTC_ACCESS(x) (*(volatile u32 *)(0xf20000 + 0xd000 + x*4))
#endif
//===========
//===============================================================================//
//
//
//
//===============================================================================//
//............. 0x0000 - 0x000f............
//#define P3_VLMT_CON P33_ACCESS(0x01)
//#define P3_POR_CON P33_ACCESS(0x02)
#define P3_VLVD_CON0 P33_ACCESS(0x03)
#define P3_VLVD_CON1 P33_ACCESS(0x04)
#define P3_VLVD_FLT P33_ACCESS(0x05)
#define P3_WDT_CON P33_ACCESS(0x06)
#define P3_OCP_CON0 P33_ACCESS(0x07)
#define P3_ANA_FLOW0 P33_ACCESS(0x08)
#define P3_ANA_FLOW1 P33_ACCESS(0x09)
#define P3_ANA_FLOW2 P33_ACCESS(0x0a)
#define P3_ANA_KEEP0 P33_ACCESS(0x0c)
#define P3_ANA_KEEP1 P33_ACCESS(0x0d)
#define P3_ANA_KEEP2 P33_ACCESS(0x0e)
//............. 0X0010 - 0X001F.........for analog others
#define P3_OSL_CON P33_ACCESS(0x10)
#define P3_RST_FLAG P33_ACCESS(0x11)
#define P3_VBAT_TYPE P33_ACCESS(0x12)
#define P3_LRC_CON0 P33_ACCESS(0x13)
#define P3_LRC_CON1 P33_ACCESS(0x14)
#define P3_RST_CON0 P33_ACCESS(0x15)
#define P3_RST_CON1 P33_ACCESS(0x16)
#define P3_RST_CON2 P33_ACCESS(0x17)
#define P3_VLD_KEEP P33_ACCESS(0x18)
#define P3_CLK_CON0 P33_ACCESS(0x19)
#define P3_ANA_READ P33_ACCESS(0x1a)
#define P3_CHG_CON0 P33_ACCESS(0x1b)
#define P3_CHG_CON1 P33_ACCESS(0x1c)
#define P3_CHG_CON2 P33_ACCESS(0x1d)
#define P3_CHG_CON3 P33_ACCESS(0x1e)
#define P3_CHG_CON4 P33_ACCESS(0x1f)
//............. 0X0020 - 0X002F............ for buck circuit
//#define P3_BUCK1_CON0 P33_ACCESS(0x20)
//#define P3_BUCK1_CON1 P33_ACCESS(0x21)
//#define P3_BUCK1_CON2 P33_ACCESS(0x22)
//#define P3_BUCK1_CON3 P33_ACCESS(0x23)
//#define P3_BUCK1_CON4 P33_ACCESS(0x24)
//#define P3_BUCK1_CON5 P33_ACCESS(0x25)
//#define P3_BUCK1_CON6 P33_ACCESS(0x26)
//#define P3_BUCK1_CON7 P33_ACCESS(0x27)
#define P3_BUCK2_CON0 P33_ACCESS(0x20)
#define P3_BUCK2_CON1 P33_ACCESS(0x21)
#define P3_BUCK2_CON2 P33_ACCESS(0x22)
#define P3_BUCK2_CON3 P33_ACCESS(0x23)
#define P3_BUCK2_CON4 P33_ACCESS(0x24)
#define P3_BUCK2_CON5 P33_ACCESS(0x25)
#define P3_BUCK2_CON6 P33_ACCESS(0x26)
#define P3_BUCK2_CON7 P33_ACCESS(0x27)
//#define P3_BUCK3_CON0 P33_ACCESS(0x28)
//#define P3_BUCK3_CON1 P33_ACCESS(0x29)
//#define P3_BUCK3_CON2 P33_ACCESS(0x2a)
//#define P3_BUCK3_CON3 P33_ACCESS(0x2b)
//#define P3_BUCK3_CON4 P33_ACCESS(0x2c)
//#define P3_BUCK3_CON5 P33_ACCESS(0x2d)
//#define P3_BUCK3_CON6 P33_ACCESS(0x2e)
//#define P3_BUCK3_CON7 P33_ACCESS(0x2f)
//............. 0X0030 - 0X003F............ for PMU manager
#define P3_SFLAG0 P33_ACCESS(0x30)
#define P3_SFLAG1 P33_ACCESS(0x31)
#define P3_SFLAG2 P33_ACCESS(0x32)
#define P3_SFLAG3 P33_ACCESS(0x33)
#define P3_SFLAG4 P33_ACCESS(0x34)
#define P3_SFLAG5 P33_ACCESS(0x35)
#define P3_SFLAG6 P33_ACCESS(0x36)
#define P3_SFLAG7 P33_ACCESS(0x37)
#define P3_SFLAG8 P33_ACCESS(0x38)
#define P3_SFLAG9 P33_ACCESS(0x39)
#define P3_SFLAGA P33_ACCESS(0x3a)
#define P3_SFLAGB P33_ACCESS(0x3b)
//............. 0X0040 - 0X004F............ for
#define P3_IVS_RD P33_ACCESS(0x40)
#define P3_IVS_SET P33_ACCESS(0x41)
#define P3_IVS_CLR P33_ACCESS(0x42)
#define P3_PVDD0_AUTO P33_ACCESS(0x43)
#define P3_PVDD1_AUTO P33_ACCESS(0x44)
#define P3_WKUP_DLY P33_ACCESS(0x45)
#define P3_PCNT_FLT P33_ACCESS(0x48)
#define P3_PCNT_CON P33_ACCESS(0x49)
#define P3_PCNT_SET0 P33_ACCESS(0x4a)
#define P3_PCNT_SET1 P33_ACCESS(0x4b)
#define P3_PCNT_DAT0 P33_ACCESS(0x4c)
#define P3_PCNT_DAT1 P33_ACCESS(0x4d)
#define P3_P11_CPU P33_ACCESS(0x4f)
//............. 0X0050 - 0X005F............ for port wake up
#define P3_WKUP_FLT_EN0 P33_ACCESS(0x50)
#define P3_WKUP_P_IE0 P33_ACCESS(0x51)
#define P3_WKUP_N_IE0 P33_ACCESS(0x52)
#define P3_WKUP_LEVEL0 P33_ACCESS(0x53)
#define P3_WKUP_P_CPND0 P33_ACCESS(0x54)
#define P3_WKUP_N_CPND0 P33_ACCESS(0x55)
#define P3_WKUP_P_PND0 P33_ACCESS(0x56)
#define P3_WKUP_N_PND0 P33_ACCESS(0x57)
#define P3_WKUP_FLT_EN1 P33_ACCESS(0x58)
#define P3_WKUP_P_IE1 P33_ACCESS(0x59)
#define P3_WKUP_N_IE1 P33_ACCESS(0x5a)
#define P3_WKUP_LEVEL1 P33_ACCESS(0x5b)
#define P3_WKUP_P_CPND1 P33_ACCESS(0x5c)
#define P3_WKUP_N_CPND1 P33_ACCESS(0x5d)
#define P3_WKUP_P_PND1 P33_ACCESS(0x5e)
#define P3_WKUP_N_PND1 P33_ACCESS(0x5f)
//............. 0X0060 - 0X006F............ for analog wake up
#define P3_AWKUP_FLT_EN P33_ACCESS(0x60)
#define P3_AWKUP_P_IE P33_ACCESS(0x61)
#define P3_AWKUP_N_IE P33_ACCESS(0x62)
#define P3_AWKUP_LEVEL P33_ACCESS(0x63)
#define P3_AWKUP_P_PND P33_ACCESS(0x64)
#define P3_AWKUP_N_PND P33_ACCESS(0x65)
#define P3_AWKUP_P_CPND P33_ACCESS(0x66)
#define P3_AWKUP_N_CPND P33_ACCESS(0x67)
#define P3_WKUP_CLK_SEL P33_ACCESS(0x68)
#define P3_AWKUP_CLK_SEL P33_ACCESS(0x69)
#define P3_SYS_PWR0 P33_ACCESS(0x6a)
#define P3_SYS_PWR1 P33_ACCESS(0x6b)
#define P3_SYS_PWR2 P33_ACCESS(0x6c)
#define P3_SYS_PWR3 P33_ACCESS(0x6d)
#define P3_SYS_PWR4 P33_ACCESS(0x6e)
#define P3_SYS_PWR5 P33_ACCESS(0x6f)
//............. 0X0070 - 0X007F............ for
#define P3_PGDR_CON0 P33_ACCESS(0x70)
#define P3_PGDR_CON1 P33_ACCESS(0x71)
#define P3_PGSD_CON P33_ACCESS(0x72)
#define P3_LP_CTL P33_ACCESS(0x74)
#define P3_LP_CFG P33_ACCESS(0x75)
#define P3_NVRAM_PWR P33_ACCESS(0x76)
#define P3_WVD_CON0 P33_ACCESS(0x77)
#define P3_PVD_CON0 P33_ACCESS(0x78)
#define P3_EVD_CON0 P33_ACCESS(0x79)
#define P3_PMU_CON0 P33_ACCESS(0x7a)
#define P3_PMU_CON4 P33_ACCESS(0x7e)
#define P3_PMU_CON5 P33_ACCESS(0x7f)
//............. 0X0080 - 0X008F............ for
#define P3_PINR_CON P33_ACCESS(0x80)
#define P3_PINR_CON1 P33_ACCESS(0x81)
#define P3_PINR_SAFE P33_ACCESS(0x82)
#define P3_PINR_SAFE1 P33_ACCESS(0x83)
#define P3_PINR_PND1 P33_ACCESS(0x84)
#define P3_RST_SRC0 P33_ACCESS(0x8e)
#define P3_RST_SRC1 P33_ACCESS(0x8f)
//............. 0X0090 - 0X009F............ for
#define P3_PSW_CON0 P33_ACCESS(0x90)
#define P3_PSW_CON1 P33_ACCESS(0x91)
#define P3_PSW_CON2 P33_ACCESS(0x92)
#define P3_PMU_ADC0 P33_ACCESS(0x93)
#define P3_PMU_ADC1 P33_ACCESS(0x94)
#define P3_VBG_CON0 P33_ACCESS(0x95)
#define P3_VBG_CON1 P33_ACCESS(0x96)
#define P3_IOV_CON0 P33_ACCESS(0x97)
#define P3_IOV_CON1 P33_ACCESS(0x98)
#define P3_PAVD_CON0 P33_ACCESS(0x99)
#define P3_DCV_CON0 P33_ACCESS(0x9a)
#define P3_DVD_CON0 P33_ACCESS(0x9b)
#define P3_DVD2_CON0 P33_ACCESS(0x9c)
#define P3_RVD_CON0 P33_ACCESS(0x9d)
#define P3_RVD_CON1 P33_ACCESS(0x9e)
#define P3_RVD2_CON0 P33_ACCESS(0x9f)
//............. 0X00A0 - 0X00AF............
#define P3_PR_PWR P33_ACCESS(0xa0)
#define P3_VPWR_CON0 P33_ACCESS(0xa1)
#define P3_VPWR_CON1 P33_ACCESS(0xa2)
#define P3_RTC_ADC0 P33_ACCESS(0xa3)
#define P3_LS_P11 P33_ACCESS(0xa4)
#define P3_LS_EN P33_ACCESS(0xa5)
#define P3_EXT_EFUSE_CON P33_ACCESS(0xa6)
#define P3_WKUP_SRC P33_ACCESS(0xa8)
#define P3_ANA_MFIX P33_ACCESS(0xa9)
#define P3_DBG_CON0 P33_ACCESS(0xaa)
#define P3_DBG_CON1 P33_ACCESS(0xab)
#define P3_MFIX_OPT P33_ACCESS(0xac)
//............. 0X00B0 - 0X00BF............ for EFUSE
#define P3_EFUSE_CON0 P33_ACCESS(0xb0)
#define P3_EFUSE_CON1 P33_ACCESS(0xb1)
#define P3_EFUSE_CON2 P33_ACCESS(0xb2)
#define P3_EFUSE_RDAT P33_ACCESS(0xb3)
#define P3_EFUSE_PU_DAT0 P33_ACCESS(0xb4)
#define P3_EFUSE_PU_DAT1 P33_ACCESS(0xb5)
#define P3_EFUSE_PU_DAT2 P33_ACCESS(0xb6)
#define P3_EFUSE_PU_DAT3 P33_ACCESS(0xb7)
#define P3_FUNC_EN P33_ACCESS(0xb8)
#define P3_FUNC_CTL0 P33_ACCESS(0xb9)
#define P3_FUNC_CTL1 P33_ACCESS(0xba)
#define P3_FUNC_CTL2 P33_ACCESS(0xbb)
#define P3_EFUSE_ANA0 P33_ACCESS(0xbc)
//............. 0X00C0 - 0X00CF............ for port input select
#define P3_PORT_SEL0 P33_ACCESS(0xc0)
#define P3_PORT_SEL1 P33_ACCESS(0xc1)
#define P3_PORT_SEL2 P33_ACCESS(0xc2)
#define P3_PORT_SEL3 P33_ACCESS(0xc3)
#define P3_PORT_SEL4 P33_ACCESS(0xc4)
#define P3_PORT_SEL5 P33_ACCESS(0xc5)
#define P3_PORT_SEL6 P33_ACCESS(0xc6)
#define P3_PORT_SEL7 P33_ACCESS(0xc7)
//............. 0x00d0 - 0x00df............
#define P3_LS_IO_USR P33_ACCESS(0xd0) //TODO: check sync with verilog head file chip_def.v LEVEL_SHIFTER
#define P3_LS_IO_ROM P33_ACCESS(0xd1)
#define P3_LS_IO_PINR P33_ACCESS(0xd2)
#define P3_LS_CTMU P33_ACCESS(0xd3)
#define P3_LS_IO_SHA P33_ACCESS(0xd4)
#define P3_LS_LRC24M P33_ACCESS(0xd5)
#define P3_LS_BT P33_ACCESS(0xd6)
#define P3_LS_PLL P33_ACCESS(0xd7)
//............. 0X00E0 - 0X00FF............ for p33 lp timer
#define P3_LP_RSC00 P33_ACCESS(0xe0)
#define P3_LP_RSC01 P33_ACCESS(0xe1)
#define P3_LP_RSC02 P33_ACCESS(0xe2)
#define P3_LP_RSC03 P33_ACCESS(0xe3)
#define P3_LP_PRD00 P33_ACCESS(0xe4)
#define P3_LP_PRD01 P33_ACCESS(0xe5)
#define P3_LP_PRD02 P33_ACCESS(0xe6)
#define P3_LP_PRD03 P33_ACCESS(0xe7)
#define P3_LP_RSC10 P33_ACCESS(0xe8)
#define P3_LP_RSC11 P33_ACCESS(0xe9)
#define P3_LP_RSC12 P33_ACCESS(0xea)
#define P3_LP_RSC13 P33_ACCESS(0xeb)
#define P3_LP_RSC14 P33_ACCESS(0xec)
#define P3_LP_RSC15 P33_ACCESS(0xed)
#define P3_LP_PRD10 P33_ACCESS(0xee)
#define P3_LP_PRD11 P33_ACCESS(0xef)
#define P3_LP_PRD12 P33_ACCESS(0xf0)
#define P3_LP_PRD13 P33_ACCESS(0xf1)
#define P3_LP_PRD14 P33_ACCESS(0xf2)
#define P3_LP_PRD15 P33_ACCESS(0xf3)
#define P3_LP_TMR0_CLK P33_ACCESS(0xf4)
#define P3_LP_TMR1_CLK P33_ACCESS(0xf5)
#define P3_LP_TMR0_CON P33_ACCESS(0xf6)
#define P3_LP_TMR1_CON P33_ACCESS(0xf7)
#define P3_LP_TMR_CFG P33_ACCESS(0xf8)
#define P3_LP_CNTRD0 P33_ACCESS(0xf9)
#define P3_LP_CNT0 P33_ACCESS(0xfa)
#define P3_LP_CNT1 P33_ACCESS(0xfb)
#define P3_LP_CNT2 P33_ACCESS(0xfc)
#define P3_LP_CNT3 P33_ACCESS(0xfd)
#define P3_LP_CNT4 P33_ACCESS(0xfe)
#define P3_LP_CNT5 P33_ACCESS(0xff)
//===============================================================================//
//
// P33 RTCVDD
//
//===============================================================================//
//............. 0X0080 - 0X008F............ for RTC
#define R3_ALM_CON RTC_ACCESS(0x80)
#define R3_RTC_CON0 RTC_ACCESS(0x84)
#define R3_RTC_CON1 RTC_ACCESS(0x85)
#define R3_RTC_DAT0 RTC_ACCESS(0x86)
#define R3_RTC_DAT1 RTC_ACCESS(0x87)
#define R3_RTC_DAT2 RTC_ACCESS(0x88)
#define R3_RTC_DAT3 RTC_ACCESS(0x89)
#define R3_RTC_DAT4 RTC_ACCESS(0x8a)
#define R3_ALM_DAT0 RTC_ACCESS(0x8b)
#define R3_ALM_DAT1 RTC_ACCESS(0x8c)
#define R3_ALM_DAT2 RTC_ACCESS(0x8d)
#define R3_ALM_DAT3 RTC_ACCESS(0x8e)
#define R3_ALM_DAT4 RTC_ACCESS(0x8f)
//............. 0X0090 - 0X009F............ for wake up
#define R3_WKUP_EN RTC_ACCESS(0x90)
#define R3_WKUP_EDGE RTC_ACCESS(0x91)
#define R3_WKUP_CPND RTC_ACCESS(0x92)
#define R3_WKUP_PND RTC_ACCESS(0x93)
#define R3_WKUP_LEVEL RTC_ACCESS(0x94)
//............. 0X00A0 - 0X00AF............ for system
#define R3_TIME_CON RTC_ACCESS(0xa0)
#define R3_TIME_CPND RTC_ACCESS(0xa1)
#define R3_TIME_PND RTC_ACCESS(0xa2)
#define R3_ADC_CON RTC_ACCESS(0xa4)
#define R3_OSL_CON RTC_ACCESS(0xa5)
#define R3_WKUP_SRC RTC_ACCESS(0xa8)
#define R3_RST_SRC RTC_ACCESS(0xa9)
#define R3_RST_CON RTC_ACCESS(0xab)
#define R3_CLK_CON RTC_ACCESS(0xac)
//............. 0X00B0 - 0X00BF............ for PORT control
#define R3_PR_IN RTC_ACCESS(0xb0)
#define R3_PR_OUT RTC_ACCESS(0xb1)
#define R3_PR_DIR RTC_ACCESS(0xb2)
#define R3_PR_DIE RTC_ACCESS(0xb3)
#define R3_PR_PU0 RTC_ACCESS(0xb4)
#define R3_PR_PU1 RTC_ACCESS(0xb5)
#define R3_PR_PD0 RTC_ACCESS(0xb6)
#define R3_PR_PD1 RTC_ACCESS(0xb7)
#define R3_PR_HD0 RTC_ACCESS(0xb8)
#define R3_PR_HD1 RTC_ACCESS(0xb9)
#endif
SDK/interface/driver/cpu/br35/asm/power/power_api.h
+180
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@@ -0,0 +1,180 @@
#ifndef __POWER_API_H__
#define __POWER_API_H__
#define AT_VOLATILE_RAM_POWER AT(.power_driver.data)
#define AT_VOLATILE_RAM_BSS_POWER AT(.power_driver.data.bss)
#define AT_VOLATILE_RAM_CODE_POWER AT(.power_driver.text.cache.L1)
#define AT_VOLATILE_RAM_LOWPOWER AT_VOLATILE_RAM_POWER //AT(.power_driver.data.overlay)
#define AT_VOLATILE_RAM_BSS_LOWPOWER AT(.power_driver.data.bss.overlay)//AT_VOLATILE_RAM_BSS_POWER
#define AT_VOLATILE_RAM_CODE_LOWPOWER AT_VOLATILE_RAM_CODE_POWER //AT(.power_driver.text.cache.L1.overlay)
#define AT_VOLATILE_CACHE_LOWPOWER
#define AT_VOLATILE_CACHE_BSS_LOWPOWER
#define AT_VOLATILE_CACHE_CODE_LOWPOWER AT(.power_driver.text.cache.fetch)
//
//
// platform_data
//
//
//
//******************************************************************
//config
enum LOWPOWER_CONFIG {
LOWPOWER_CLOSE,
SLEEP_EN,
DEEP_SLEEP_EN,
};
//osc_type
enum LOWPOWER_OSC_TYPE {
OSC_TYPE_LRC,
OSC_TYPE_BT_OSC,
OSC_TYPE_NULL,
};
struct _power_param {
//sleep
u32 btosc_hz; //蓝牙晶振频率(默认使用24M)
u32 osc_delay_us; //低功耗晶振起振延时，为预留配置。
u32 t1; //低功耗参数，预留配置
u32 t2; //低功耗参数，预留配置
u32 t3; //低功耗参数，预留配置
u32 t4; //低功耗参数，预留配置
//power
//vddiom\vddiow在进出低功耗时使用 VDDIO_KEEP_TYPE 配置
u8 vddiom_lev; //vddiom，系统工作时使用vddiom ldo(使用enum VDDIOM_VOL配置)
u8 vddiow_lev; //vddiow，系统低功耗时使用vddiow ldo(使用enum VDDIOW_VOL配置)
//sleep
u8 config; //低功耗使能，蓝牙&&系统空闲可进入低功耗(使用LOWPOWER_CONFIG配置)
u8 osc_type; //低功耗晶振类型(使用enum LOWPOWER_OSC_TYPE配置)
u8 lptmr_flow; //低功耗参数由用户配置
};
struct _power_pdata {
struct _power_param *power_param_p;
struct _wakeup_param *wakeup_param_p;
};
//
//
// power_api
//
//
//
//******************************************************************
enum VDDIO_KEEP_TYPE {
VDDIO_KEEP_TYPE_NULL, //vddiow使用配置值
VDDIO_KEEP_TYPE_NORMAL, //vddiow使用配置值使用vddiom挡位，即vddiom_lev
VDDIO_KEEP_TYPE_TRIM, //vddiow使用trim值
VDDIO_KEEP_TYPE_PG, //保持vddiom不关闭
VDDIO_KEEP_TYPE_CLOSE, //vddio关闭
};
#include "power/low_power.h"
void power_early_init(u32 arg);
void power_later_init(u32 arg);
void power_init(struct _power_pdata *pdata);
enum PCONTROL_CMD {
PCONTROL_POWER_DRIVER_RESERVE = 0,
PCONTROL_P_PUTBYTE, //串口调试函数
//*****************************************************
/* power
*/
PCONTROL_POWER_MODE = 0x100,
PCONTROL_DCVDD_CAP_SW, //0：DCVDD上没有外挂电容 1：DCVDD上有外挂电容
PCONTROL_FLASH_PG_VDDIO, //0：FLASH电源引脚使用IO 1：FLASH电源引脚没有使用IO
PCONTROL_RTC_CLK, //RTC_CLK类型，配置开机、关机晶振流程
PCONTROL_POWER_SUPPLY, //供电方式，0：IOVDD供电，1：VPWR供电
//*****************************************************
/* sleep
*/
PCONTROL_PD_VDDIO_KEEP, //pdown vddio切换流程(使用enum VDDIO_KEEP_TYPE配置)
PCONTROL_PD_WDVDD_LEV, //pdown wvdd挡位
PCONTROL_PD_DVDD_LEV, //pdown dvdd挡位
PCONTROL_PD_KEEP_LPCTMU, //pdown 触摸是否保持 0：不保持 1：保持
PCONTROL_PD_KEEP_NVDD, //pdown 模式pvdd是否掉电 0, 不掉点 1：掉电
//*****************************************************
/* soff
*/
PCONTROL_SF_KEEP_LRC, //soff lrc是否保持 0：不保持 1：保持
PCONTROL_SF_VDDIO_KEEP, //soff vddio切换流程(使用enum VDDIO_KEEP_TYPE配置)
PCONTROL_SF_KEEP_NVDD, //soff nvdd是否保持 0：不保持 1：保持
PCONTROL_SF_KEEP_PVDD, //soff pvdd是否保持 0：不保持 1：保持
//*****************************************************
/* 以下配置为对应子模块的预留配置
*/
PCONTROL_PHW_RESERVE = 0x100, //使用enum POWER_MODE配置
PCONTROL_P33_RESERVE = 0x200, //使用PCONTROL_P33_CMD配置
PCONTROL_P11_RESERVE = 0x300, //使用PCONTROL_P11_CMD配置
PCONTROL_LP_FLOW_IC_RESERVE = 0x400, //使用PCONTROL_IC_CMD配置
};
u32 power_control(enum PCONTROL_CMD cmd, u32 arg);
void dvdd2_bypass_en(u8 mode);
//
//
// lowpower
//
//
//
//******************************************************************
void pmu_trim(u32 force_trim, u32 vddio_tieup_vbat);
//
//
// soff
//
//
//
//******************************************************************
//p33 soft flag
enum soft_flag_io_stage {
SOFTFLAG_HIGH_RESISTANCE,
SOFTFLAG_PU,
SOFTFLAG_PD,
SOFTFLAG_OUT0,
SOFTFLAG_OUT0_HD0,
SOFTFLAG_OUT0_HD,
SOFTFLAG_OUT0_HD0_HD,
SOFTFLAG_OUT1,
SOFTFLAG_OUT1_HD0,
SOFTFLAG_OUT1_HD,
SOFTFLAG_OUT1_HD0_HD,
SOFTFLAG_PU100K,
SOFTFLAG_PU1M,
SOFTFLAG_PD100K,
SOFTFLAG_PD1M,
};
struct app_soft_flag_t {
u8 sfc_fast_boot;
u8 flash_stable_delay_sel;
u8 usbdp;
u8 usbdm;
u8 pp0;
};
void mask_softflag_config(struct app_soft_flag_t *softflag);
#endif
SDK/interface/driver/cpu/br35/asm/power/power_compat.h
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#ifndef __POWER_COMPAT_H__
#define __POWER_COMPAT_H__
int cpu_reset_by_soft();
void wdt_close();
#endif
SDK/interface/driver/cpu/br35/asm/power/power_gate.h
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#ifndef __POWER_GATE_H__
#define __POWER_GATE_H__
#include "typedef.h"
//STPG define bit
#define STPG_A 0 //STPG output bit
#define STPG_HD0 2 //STPG HD0
#define STPG_HD1 3 //STPG HD1
#define STPG_OE 4 //STPG output enable bit
#define STPG_PD 5 //STPG pull down enable bit
#define STPG_PD1 6 //STPG pull down enable bit
/*
*@brief 初始化pg_io送出高阻+低电平的pwm
*@param pg_io : 可选IO_LCD_PG, IO_MT_PG
*@param freq : pwm的频率
*@param duty : pwm的低电平的占空比，0~10000对应0%~100%
*@return 0:成功 非0:失败
*/
int power_gate_pwm_init(u32 pg_io, u32 freq, u32 duty);
/*
*@brief 设置pg_io的pwm的低电平占空比
*@param pg_io : 可选IO_LCD_PG, IO_MT_PG
*@param duty : pwm的低电平的占空比，0~10000对应0%~100%
*/
void power_gate_pwm_set_duty(u32 pg_io, u32 duty);
/*
*@brief 关闭pwm, pg_io为高阻
*@param pg_io : 可选IO_LCD_PG, IO_MT_PG
*/
void power_gate_pwm_close(u32 pg_io);
/*
*@brief 设置pg_io的开漏输出
*@param pg_io : 可选IO_LCD_PG, IO_MT_PG
*@param value : 0,输出低电平 1,则高阻
*/
void power_gate_open_drain_output(u32 pg_io, u32 value);
/*
*@brief 开启stpg供电
*@param ms : ms延时
*/
void fspg2_poweron(u32 ms);
/*
*@brief 关闭stpg供电
*@param ms : ms延时
*/
void fspg2_poweroff(u32 ms);
#endif
SDK/interface/driver/cpu/br35/asm/power/power_port.h
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#ifndef __POWER_PORT_H__
#define __POWER_PORT_H__
//
//
// FLASH PIN
//
//
//
//*****************************************************************************/
#define GET_SFC_PORT() ((JL_SFC_IOMC->IOMC0 & BIT(1)) ? 1:0)
/******************************************************************************/
#define _PORT(p) JL_PORT##p
#define _PORT_IN(p,b) P##p##b##_IN
#define _PORT_OUT(p,b) JL_OMAP->P##p##b##_OUT
/****************************spi boot *****************************************/
#define SPI_PORT(p) _PORT(p)
#define SPI0_FUNC_OUT(p,b) _PORT_OUT(p,b)
#define SPI0_FUNC_IN(p,b) _PORT_IN(p,b)
// | func\port | A | B |
// |-----------|------|------|
// | VCC | FSPG | |
// | CS | PD3 | |
// | CLK | PD0 | |
// | DO(D0) | PD1 | |
// | DI(D1) | PD2 | |
// | WP(D2) | PA5 | |
// | HOLD(D3) | PA6 | |
//FSPG define bit
#define FSPG_A 0 //FSPG output bit
#define FSPG_CS_EN 1 //FSPG CS connect enable bit
#define FSPG_HD0 2 //FSPG HD0
#define FSPG_HD1 3 //FSPG HD1
#define FSPG_OE 4 //FSPG output enable bit
#define FSPG_PD 5 //FSPG pull down enable bit
#define FSPG_PD1 6 //FSPG pull down enable bit
#define FSPG_18V 7 //flash supply power domain 1: DCVDD 1.8V; 0: IOVDD;
////////////////////////////////////////////////////////////////////////////////
//group a
#define PORT_SPI0_CSA F
#define SPI0_CSA 0
#define PORT_SPI0_CLKA F
#define SPI0_CLKA 4
#define PORT_SPI0_DOA F
#define SPI0_DOA 5
#define PORT_SPI0_DIA F
#define SPI0_DIA 1
#define PORT_SPI0_D2A F
#define SPI0_D2A 2
#define PORT_SPI0_D3A F
#define SPI0_D3A 3
//#define SPI0_PWR_A IO_PORTD_04
#define SPI0_CS_A IO_PORTF_00
#define SPI0_CLK_A IO_PORTF_04
#define SPI0_DO_D0_A IO_PORTF_05
#define SPI0_DI_D1_A IO_PORTF_01
#define SPI0_WP_D2_A IO_PORTF_02
#define SPI0_HOLD_D3_A IO_PORTF_03
////////////////////////////////////////////////////////////////////////////////
//group b
#define PORT_SPI0_CSB F
#define SPI0_CSB 3
#define PORT_SPI0_CLKB F
#define SPI0_CLKB 1
#define PORT_SPI0_DOB F
#define SPI0_DOB 0
#define PORT_SPI0_DIB F
#define SPI0_DIB 4
#define PORT_SPI0_D2B F
#define SPI0_D2B 5
#define PORT_SPI0_D3B F
#define SPI0_D3B 2
//#define SPI0_PWR_B IO_PORTD_04
#define SPI0_CS_B IO_PORTF_03
#define SPI0_CLK_B IO_PORTF_01
#define SPI0_DO_D0_B IO_PORTF_00
#define SPI0_DI_D1_B IO_PORTF_04
#define SPI0_WP_D2_B IO_PORTF_05
#define SPI0_HOLD_D3_B IO_PORTF_02
////////////////////////////////////////////////////////////////////////////////
//
//
// PSRAM
//
//
//
//*****************************************************************************/
#define PSRAM_CS IO_PORTC_06
#define PSRAM_CLK IO_PORTC_05
#define PSRAM_D0A IO_PORTC_09
#define PSRAM_D1A IO_PORTC_07
#define PSRAM_D2A IO_PORTC_08
#define PSRAM_D3A IO_PORTC_04
#define PINR_DEFAULT_IO IO_PORTB_07
#define MCLR_PORT IO_PORTB_06
//A B C F P USB
#define PORT_TABLE(arg) u32 gpio_confi##arg[6] = {0xffff, 0xffff,0xffff, 0xffff, 0xffff, 0xffff}
void port_protect(u32 *gpio_config, u32 gpio);
#define PORT_PROTECT(gpio) port_protect(gpio_config, gpio)
void init_boot_rom();
u8 get_boot_rom();
void *__port_init(u32 arg);
#endif