初版
This commit is contained in:
huxi
@@ -0,0 +1,164 @@
|
||||
#ifndef __LP_IPC__
|
||||
#define __LP_IPC__
|
||||
|
||||
//===========================================================================//
|
||||
// P2M MESSAGE TABLE //
|
||||
//===========================================================================//
|
||||
#define P11_RAM_ACCESS(x) (*(volatile u8 *)(x))
|
||||
#define M2P_MESSAGE_ACCESS(x) P11_RAM_ACCESS(M2P_MESSAGE_RAM_BEGIN + x)
|
||||
#define P2M_MESSAGE_ACCESS(x) P11_RAM_ACCESS(P2M_MESSAGE_RAM_BEGIN + x)
|
||||
|
||||
//==================power=============================
|
||||
#define P2M_WKUP_SRC P2M_MESSAGE_ACCESS(0)
|
||||
#define P2M_WKUP_P_PND P2M_MESSAGE_ACCESS(1)
|
||||
#define P2M_WKUP_N_PND P2M_MESSAGE_ACCESS(2)
|
||||
#define P2M_AWKUP_P_PND P2M_MESSAGE_ACCESS(3)
|
||||
#define P2M_AWKUP_N_PND P2M_MESSAGE_ACCESS(4)
|
||||
#define P2M_WKUP_RTC P2M_MESSAGE_ACCESS(5)
|
||||
#define P2M_WKUP_CNT0 P2M_MESSAGE_ACCESS(6)
|
||||
#define P2M_WKUP_CNT1 P2M_MESSAGE_ACCESS(7)
|
||||
#define P2M_WKUP_CNT2 P2M_MESSAGE_ACCESS(8)
|
||||
#define P2M_WKUP_CNT3 P2M_MESSAGE_ACCESS(9)
|
||||
#define P2M_OSC_CNT0 P2M_MESSAGE_ACCESS(10)
|
||||
#define P2M_OSC_CNT1 P2M_MESSAGE_ACCESS(11)
|
||||
#define P2M_OSC_CNT2 P2M_MESSAGE_ACCESS(12)
|
||||
#define P2M_OSC_CNT3 P2M_MESSAGE_ACCESS(13)
|
||||
|
||||
//==================system===========================
|
||||
#define P2M_MESSAGE_BANK_ADR_L P2M_MESSAGE_ACCESS(15)
|
||||
#define P2M_MESSAGE_BANK_ADR_H P2M_MESSAGE_ACCESS(16)
|
||||
#define P2M_MESSAGE_BANK_INDEX P2M_MESSAGE_ACCESS(17)
|
||||
#define P2M_MESSAGE_BANK_ACK P2M_MESSAGE_ACCESS(18)
|
||||
#define P2M_P11_HEAP_BEGIN_ADDR_L P2M_MESSAGE_ACCESS(19)
|
||||
#define P2M_P11_HEAP_BEGIN_ADDR_H P2M_MESSAGE_ACCESS(20)
|
||||
#define P2M_P11_HEAP_SIZE_L P2M_MESSAGE_ACCESS(21)
|
||||
#define P2M_P11_HEAP_SIZE_H P2M_MESSAGE_ACCESS(22)
|
||||
#define P2M_REPLY_SYNC_CMD P2M_MESSAGE_ACCESS(23)
|
||||
#define P2M_CBUF_ADDR0 P2M_MESSAGE_ACCESS(24)
|
||||
#define P2M_CBUF_ADDR1 P2M_MESSAGE_ACCESS(25)
|
||||
#define P2M_CBUF_ADDR2 P2M_MESSAGE_ACCESS(26)
|
||||
#define P2M_CBUF_ADDR3 P2M_MESSAGE_ACCESS(27)
|
||||
#define P2M_CBUF1_ADDR0 P2M_MESSAGE_ACCESS(28)
|
||||
#define P2M_CBUF1_ADDR1 P2M_MESSAGE_ACCESS(29)
|
||||
#define P2M_CBUF1_ADDR2 P2M_MESSAGE_ACCESS(30)
|
||||
#define P2M_CBUF1_ADDR3 P2M_MESSAGE_ACCESS(31)
|
||||
|
||||
//==================clock===========================
|
||||
#define P2M_BTOSC_OK P2M_MESSAGE_ACCESS(35)
|
||||
|
||||
//==================lpctmu===========================
|
||||
#define P2M_CTMU_CMD_ACK P2M_MESSAGE_ACCESS(39)
|
||||
#define P2M_MASSAGE_CTMU_CH0_L_RES 40
|
||||
#define P2M_MASSAGE_CTMU_CH0_H_RES 41
|
||||
#define P2M_CTMU_CH0_L_RES P2M_MESSAGE_ACCESS(40)
|
||||
#define P2M_CTMU_CH0_H_RES P2M_MESSAGE_ACCESS(41)
|
||||
#define P2M_CTMU_CH1_L_RES P2M_MESSAGE_ACCESS(42)
|
||||
#define P2M_CTMU_CH1_H_RES P2M_MESSAGE_ACCESS(43)
|
||||
#define P2M_CTMU_CH2_L_RES P2M_MESSAGE_ACCESS(44)
|
||||
#define P2M_CTMU_CH2_H_RES P2M_MESSAGE_ACCESS(45)
|
||||
#define P2M_CTMU_CH3_L_RES P2M_MESSAGE_ACCESS(46)
|
||||
#define P2M_CTMU_CH3_H_RES P2M_MESSAGE_ACCESS(47)
|
||||
#define P2M_CTMU_CH4_L_RES P2M_MESSAGE_ACCESS(48)
|
||||
#define P2M_CTMU_CH4_H_RES P2M_MESSAGE_ACCESS(49)
|
||||
|
||||
|
||||
|
||||
//===========================================================================//
|
||||
// M2P MESSAGE TABLE //
|
||||
//===========================================================================//
|
||||
//==================power=============================
|
||||
#define M2P_LRC_PRD M2P_MESSAGE_ACCESS(0)
|
||||
#define M2P_WDVDD M2P_MESSAGE_ACCESS(1)
|
||||
#define M2P_LRC_FEQ0 M2P_MESSAGE_ACCESS(2)
|
||||
#define M2P_LRC_FEQ1 M2P_MESSAGE_ACCESS(3)
|
||||
#define M2P_LRC_FEQ2 M2P_MESSAGE_ACCESS(4)
|
||||
#define M2P_LRC_FEQ3 M2P_MESSAGE_ACCESS(5)
|
||||
#define M2P_VDDIO_KEEP M2P_MESSAGE_ACCESS(6)
|
||||
#define M2P_LRC_KEEP M2P_MESSAGE_ACCESS(7)
|
||||
#define M2P_RCH_FEQ_L M2P_MESSAGE_ACCESS(8)
|
||||
#define M2P_RCH_FEQ_H M2P_MESSAGE_ACCESS(9)
|
||||
#define M2P_MEM_CONTROL M2P_MESSAGE_ACCESS(10)
|
||||
#define M2P_BTOSC_KEEP M2P_MESSAGE_ACCESS(11)
|
||||
#define M2P_CTMU_KEEP M2P_MESSAGE_ACCESS(12)
|
||||
#define M2P_RTC_KEEP M2P_MESSAGE_ACCESS(13)
|
||||
#define M2P_SF_MODE M2P_MESSAGE_ACCESS(14)
|
||||
#define M2P_DCV_MODE M2P_MESSAGE_ACCESS(15)
|
||||
#define M2P_LIGHT_PDOWN_DVDD_VOL M2P_MESSAGE_ACCESS(16)
|
||||
#define M2P_LRC24M_MODE M2P_MESSAGE_ACCESS(17)
|
||||
|
||||
//==================system===========================
|
||||
#define M2P_SYNC_CMD M2P_MESSAGE_ACCESS(25)
|
||||
#define M2P_WDT_SYNC M2P_MESSAGE_ACCESS(26)
|
||||
#define M2P_WAIT_RELEASE M2P_MESSAGE_ACCESS(27)
|
||||
|
||||
//==================clock===========================
|
||||
#define M2P_LRC24M_CFG0 M2P_MESSAGE_ACCESS(35)
|
||||
#define M2P_LRC24M_CFG1 M2P_MESSAGE_ACCESS(36)
|
||||
#define M2P_BTOSC_CFG0 M2P_MESSAGE_ACCESS(37)
|
||||
#define M2P_BTOSC_CFG1 M2P_MESSAGE_ACCESS(38)
|
||||
|
||||
#define M2P_LRC24M_FEQ0 M2P_MESSAGE_ACCESS(39)
|
||||
#define M2P_LRC24M_FEQ1 M2P_MESSAGE_ACCESS(40)
|
||||
#define M2P_LRC24M_FEQ2 M2P_MESSAGE_ACCESS(41)
|
||||
#define M2P_LRC24M_FEQ3 M2P_MESSAGE_ACCESS(42)
|
||||
|
||||
|
||||
//==================lpctmu===========================
|
||||
#define M2P_CTMU_CMD M2P_MESSAGE_ACCESS(50)
|
||||
#define M2P_CTMU_CH_ENABLE M2P_MESSAGE_ACCESS(51)
|
||||
#define M2P_CTMU_CH_WAKEUP_EN M2P_MESSAGE_ACCESS(52)
|
||||
#define M2P_CTMU_SCAN_TIME M2P_MESSAGE_ACCESS(53)
|
||||
#define M2P_CTMU_LOWPOER_SCAN_TIME M2P_MESSAGE_ACCESS(54)
|
||||
|
||||
|
||||
/*
|
||||
* Must Sync to P11 code
|
||||
*/
|
||||
enum {
|
||||
M2P_LP_INDEX = 0,
|
||||
M2P_PF_INDEX,
|
||||
M2P_LLP_INDEX,
|
||||
M2P_P33_INDEX,
|
||||
M2P_SF_INDEX,
|
||||
M2P_CTMU_INDEX,
|
||||
M2P_CCMD_INDEX, //common cmd
|
||||
M2P_VAD_INDEX,
|
||||
M2P_USER_INDEX,
|
||||
M2P_WDT_INDEX,
|
||||
M2P_SYNC_INDEX,
|
||||
M2P_APP_INDEX,
|
||||
M2P_WKUP_INDEX,
|
||||
};
|
||||
|
||||
enum {
|
||||
P2M_LP_INDEX = 0,
|
||||
P2M_PF_INDEX,
|
||||
P2M_LLP_INDEX,
|
||||
P2M_WK_INDEX,
|
||||
P2M_WDT_INDEX,
|
||||
P2M_LP_INDEX2,
|
||||
P2M_CTMU_INDEX,
|
||||
P2M_CTMU_POWUP,
|
||||
P2M_REPLY_CCMD_INDEX, //reply common cmd
|
||||
P2M_VAD_INDEX,
|
||||
P2M_USER_INDEX,
|
||||
P2M_BANK_INDEX,
|
||||
P2M_REPLY_SYNC_INDEX,
|
||||
P2M_APP_INDEX,
|
||||
P2M_OSC_INDEX,
|
||||
};
|
||||
|
||||
enum {
|
||||
CLOSE_P33_INTERRUPT = 1,
|
||||
OPEN_P33_INTERRUPT,
|
||||
LOWPOWER_PREPARE,
|
||||
M2P_SPIN_LOCK,
|
||||
M2P_SPIN_UNLOCK,
|
||||
P2M_SPIN_LOCK,
|
||||
P2M_SPIN_UNLOCK,
|
||||
|
||||
};
|
||||
|
||||
#include "lp_msg.h"
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,139 @@
|
||||
#ifndef __LP_MSG_H__
|
||||
#define __LP_MSG_H__
|
||||
|
||||
//=================================消息格式========================================
|
||||
|
||||
//消息buf大小
|
||||
#define MAX_POOL 512
|
||||
|
||||
//消息类型
|
||||
enum {
|
||||
MSG_ACK = 0,
|
||||
MSG_TEST = 1,
|
||||
MSG_COMMOM = 2,
|
||||
MSG_CTMU = 3,
|
||||
MSG_SENSOR = 4,
|
||||
MSG_VAD = 5,
|
||||
MSG_RTC = 6,
|
||||
MSG_APP = 7,
|
||||
MSG_CLOCK = 8,
|
||||
};
|
||||
|
||||
//消息函数返回值
|
||||
enum {
|
||||
MSG_NO_ERROR = 0, //读取/发送消息成功
|
||||
MSG_NO_MSG = -1, //未读取到消息
|
||||
MSG_BUF_ERROR = -2, //读消息格式不对
|
||||
MSG_BUF_READ_OVER = -3, //读消息溢出，传的参数长度不对
|
||||
MSG_BUF_WRITE_OVER = -4, //写消息会溢出
|
||||
};
|
||||
|
||||
//消息头格式
|
||||
#define MSG_HEADER_BYTE_LEN 4
|
||||
#define MSG_HEADER_BIT_LEN (MSG_HEADER_BYTE_LEN*8)
|
||||
#define MSG_HEADER_ALL_BIT ((1L<<MSG_HEADER_BIT_LEN) - 1)
|
||||
|
||||
#define MSG_INDEX_BIT 15
|
||||
#define MSG_ACK_BIT 1
|
||||
|
||||
#define MSG_TYPE_BIT_LEN 8
|
||||
#define MSG_PARAM_BIT_LEN (MSG_HEADER_BYTE_LEN*8-MSG_TYPE_BIT_LEN-MSG_INDEX_BIT-MSG_ACK_BIT)
|
||||
|
||||
struct lp_msg_head {
|
||||
u32 type :
|
||||
MSG_TYPE_BIT_LEN;
|
||||
u32 ack :
|
||||
MSG_ACK_BIT;
|
||||
u32 index :
|
||||
MSG_INDEX_BIT;
|
||||
u32 len :
|
||||
MSG_PARAM_BIT_LEN;
|
||||
} __attribute__((packed));
|
||||
|
||||
//消息队列
|
||||
typedef struct LP_Q {
|
||||
u16 in; //写位置
|
||||
u16 out; //读位置
|
||||
u16 count; //有效数据
|
||||
u16 size; //buf大小
|
||||
u32 start; //buf起址
|
||||
u32 ack_flag;
|
||||
} LP_Q;
|
||||
|
||||
|
||||
enum {
|
||||
LP_BUF_NO_ERR = 0,
|
||||
LP_BUF_READ_NOT_ENOUGH_DATA = -1, //buf里数据不够读
|
||||
LP_BUF_READ_NO_DATA = -2, //buf里面没有数据
|
||||
LP_BUF_WRITE_OVER = -3, //写数据超过了buf大小
|
||||
};
|
||||
|
||||
//用户消息对应处理
|
||||
struct lp_msg_handler {
|
||||
void (*handler)(void *, u8 *, u32);
|
||||
void *priv;
|
||||
u8 type;
|
||||
} __attribute__((packed));
|
||||
|
||||
void lp_ipc_init();
|
||||
|
||||
void lp_ipc_later_init();
|
||||
|
||||
void message_init();
|
||||
|
||||
void lp_lock();
|
||||
|
||||
void lp_unlock();
|
||||
|
||||
void lp_ipc_handle_sync_cmd();
|
||||
|
||||
void config_post_ack_flag(u32 enable);
|
||||
|
||||
|
||||
//=================================M2P========================================
|
||||
#define REGISTER_M2P_MSG_HANDLER(pri, _type, fn) \
|
||||
const struct lp_msg_handler _##fn SEC_USED(.m2p_msg_handler)= { \
|
||||
.handler = fn, \
|
||||
.priv = pri, \
|
||||
.type = _type, \
|
||||
}
|
||||
|
||||
extern struct lp_msg_handler m2p_msg_handler_begin[];
|
||||
extern struct lp_msg_handler m2p_msg_handler_end[];
|
||||
|
||||
#define list_for_each_m2p_msg_handler(p) \
|
||||
for (p = m2p_msg_handler_begin; p < m2p_msg_handler_end; p++)
|
||||
|
||||
int m2p_get_msg(struct lp_msg_head *head, u8 *msg, u32 len);
|
||||
int m2p_post_msg(u32 type, u32 ack, u8 *msg, u32 len);
|
||||
|
||||
void msys_to_p11_sys_cmd(u8 cmd);
|
||||
|
||||
int m2p_msg_hdl(u32 index);
|
||||
|
||||
u32 msys_ack_p11(u32 index);
|
||||
|
||||
//=================================P2M========================================
|
||||
#define REGISTER_P2M_MSG_HANDLER(pri, _type, fn) \
|
||||
const struct lp_msg_handler _##fn SEC_USED(.p2m_msg_handler)= { \
|
||||
.handler = fn, \
|
||||
.priv = pri, \
|
||||
.type = _type, \
|
||||
}
|
||||
|
||||
extern struct lp_msg_handler p2m_msg_handler_begin[];
|
||||
extern struct lp_msg_handler p2m_msg_handler_end[];
|
||||
|
||||
#define list_for_each_p2m_msg_handler(p) \
|
||||
for (p = p2m_msg_handler_begin; p < p2m_msg_handler_end; p++)
|
||||
|
||||
int p2m_get_msg(struct lp_msg_head *head, u8 *msg, u32 len);
|
||||
int p2m_post_msg(u32 type, u32 ack, u8 *msg, u32 len);
|
||||
|
||||
int p2m_msg_hdl(u32 index);
|
||||
|
||||
u32 p11_ack_msys(u32 index);
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,9 @@
|
||||
#ifndef __P11_API_H__
|
||||
#define __P11_API_H__
|
||||
|
||||
void sfr_p2m_int_set(u32 index);
|
||||
|
||||
void sfr_p2m_int_ie_set(u32 index, u8 enable);
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,46 @@
|
||||
/**@file p11_hw.h
|
||||
* @brief hw sfr layer
|
||||
* @date 2024-05-16
|
||||
* @version V1.0
|
||||
* @copyright Copyright(c)2010-2031 JIELI
|
||||
* @details 该文件对p11 clock相关寄存器封装
|
||||
*/
|
||||
#ifndef __P11_CLOCK_HW_H__
|
||||
#define __P11_CLOCK_HW_H__
|
||||
|
||||
enum P11_SYS_CLK_TABLE {
|
||||
P11_SYS_CLK_RC16M = 0,
|
||||
P11_SYS_CLK_RC250K,
|
||||
P11_SYS_CLK_LRC_OSC,
|
||||
P11_SYS_CLK_BTOSC_24M,
|
||||
P11_SYS_CLK_BTOSC_48M,
|
||||
P11_SYS_CLK_LRC24M,
|
||||
P11_SYS_CLK_CLK_X2,
|
||||
P11_SYS_CLK_TEST,
|
||||
};
|
||||
|
||||
#define P11_SYS_CLK_SEL(x) (P11_CLOCK->CLK_CON0 = x)
|
||||
|
||||
//p11 btosc use d2sh
|
||||
#define CLOCK_KEEP(en) \
|
||||
if(en){ \
|
||||
P11_CLOCK->CLK_CON1 &= ~(3<<15); \
|
||||
P11_CLOCK->CLK_CON1 |= BIT(14); \
|
||||
P11_CLOCK->CLK_CON1 |= (2<<15); \
|
||||
}else{ \
|
||||
P11_CLOCK->CLK_CON1 &= ~(3<<15); \
|
||||
P11_CLOCK->CLK_CON1 &= ~BIT(14); \
|
||||
}
|
||||
|
||||
#define P2M_CLK_SET(x) SFR(P11_SYSTEM->P2M_CLK_CON0,0,8,x)
|
||||
|
||||
#define P2M_CLK_GET(x) (P11_SYSTEM->P2M_CLK_CON0 & 0xff)
|
||||
|
||||
#define RC_250k_EN(a) \
|
||||
if (a) { \
|
||||
P11_CLOCK->CLK_CON1 |= BIT(10); \
|
||||
} else { \
|
||||
P11_CLOCK->CLK_CON1 &= ~BIT(10); \
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,180 @@
|
||||
//*********************************************************************************//
|
||||
// Module name : csfr.h //
|
||||
// Description : q32small core sfr define //
|
||||
// By Designer : zequan_liu //
|
||||
// Dat changed : //
|
||||
//*********************************************************************************//
|
||||
|
||||
#ifndef __P11_Q32S_CSFR__
|
||||
#define __P11_Q32S_CSFR__
|
||||
|
||||
#define __RW volatile // read write
|
||||
#define __RO volatile const // only read
|
||||
#define __WO volatile // only write
|
||||
|
||||
#define __u8 unsigned int // u8 to u32 special for struct
|
||||
#define __u16 unsigned int // u16 to u32 special for struct
|
||||
#define __u32 unsigned int
|
||||
|
||||
#define CPU_CORE_NUM 1
|
||||
|
||||
//---------------------------------------------//
|
||||
// q32small define
|
||||
//---------------------------------------------//
|
||||
//#ifdef PMU_SYSTEM
|
||||
#if 1
|
||||
#define p11_q32s_sfr_base 0x00a000
|
||||
#define p11_q32s_sfr_offset 0x000000 // multi_core used
|
||||
#else
|
||||
#define p11_q32s_sfr_base 0xf2a000
|
||||
#define p11_q32s_sfr_offset 0x000000 // multi_core used
|
||||
#endif
|
||||
|
||||
#define p11_q32s_cpu_base (p11_q32s_sfr_base + 0x00)
|
||||
#define p11_q32s_mpu_base (p11_q32s_sfr_base + 0x80)
|
||||
|
||||
#define p11_q32s(n) ((JL_TypeDef_p11_q32s *)(p11_q32s_sfr_base + p11_q32s_sfr_offset*n))
|
||||
#define p11_q32s_mpu(n) ((JL_TypeDef_p11_q32s_MPU *)(p11_q32s_mpu_base + p11_q32s_sfr_offset*n))
|
||||
|
||||
//---------------------------------------------//
|
||||
// q32small core sfr
|
||||
//---------------------------------------------//
|
||||
|
||||
typedef struct {
|
||||
/* 00 */ __RO __u32 DR00;
|
||||
/* 01 */ __RO __u32 DR01;
|
||||
/* 02 */ __RO __u32 DR02;
|
||||
/* 03 */ __RO __u32 DR03;
|
||||
/* 04 */ __RO __u32 DR04;
|
||||
/* 05 */ __RO __u32 DR05;
|
||||
/* 06 */ __RO __u32 DR06;
|
||||
/* 07 */ __RO __u32 DR07;
|
||||
/* 08 */ __RO __u32 DR08;
|
||||
/* 09 */ __RO __u32 DR09;
|
||||
/* 0a */ __RO __u32 DR10;
|
||||
/* 0b */ __RO __u32 DR11;
|
||||
/* 0c */ __RO __u32 DR12;
|
||||
/* 0d */ __RO __u32 DR13;
|
||||
/* 0e */ __RO __u32 DR14;
|
||||
/* 0f */ __RO __u32 DR15;
|
||||
|
||||
/* 10 */ __RO __u32 RETI;
|
||||
/* 11 */ __RO __u32 RETE;
|
||||
/* 12 */ __RO __u32 RETX;
|
||||
/* 13 */ __RO __u32 RETS;
|
||||
/* 14 */ __RO __u32 SR04;
|
||||
/* 15 */ __RO __u32 PSR;
|
||||
/* 16 */ __RO __u32 CNUM;
|
||||
/* 17 */ __RO __u32 SR07;
|
||||
/* 18 */ __RO __u32 SR08;
|
||||
/* 19 */ __RO __u32 SR09;
|
||||
/* 1a */ __RO __u32 SR10;
|
||||
/* 1b */ __RO __u32 ICFG;
|
||||
/* 1c */ __RO __u32 USP;
|
||||
/* 1d */ __RO __u32 SSP;
|
||||
/* 1e */ __RO __u32 SP;
|
||||
/* 1f */ __RO __u32 PCRS;
|
||||
|
||||
/* 20 */ __RW __u32 BPCON;
|
||||
/* 21 */ __RW __u32 BSP;
|
||||
/* 22 */ __RW __u32 BP0;
|
||||
/* 23 */ __RW __u32 BP1;
|
||||
/* 24 */ __RW __u32 BP2;
|
||||
/* 25 */ __RW __u32 BP3;
|
||||
/* 26 */ __WO __u32 CMD_PAUSE;
|
||||
/* */ __RO __u32 REV_30_26[0x30 - 0x26 - 1];
|
||||
|
||||
/* 30 */ __RW __u32 PMU_CON0;
|
||||
/* 31 */ __RW __u32 PMU_CON1;
|
||||
/* 32 */ __RW __u32 RST_ADDR;
|
||||
/* */ __RO __u32 REV_3b_30[0x3b - 0x32 - 1];
|
||||
/* 3b */ __RW __u8 TTMR_CON;
|
||||
/* 3c */ __RW __u32 TTMR_CNT;
|
||||
/* 3d */ __RW __u32 TTMR_PRD;
|
||||
/* 3e */ __RW __u32 BANK_CON;
|
||||
/* 3f */ __RW __u32 BANK_NUM;
|
||||
|
||||
/* 40 */ __RW __u32 ICFG00;
|
||||
/* 41 */ __RW __u32 ICFG01;
|
||||
/* 42 */ __RW __u32 ICFG02;
|
||||
/* 43 */ __RW __u32 ICFG03;
|
||||
/* 44 */ __RW __u32 ICFG04;
|
||||
/* 45 */ __RW __u32 ICFG05;
|
||||
/* 46 */ __RW __u32 ICFG06;
|
||||
/* 47 */ __RW __u32 ICFG07;
|
||||
/* 48 */ __RW __u32 ICFG08;
|
||||
/* 49 */ __RW __u32 ICFG09;
|
||||
/* 4a */ __RW __u32 ICFG10;
|
||||
/* 4b */ __RW __u32 ICFG11;
|
||||
/* 4c */ __RW __u32 ICFG12;
|
||||
/* 4d */ __RW __u32 ICFG13;
|
||||
/* 4e */ __RW __u32 ICFG14;
|
||||
/* 4f */ __RW __u32 ICFG15;
|
||||
|
||||
/* 50 */ __RW __u32 ICFG16;
|
||||
/* 51 */ __RW __u32 ICFG17;
|
||||
/* 52 */ __RW __u32 ICFG18;
|
||||
/* 53 */ __RW __u32 ICFG19;
|
||||
/* 54 */ __RW __u32 ICFG20;
|
||||
/* 55 */ __RW __u32 ICFG21;
|
||||
/* 56 */ __RW __u32 ICFG22;
|
||||
/* 57 */ __RW __u32 ICFG23;
|
||||
/* 58 */ __RW __u32 ICFG24;
|
||||
/* 59 */ __RW __u32 ICFG25;
|
||||
/* 5a */ __RW __u32 ICFG26;
|
||||
/* 5b */ __RW __u32 ICFG27;
|
||||
/* 5c */ __RW __u32 ICFG28;
|
||||
/* 5d */ __RW __u32 ICFG29;
|
||||
/* 5e */ __RW __u32 ICFG30;
|
||||
/* 5f */ __RW __u32 ICFG31;
|
||||
|
||||
/* 60 */ __RO __u32 IPND0;
|
||||
/* 61 */ __RO __u32 IPND1;
|
||||
/* 62 */ __RO __u32 IPND2;
|
||||
/* 63 */ __RO __u32 IPND3;
|
||||
/* 64 */ __RO __u32 IPND4;
|
||||
/* 65 */ __RO __u32 IPND5;
|
||||
/* 66 */ __RO __u32 IPND6;
|
||||
/* 67 */ __RO __u32 IPND7;
|
||||
/* 68 */ __WO __u32 ILAT_SET;
|
||||
/* 69 */ __WO __u32 ILAT_CLR;
|
||||
/* 6a */ __RW __u32 IPMASK;
|
||||
/* 6b */ __RW __u32 GIEMASK;
|
||||
/* 6c */ __RW __u32 IWKUP_NUM;
|
||||
/* */ __RO __u32 REV_70_6c[0x70 - 0x6c - 1];
|
||||
|
||||
/* 70 */ __RW __u32 ETM_CON;
|
||||
/* 71 */ __RO __u32 ETM_PC0;
|
||||
/* 72 */ __RO __u32 ETM_PC1;
|
||||
/* 73 */ __RO __u32 ETM_PC2;
|
||||
/* 74 */ __RO __u32 ETM_PC3;
|
||||
/* 75 */ __RW __u32 WP0_ADRH;
|
||||
/* 76 */ __RW __u32 WP0_ADRL;
|
||||
/* 77 */ __RW __u32 WP0_DATH;
|
||||
/* 78 */ __RW __u32 WP0_DATL;
|
||||
/* 79 */ __RW __u32 WP0_PC;
|
||||
|
||||
/* */ __RO __u32 REV_80_79[0x80 - 0x79 - 1];
|
||||
/* 80 */ __RW __u32 EMU_CON;
|
||||
/* 81 */ __RW __u32 EMU_MSG;
|
||||
/* 82 */ __RO __u32 EMU_SSP_H;
|
||||
/* 83 */ __RO __u32 EMU_SSP_L;
|
||||
/* 84 */ __RO __u32 EMU_USP_H;
|
||||
/* 85 */ __RO __u32 EMU_USP_L;
|
||||
} JL_TypeDef_p11_q32s;
|
||||
|
||||
#undef __RW
|
||||
#undef __RO
|
||||
#undef __WO
|
||||
|
||||
#undef __u8
|
||||
#undef __u16
|
||||
#undef __u32
|
||||
|
||||
#endif
|
||||
|
||||
//*********************************************************************************//
|
||||
// //
|
||||
// end of this module //
|
||||
// //
|
||||
//*********************************************************************************//
|
||||
@@ -0,0 +1,34 @@
|
||||
//===============================================================================//
|
||||
//
|
||||
// input IO define
|
||||
//
|
||||
//===============================================================================//
|
||||
#define P11_PB0_IN 1
|
||||
#define P11_PB1_IN 2
|
||||
#define P11_PB2_IN 3
|
||||
#define P11_PB3_IN 4
|
||||
#define P11_PB4_IN 5
|
||||
#define P11_PB5_IN 6
|
||||
#define P11_PB6_IN 7
|
||||
#define P11_PB7_IN 8
|
||||
#define P11_PB8_IN 9
|
||||
|
||||
//===============================================================================//
|
||||
//
|
||||
// function input select sfr
|
||||
//
|
||||
//===============================================================================//
|
||||
typedef struct {
|
||||
__RW __u8 P11_FI_GP_ICH0;
|
||||
__RW __u8 P11_FI_GP_ICH1;
|
||||
__RW __u8 P11_FI_GP_ICH2;
|
||||
__RW __u8 P11_FI_UART0_RX;
|
||||
__RW __u8 P11_FI_UART1_RX;
|
||||
__RW __u8 P11_FI_SPI_DI;
|
||||
__RW __u8 P11_FI_IIC_SCL;
|
||||
__RW __u8 P11_FI_IIC_SDA;
|
||||
} P11_IMAP_TypeDef;
|
||||
|
||||
#define P11_IMAP_BASE (p11_sfr_base + map_adr(0x17, 0x00))
|
||||
#define P11_IMAP ((P11_IMAP_TypeDef *)P11_IMAP_BASE)
|
||||
|
||||
@@ -0,0 +1,35 @@
|
||||
//===============================================================================//
|
||||
//
|
||||
// output function define
|
||||
//
|
||||
//===============================================================================//
|
||||
#define P11_FO_GP_OCH0 ((0 << 2)|BIT(1))
|
||||
#define P11_FO_GP_OCH1 ((1 << 2)|BIT(1))
|
||||
#define P11_FO_GP_OCH2 ((2 << 2)|BIT(1))
|
||||
#define P11_FO_UART0_TX ((3 << 2)|BIT(1)|BIT(0))
|
||||
#define P11_FO_UART1_TX ((4 << 2)|BIT(1)|BIT(0))
|
||||
#define P11_FO_SPI_CLK ((5 << 2)|BIT(1)|BIT(0))
|
||||
#define P11_FO_SPI_DO ((6 << 2)|BIT(1)|BIT(0))
|
||||
#define P11_FO_IIC_SCL ((7 << 2)|BIT(1)|BIT(0))
|
||||
#define P11_FO_IIC_SDA ((8 << 2)|BIT(1)|BIT(0))
|
||||
|
||||
//===============================================================================//
|
||||
//
|
||||
// IO output select sfr
|
||||
//
|
||||
//===============================================================================//
|
||||
typedef struct {
|
||||
__RW __u8 P11_PB0_OUT;
|
||||
__RW __u8 P11_PB1_OUT;
|
||||
__RW __u8 P11_PB2_OUT;
|
||||
__RW __u8 P11_PB3_OUT;
|
||||
__RW __u8 P11_PB4_OUT;
|
||||
__RW __u8 P11_PB5_OUT;
|
||||
__RW __u8 P11_PB6_OUT;
|
||||
__RW __u8 P11_PB7_OUT;
|
||||
__RW __u8 P11_PB8_OUT;
|
||||
} P11_OMAP_TypeDef;
|
||||
|
||||
#define P11_OMAP_BASE (p11_sfr_base + map_adr(0x16, 0x00))
|
||||
#define P11_OMAP ((P11_OMAP_TypeDef *)P11_OMAP_BASE)
|
||||
|
||||
@@ -0,0 +1,41 @@
|
||||
#ifndef __P11_MMAP_H__
|
||||
#define __P11_MMAP_H__
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//#ifdef PMU_SYSTEM
|
||||
#if 1
|
||||
#define P11_RAM_BASE 0
|
||||
#else
|
||||
#define P11_RAM_BASE 0xF20000
|
||||
#endif
|
||||
#define P11_RAM_BEGIN (P11_RAM_BASE)
|
||||
#define P11_RAM_SIZE (0x8000)
|
||||
#define P11_RAM_END (P11_RAM_BASE+P11_RAM_SIZE)
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
#define MSYS_POFF_RAM_END P11_RAM_END
|
||||
#define MSYS_POFF_RAM_SIZE 0x20
|
||||
#define MSYS_POFF_RAM_BEGIN (MSYS_POFF_RAM_END - MSYS_POFF_RAM_SIZE)
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
#define M2P_MESSAGE_END MSYS_POFF_RAM_BEGIN
|
||||
#define M2P_MESSAGE_SIZE 0xe0
|
||||
#define M2P_MESSAGE_RAM_BEGIN (M2P_MESSAGE_END - M2P_MESSAGE_SIZE)
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
#define P2M_MESSAGE_END M2P_MESSAGE_RAM_BEGIN
|
||||
#define P2M_MESSAGE_SIZE 0x40
|
||||
#define P2M_MESSAGE_RAM_BEGIN (P2M_MESSAGE_END - P2M_MESSAGE_SIZE)
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
#define P11_RAM0_END P2M_MESSAGE_RAM_BEGIN
|
||||
#define P11_RAM0_BEGIN (P11_RAM_BASE+P11_ISR_SIZE)
|
||||
#define P11_RAM0_SIZE (P11_RAM0_END - P11_RAM0_BEGIN)
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
#define P11_ISR_END P11_RAM0_BEGIN
|
||||
#define P11_ISR_SIZE 0x80
|
||||
#define P11_ISR_BEGIN P11_RAM_BASE
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,22 @@
|
||||
#ifndef _ROM_API_H_
|
||||
#define _ROM_API_H_
|
||||
//---------------------------------------------//
|
||||
// rom functions
|
||||
//---------------------------------------------//
|
||||
|
||||
void idle(void);
|
||||
void standby(volatile u32 *pwr_con_sfr);
|
||||
void standby_ext(volatile u32 *pwr_con_sfr);
|
||||
void sleep_ext(volatile u32 *pwr_con_sfr);
|
||||
void sleep(volatile u32 *pwr_con_sfr);
|
||||
void deep_sleep(volatile u32 *nvpwr_sfr, volatile u32 *pvdd_sfr, volatile u32 *pwr_con_sfr, u32 dly, u32 pvdd_set, u8 nvpwr_set);
|
||||
|
||||
|
||||
#define CALL_IDLE() idle()
|
||||
#define CALL_STANDBY() standby(&P11_CLOCK->PWR_CON)
|
||||
#define CALL_SLEEP() sleep(&P11_CLOCK->PWR_CON)
|
||||
#define CALL_STANDBY_EXT() standby_ext(&P11_CLOCK->PWR_CON)
|
||||
#define CALL_SLEEP_EXT() sleep_ext(&P11_CLOCK->PWR_CON)
|
||||
#define CALL_DEEP_SLEEP(x,y,z) deep_sleep(&P3_NVRAM_PWR, &P3_PVDD1_AUTO, &P11_CLOCK->PWR_CON, x, y, z)
|
||||
|
||||
#endif /* #ifndef _ROM_API_H_ */
|
||||
@@ -0,0 +1,332 @@
|
||||
#ifndef __P11__
|
||||
#define __P11__
|
||||
|
||||
//===============================================================================//
|
||||
//
|
||||
// sfr define
|
||||
//
|
||||
//===============================================================================//
|
||||
|
||||
//#ifdef PMU_SYSTEM
|
||||
#if 1
|
||||
#define p11_base 0x000000
|
||||
#define p11_ram_base p11_base
|
||||
#define p11_sfr_base 0x00a000
|
||||
#else
|
||||
#define p11_base 0xf20000
|
||||
#define p11_ram_base p11_base
|
||||
#define p11_sfr_base 0xf2a000
|
||||
#endif
|
||||
|
||||
#define __RW volatile // read write
|
||||
#define __RO volatile const // only read
|
||||
#define __WO volatile // only write
|
||||
|
||||
#define __u8 unsigned int // u8 to u32 special for struct
|
||||
#define __u16 unsigned int // u16 to u32 special for struct
|
||||
#define __u32 unsigned int
|
||||
|
||||
#define __s8(x) char(x); char(reserved_1_##x); char(reserved_2_##x); char(reserved_3_##x)
|
||||
#define __s16(x) short(x); short(reserved_1_##x)
|
||||
#define __s32(x) int(x)
|
||||
|
||||
#define map_adr(grp, adr) ((64 * grp + adr) * 4) // grp(0x0-0xff), adr(0x0-0x3f)
|
||||
#define P11_ACCESS(x) (*(volatile u32 *)(p11_base + x))
|
||||
#define P11_RAM(x) (*(volatile u32 *)(p11_ram_base + x))
|
||||
|
||||
//===============================================================================//
|
||||
//
|
||||
// sfr address define
|
||||
//
|
||||
//===============================================================================//
|
||||
|
||||
//............. 0x0000 - 0x03ff............ for cpu
|
||||
|
||||
// #include ../core/csfr.h
|
||||
|
||||
//............. 0x0400 - 0x04ff............ for clock
|
||||
typedef struct {
|
||||
__RW __u32 PWR_CON;
|
||||
__RW __u32 RST_SRC;
|
||||
__RW __u32 WKUP_EN;
|
||||
__RW __u32 WKUP_SRC;
|
||||
__RW __u32 SYS_DIV;
|
||||
__RW __u32 CLK_CON0;
|
||||
__RW __u32 CLK_CON1;
|
||||
__RW __u32 CLK_CON2;
|
||||
__RW __u32 XOSC_CFG0;
|
||||
__RW __u32 XOSC_CFG1;
|
||||
__RW __u32 LRC24M_CFG0;
|
||||
__RW __u32 CLKCFG_CFG0;
|
||||
} P11_CLOCK_TypeDef;
|
||||
|
||||
#define P11_CLOCK_BASE (p11_sfr_base + map_adr(0x04, 0x00))
|
||||
#define P11_CLOCK ((P11_CLOCK_TypeDef *)P11_CLOCK_BASE)
|
||||
|
||||
#define P11_PWR_CON P11_CLOCK->PWR_CON
|
||||
#define P11_CLK_CON0 P11_CLOCK->CLK_CON0
|
||||
|
||||
|
||||
//............. 0x0600 - 0x06ff............ for system
|
||||
typedef struct {
|
||||
__RW __u32 P2M_INT_IE;
|
||||
__RW __u32 P2M_INT_SET;
|
||||
__RW __u32 P2M_INT_CLR;
|
||||
__RO __u32 P2M_INT_PND;
|
||||
__RW __u32 P2M_CLK_CON0;
|
||||
__RW __u32 M2P_INT_IE;
|
||||
__RW __u32 M2P_INT_SET;
|
||||
__RW __u32 M2P_INT_CLR;
|
||||
__RO __u32 M2P_INT_PND;
|
||||
__RW __u32 P11_SYS_CON0;
|
||||
__RW __u32 P11_SYS_CON1;
|
||||
__RW __u32 PMU_KEY;
|
||||
} P11_SYSTEM_TypeDef;
|
||||
|
||||
#define P11_SYSTEM_BASE (p11_sfr_base + map_adr(0x06, 0x00))
|
||||
#define P11_SYSTEM ((P11_SYSTEM_TypeDef *)P11_SYSTEM_BASE)
|
||||
|
||||
//............. 0x0700 - 0x07ff............ for mbist
|
||||
typedef struct {
|
||||
__RW __u32 CON;
|
||||
__RW __u32 SEL;
|
||||
__RW __u32 BEG;
|
||||
__RW __u32 END;
|
||||
__RW __u32 DAT_VLD0;
|
||||
__RW __u32 DAT_VLD1;
|
||||
__RW __u32 DAT_VLD2;
|
||||
__RW __u32 DAT_VLD3;
|
||||
__RO __u32 ROM_CRC;
|
||||
__RW __u32 MCFG0_RF1P;
|
||||
__RW __u32 MCFG0_RF2P;
|
||||
__RW __u32 MCFG0_RM1P;
|
||||
__RW __u32 MCFG0_RM2P;
|
||||
__RW __u32 MCFG0_VROM;
|
||||
__RW __u32 MCFG0_CON[3];
|
||||
} P11_MBIST_TypeDef;
|
||||
|
||||
#define P11_MBIST_BASE (p11_sfr_base + map_adr(0x07, 0x00))
|
||||
#define P11_MBIST ((P11_MBIST_TypeDef *)P11_MBIST_BASE)
|
||||
|
||||
//............. 0x0800 - 0x08ff............ for watch dog
|
||||
typedef struct {
|
||||
__RW __u32 CON;
|
||||
__RW __u32 KEY;
|
||||
__RW __u32 DUMMY;
|
||||
} P11_WDT_TypeDef;
|
||||
|
||||
#define P11_WDT_BASE (p11_sfr_base + map_adr(0x08, 0x00))
|
||||
#define P11_WDT ((P11_WDT_TypeDef *)P11_WDT_BASE)
|
||||
|
||||
#define P11_SIM_END P11_WDT->DUMMY
|
||||
|
||||
//............. 0x0900 - 0x0cff............ for lp timer
|
||||
typedef struct {
|
||||
__RW __u32 CON0;
|
||||
__RW __u32 CON1;
|
||||
__RW __u32 CON2;
|
||||
__RW __u32 PRD;
|
||||
__RW __u32 RSC;
|
||||
__RO __u32 CNT;
|
||||
} P11_LPTMR_TypeDef;
|
||||
|
||||
#define P11_LPTMR0_BASE (p11_sfr_base + map_adr(0x09, 0x00))
|
||||
#define P11_LPTMR1_BASE (p11_sfr_base + map_adr(0x0a, 0x00))
|
||||
#define P11_LPTMR2_BASE (p11_sfr_base + map_adr(0x0b, 0x00))
|
||||
#define P11_LPTMR3_BASE (p11_sfr_base + map_adr(0x0c, 0x00))
|
||||
|
||||
#define P11_LPTMR0 ((P11_LPTMR_TypeDef *)P11_LPTMR0_BASE)
|
||||
#define P11_LPTMR1 ((P11_LPTMR_TypeDef *)P11_LPTMR1_BASE)
|
||||
#define P11_LPTMR2 ((P11_LPTMR_TypeDef *)P11_LPTMR2_BASE)
|
||||
#define P11_LPTMR3 ((P11_LPTMR_TypeDef *)P11_LPTMR3_BASE)
|
||||
|
||||
//............. 0x0d00 - 0x0dff............ for irflt
|
||||
typedef struct {
|
||||
__RW __u32 CON;
|
||||
} P11_IRFLT_TypeDef;
|
||||
|
||||
#define P11_IRFLT_BASE (p11_sfr_base + map_adr(0x0d, 0x00))
|
||||
#define P11_IRFLT ((P11_IRFLT_TypeDef *)P11_IRFLT_BASE)
|
||||
|
||||
//............. 0x0e00 - 0x0eff............ for spi
|
||||
typedef struct {
|
||||
__RW __u32 CON;
|
||||
__RW __u32 BAUD;
|
||||
__RW __u32 BUF;
|
||||
__WO __u32 ADR;
|
||||
__RW __u32 CNT;
|
||||
__RW __u32 CON1;
|
||||
} P11_SPI_TypeDef;
|
||||
|
||||
#define P11_SPI_BASE (p11_sfr_base + map_adr(0x0e, 0x00))
|
||||
#define P11_SPI ((P11_SPI_TypeDef *)P11_SPI_BASE)
|
||||
|
||||
//............. 0x0f00 - 0x10ff............ for uart
|
||||
typedef struct {
|
||||
__RW __u16 CON0;
|
||||
__RW __u16 CON1;
|
||||
__RW __u16 CON2;
|
||||
__RW __u16 BAUD;
|
||||
__RW __u8 BUF;
|
||||
__RW __u32 OTCNT;
|
||||
//__RW __u32 TXADR;
|
||||
//__WO __u16 TXCNT;
|
||||
//__RW __u32 RXSADR;
|
||||
//__RW __u32 RXEADR;
|
||||
//__RW __u32 RXCNT;
|
||||
//__RO __u16 HRXCNT;
|
||||
//__RO __u16 RX_ERR_CNT;
|
||||
} P11_UART_TypeDef;
|
||||
|
||||
#define P11_UART0_BASE (p11_sfr_base + map_adr(0x0f, 0x00))
|
||||
#define P11_UART1_BASE (p11_sfr_base + map_adr(0x10, 0x00))
|
||||
|
||||
#define P11_UART0 ((P11_UART_TypeDef *)P11_UART0_BASE)
|
||||
#define P11_UART1 ((P11_UART_TypeDef *)P11_UART1_BASE)
|
||||
|
||||
//............. 0x1100 - 0x11ff............ for iic
|
||||
typedef struct {
|
||||
__RW __u32 CON ;
|
||||
__RW __u32 PND ;
|
||||
__RW __u32 TX_BUF ;
|
||||
__RW __u32 TASK ;
|
||||
__RO __u32 RX_BUF ;
|
||||
__RW __u32 ADDR ;
|
||||
__RW __u32 BAUD ;
|
||||
__RW __u32 TSU ;
|
||||
__RW __u32 THD ;
|
||||
__RO __u32 DBG ;
|
||||
} P11_IIC_TypeDef;
|
||||
|
||||
#define P11_IIC_BASE (p11_sfr_base + map_adr(0x11, 0x00))
|
||||
#define P11_IIC ((P11_IIC_TypeDef *)P11_IIC_BASE)
|
||||
|
||||
//............. 0x1200 - 0x12ff............ for port
|
||||
typedef struct {
|
||||
__RW __u32 OCH_CON0 ;
|
||||
__RW __u32 ICH_CON0 ;
|
||||
__RW __u32 P33_PORT ;
|
||||
__RW __u32 PB_SEL ;
|
||||
__RO __u32 PB_IN ;
|
||||
__RW __u32 PB_OUT ;
|
||||
__RW __u32 PB_DIR ;
|
||||
__RW __u32 PB_DIE ;
|
||||
__RW __u32 PB_DIEH ;
|
||||
__RW __u32 PB_PU0 ;
|
||||
__RW __u32 PB_PU1 ;
|
||||
__RW __u32 PB_PD0 ;
|
||||
__RW __u32 PB_PD1 ;
|
||||
__RW __u32 PB_HD0 ;
|
||||
__RW __u32 PB_HD1 ;
|
||||
__RW __u32 PB_SPL ;
|
||||
} P11_PORT_TypeDef;
|
||||
|
||||
#define P11_PORT_BASE (p11_sfr_base + map_adr(0x12, 0x00))
|
||||
#define P11_PORT ((P11_PORT_TypeDef *)P11_PORT_BASE)
|
||||
|
||||
//............. 0x1300 - 0x14ff............ for lp ctmu
|
||||
typedef struct {
|
||||
__RW __u32 CON0 ;
|
||||
__RW __u32 CHEN ;
|
||||
__RW __u32 CNUM ;
|
||||
__RW __u32 PPRD ;
|
||||
__RW __u32 DPRD ;
|
||||
__RW __u32 ECON ;
|
||||
__RW __u32 EXEN ;
|
||||
__RW __u32 CHIS ;
|
||||
__RW __u32 CLKC ;
|
||||
__WO __u32 WCON ;
|
||||
__RW __u32 ANA0 ;
|
||||
__RW __u32 ANA1 ;
|
||||
__RO __u32 RES ;
|
||||
__RW __u32 DMA_START_ADR;
|
||||
__RW __u32 DMA_HALF_ADR;
|
||||
__RW __u32 DMA_END_ADR;
|
||||
__RW __u32 DMA_CON;
|
||||
__RW __u32 MSG_CON;
|
||||
__RO __u32 DMA_WADR;
|
||||
__RW __u32 SLEEP_CON;
|
||||
} P11_LPCTM_TypeDef;
|
||||
|
||||
#define P11_LPCTM0_BASE (p11_sfr_base + map_adr(0x13, 0x00))
|
||||
#define P11_LPCTM0 ((P11_LPCTM_TypeDef *)P11_LPCTM0_BASE)
|
||||
|
||||
// #define P11_LPCTM1_BASE (p11_sfr_base + map_adr(0x14, 0x00))
|
||||
// #define P11_LPCTM1 ((P11_LPCTM_TypeDef *)P11_LPCTM1_BASE)
|
||||
|
||||
|
||||
//............. 0x1500 - 0x15ff............ for lpvad
|
||||
typedef struct {
|
||||
__RW __u32 VAD_CON;
|
||||
__RW __u32 VAD_ACON0;
|
||||
__RW __u32 VAD_ACON1;
|
||||
__RW __u32 AVAD_CON;
|
||||
__RW __u32 AVAD_DATA;
|
||||
__RW __u32 DVAD_CON0;
|
||||
__RW __u32 DVAD_CON1;
|
||||
__RW __u32 DMA_BADR;
|
||||
__RW __u32 DMA_LEN;
|
||||
__RW __u32 DMA_HPTR;
|
||||
__RW __u32 DMA_SPTR;
|
||||
__RW __u32 DMA_SPN;
|
||||
__RW __u32 DMA_SHN;
|
||||
} P11_LPVAD_TypeDef;
|
||||
|
||||
#define P11_LPVAD_BASE (p11_sfr_base + map_adr(0x15, 0x00))
|
||||
#define P11_LPVAD ((P11_LPVAD_TypeDef *)P11_LPVAD_BASE)
|
||||
|
||||
//............. 0x1600 - 0x17ff............ for crossbar
|
||||
#include "p11_io_omap.h"
|
||||
#include "p11_io_imap.h"
|
||||
|
||||
//............. 0x1800 - 0x19ff............ for gp timer
|
||||
typedef struct {
|
||||
__RW __u32 CON;
|
||||
__RW __u32 CNT;
|
||||
__RW __u32 PRD;
|
||||
__RW __u32 PWM;
|
||||
__RW __u32 IRFLT;
|
||||
} P11_GPTMR_TypeDef;
|
||||
|
||||
#define P11_GPTMR0_BASE (p11_sfr_base + map_adr(0x18, 0x00))
|
||||
#define P11_GPTMR1_BASE (p11_sfr_base + map_adr(0x18, 0x05))
|
||||
|
||||
#define P11_GPTMR0 ((P11_GPTMR_TypeDef *)P11_GPTMR0_BASE)
|
||||
#define P11_GPTMR1 ((P11_GPTMR_TypeDef *)P11_GPTMR1_BASE)
|
||||
|
||||
//............. 0x1a00 - 0x1aff............ for NFC
|
||||
typedef struct {
|
||||
__RW __u32 CON0;
|
||||
__RW __u32 CON1;
|
||||
__RW __u32 CON2;
|
||||
__RW __u32 CON3;
|
||||
__RW __u32 BUF0;
|
||||
__RW __u32 BUF1;
|
||||
__RW __u32 BUF2;
|
||||
__RW __u32 BUF3;
|
||||
} P11_NFC_TypeDef;
|
||||
|
||||
#define P11_NFC_BASE (p11_sfr_base + map_adr(0x1a, 0x00))
|
||||
#define P11_NFC ((P11_NFC_TypeDef *)P11_NFC_BASE)
|
||||
|
||||
|
||||
//............. 0x1b00 - 0x1bff............ for RESLOCK
|
||||
typedef struct {
|
||||
__RW __u32 LOCK[16];
|
||||
} P11_RESLOCK_TypeDef;
|
||||
|
||||
#define P11_RESLOCK_BASE (p11_sfr_base + map_adr(0x1b,0x00))
|
||||
#define P11_RESLOCK ((P11_RESLOCK_TypeDef *)P11_RESLOCK_BASE)
|
||||
|
||||
|
||||
//............. 0x1c00 - 0x1cff............ for lp_gpcnt0
|
||||
typedef struct {
|
||||
__RW __u32 CON;
|
||||
__RO __u32 NUM;
|
||||
} P11_GPCNT_TypeDef;
|
||||
|
||||
#define P11_GPCNT0_BASE (p11_sfr_base + map_adr(0x1c, 0x00))
|
||||
#define P11_GPCNT0 ((P11_GPCNT_TypeDef *)P11_GPCNT0_BASE)
|
||||
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user