Uahpet/AC707N
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

初版

Browse Source
This commit is contained in:
huxi
2025-12-03 11:12:34 +08:00
parent c23ae4f24c
commit bc195654bf
8163 changed files with 3799544 additions and 92 deletions
Download Patch File Download Diff File Expand all files Collapse all files
loader/ble_app_ota_update/include_lib/btstack/ble_api.h
+141
View File
@@ -0,0 +1,141 @@
#ifndef __BLE_API_H__
#define __BLE_API_H__
#include "typedef.h"
///***注意：该文件的枚举与库编译密切相关，主要是给用户提供调用所用。用户不能自己在中间添加值。*/
////----user (command) codes----////
/**
* @brief hci connection handle type
*/
typedef uint16_t hci_con_handle_t;
typedef enum {
/*
*/
BLE_CMD_ADV_ENABLE = 1,
BLE_CMD_ADV_PARAM,
BLE_CMD_ADV_DATA,
BLE_CMD_RSP_DATA,
BLE_CMD_DISCONNECT,
BLE_CMD_REGIEST_THREAD,
BLE_CMD_ATT_SEND_INIT,
BLE_CMD_ATT_MTU_SIZE,
BLE_CMD_ATT_VAILD_LEN,
BLE_CMD_ATT_SEND_DATA,
BLE_CMD_REQ_CONN_PARAM_UPDATE,
BLE_CMD_SCAN_ENABLE,
BLE_CMD_SCAN_PARAM,
BLE_CMD_STACK_EXIT,
BLE_CMD_CREATE_CONN,
BLE_CMD_CREATE_CONN_CANCEL,
BLE_CMD_ADV_PARAM_EXT,
BLE_CMD_SEND_TEST_KEY_NUM,
//client
BLE_CMD_SEARCH_PROFILE = 0x80,
BLE_CMD_WRITE_CCC,
} ble_cmd_type_e;
typedef enum {
BLE_CMD_RET_SUCESS = 0, //
BLE_CMD_RET_BUSY = -100, //
BLE_CMD_PARAM_OVERFLOW, //
BLE_CMD_OPT_FAIL, //
BLE_BUFFER_FULL, //
BLE_BUFFER_ERROR, //
BLE_CMD_PARAM_ERROR, //
BLE_CMD_STACK_NOT_RUN,
} ble_cmd_ret_e;
//--------------------------------------------
enum {
ATT_OP_AUTO_READ_CCC = 0,
ATT_OP_NOTIFY = 1,
ATT_OP_INDICATE = 2,
ATT_OP_READ,
ATT_OP_READ_LONG,
ATT_OP_WRITE,
ATT_OP_WRITE_WITHOUT_RESPOND,
//add here
ATT_OP_CMD_MAX = 15,
};
extern ble_cmd_ret_e ble_user_cmd_prepare(ble_cmd_type_e cmd, int argc, ...);
struct conn_update_param_t {
u16 interval_min;
u16 interval_max;
u16 latency;
u16 timeout;
};
typedef enum {
PFL_SERVER_UUID16 = 1,
PFL_SERVER_UUID128,
PFL_SERVER_ALL,
} search_profile_type_e;
//------
typedef struct {
uint16_t start_group_handle;
uint16_t end_group_handle;
uint16_t uuid16;
uint8_t uuid128[16];
} service_report_t; //==le_service_t
typedef struct {
uint16_t start_handle;
uint16_t value_handle;
uint16_t end_handle;
uint16_t properties;
uint16_t uuid16;
uint8_t uuid128[16];
} charact_report_t; //==le_characteristic_t
typedef struct {
service_report_t services;
charact_report_t characteristic;
u16 service_index;
u16 characteristic_index;
} search_result_t;
//------
struct create_conn_param_t {
u16 conn_interval;
u16 conn_latency;
u16 supervision_timeout;
u8 peer_address_type;
u8 peer_address[6];
} _GNU_PACKED_;
typedef struct {
u8 event_type;
u8 address_type;
u8 address[6];
u8 reserve;
u8 length;
u8 data[0];
} adv_report_t;
typedef struct {
u16 packet_type;
u16 value_handle;
u16 value_offset;
u16 blob_length;
u8 *blob;
} att_data_report_t;
//---------------
void ble_set_gap_role(u8 role);
void att_ccc_config_init(void);
void att_set_ccc_config(uint16_t handle, uint16_t cfg);
uint16_t att_get_ccc_config(uint16_t handle);
void user_client_init(u16 handle, u8 *buffer, u16 buffer_size);
#endif
loader/ble_app_ota_update/include_lib/btstack/bluetooth.h
+541
View File
@@ -0,0 +1,541 @@
#ifndef _BLUETOOTH_H_
#define _BLUETOOTH_H_
#include "typedef.h"
//LE
#define ISO_SDU_DTAT_LENGTH 0x032c //812byte
#define ISO_PDU_DTAT_LENGTH 251 //251byte
#define ISO_PDU_INTERVAL_M_S 0x4e20 //20ms
#define ISO_PDU_INTERVAL_S_M 0x4e20 //20ms
#define HCI_ISO_DATA_PACKET 0x05
#define HCI_COMMAND_DATA_PACKET 0x01
#define HCI_ACL_DATA_PACKET 0x02
#define HCI_SCO_DATA_PACKET 0x03
#define HCI_EVENT_PACKET 0x04
// OGFs
#define OGF_LINK_CONTROL 0x01
#define OGF_LINK_POLICY 0x02
#define OGF_CONTROLLER_BASEBAND 0x03
#define OGF_INFORMATIONAL_PARAMETERS 0x04
#define OGF_STATUS_PARAMETERS 0x05
#define OGF_TESTING 0x06
#define OGF_LE_CONTROLLER 0x08
#define OGF_VENDOR_LE_CONTROLLER 0x3e
#define OGF_VENDOR 0x3f
// Events from host controller to host
/**
* @format 1
* @param status
*/
#define HCI_EVENT_INQUIRY_COMPLETE 0x01
/**
* @format 1B11132
* @param num_responses
* @param bd_addr
* @param page_scan_repetition_mode
* @param reserved1
* @param reserved2
* @param class_of_device
* @param clock_offset
*/
#define HCI_EVENT_INQUIRY_RESULT 0x02
/**
* @format 12B11
* @param status
* @param connection_handle
* @param bd_addr
* @param link_type
* @param encryption_enabled
*/
#define HCI_EVENT_CONNECTION_COMPLETE 0x03
/**
* @format B31
* @param bd_addr
* @param class_of_device
* @param link_type
*/
#define HCI_EVENT_CONNECTION_REQUEST 0x04
/**
* @format 121
* @param status
* @param connection_handle
* @param reason
*/
#define HCI_EVENT_DISCONNECTION_COMPLETE 0x05
/**
* @format 12
* @param status
* @param connection_handle
*/
#define HCI_EVENT_AUTHENTICATION_COMPLETE 0x06
/**
* @format 1BN
* @param status
* @param bd_addr
* @param remote_name
*/
#define HCI_EVENT_REMOTE_NAME_REQUEST_COMPLETE 0x07
/**
* @format 121
* @param status
* @param connection_handle
* @param encryption_enabled
*/
#define HCI_EVENT_ENCRYPTION_CHANGE 0x08
/**
* @format 12
* @param status
* @param connection_handle
*/
#define HCI_EVENT_CHANGE_CONNECTION_LINK_KEY_COMPLETE 0x09
/**
* @format 121
* @param status
* @param connection_handle
* @param key_flag
*/
#define HCI_EVENT_MASTER_LINK_KEY_COMPLETE 0x0A
#define HCI_EVENT_READ_REMOTE_SUPPORTED_FEATURES_COMPLETE 0x0B
#define HCI_EVENT_READ_REMOTE_VERSION_INFORMATION_COMPLETE 0x0C
#define HCI_EVENT_QOS_SETUP_COMPLETE 0x0D
/**
* @format 12R
* @param num_hci_command_packets
* @param command_opcode
* @param return_parameters
*/
#define HCI_EVENT_COMMAND_COMPLETE 0x0E
/**
* @format 112
* @param status
* @param num_hci_command_packets
* @param command_opcode
*/
#define HCI_EVENT_COMMAND_STATUS 0x0F
/**
* @format 1
* @param hardware_code
*/
#define HCI_EVENT_HARDWARE_ERROR 0x10
#define HCI_EVENT_FLUSH_OCCURRED 0x11
/**
* @format 1B1
* @param status
* @param bd_addr
* @param role
*/
#define HCI_EVENT_ROLE_CHANGE 0x12
// TODO: number_of_handles 1, connection_handle[H*i], hc_num_of_completed_packets[2*i]
#define HCI_EVENT_NUMBER_OF_COMPLETED_PACKETS 0x13
/**
* @format 1H12
* @param status
* @param handle
* @param mode
* @param interval
*/
#define HCI_EVENT_MODE_CHANGE_EVENT 0x14
// TODO: num_keys, bd_addr[B*i], link_key[16 octets * i]
#define HCI_EVENT_RETURN_LINK_KEYS 0x15
/**
* @format B
* @param bd_addr
*/
#define HCI_EVENT_PIN_CODE_REQUEST 0x16
/**
* @format B
* @param bd_addr
*/
#define HCI_EVENT_LINK_KEY_REQUEST 0x17
// TODO: bd_addr B, link_key 16octets, key_type 1
#define HCI_EVENT_LINK_KEY_NOTIFICATION 0x18
/**
* @format 1
* @param link_type
*/
#define HCI_EVENT_DATA_BUFFER_OVERFLOW 0x1A
/**
* @format H1
* @param handle
* @param lmp_max_slots
*/
#define HCI_EVENT_MAX_SLOTS_CHANGED 0x1B
/**
* @format 1H2
* @param status
* @param handle
* @param clock_offset
*/
#define HCI_EVENT_READ_CLOCK_OFFSET_COMPLETE 0x1C
/**
* @format 1H2
* @param status
* @param handle
* @param packet_types
* @pnote packet_type is in plural to avoid clash with Java binding Packet.getPacketType()
*/
#define HCI_EVENT_CONNECTION_PACKET_TYPE_CHANGED 0x1D
#define HCI_EVENT_PAGE_SCAN_REPETITION_MODE_CHANGE 0x20
/**
* @format 1B11321
* @param num_responses
* @param bd_addr
* @param page_scan_repetition_mode
* @param reserved
* @param class_of_device
* @param clock_offset
* @param rssi
*/
#define HCI_EVENT_INQUIRY_RESULT_WITH_RSSI 0x22
#define HCI_EVENT_READ_REMOTE_EXTERNED_FEATURES_COMPLETE 0x23
/**
* @format 1HB111221
* @param status
* @param handle
* @param bd_addr
* @param link_type
* @param transmission_interval
* @param retransmission_interval
* @param rx_packet_length
* @param tx_packet_length
* @param air_mode
*/
#define HCI_EVENT_SYNCHRONOUS_CONNECTION_COMPLETE 0x2C
// TODO: serialize extended_inquiry_response and provide parser
/**
* @format 1B11321
* @param num_responses
* @param bd_addr
* @param page_scan_repetition_mode
* @param reserved
* @param class_of_device
* @param clock_offset
* @param rssi
*/
#define HCI_EVENT_EXTENDED_INQUIRY_RESPONSE 0x2F
#define HCI_EVENT_EXTENDED_INQUIRY_RESULT 0x2F
/**
* @format 1H
* @param status
* @param handle
*/
#define HCI_EVENT_ENCRYPTION_KEY_REFRESH_COMPLETE 0x30
#define HCI_EVENT_IO_CAPABILITY_REQUEST 0x31
#define HCI_EVENT_IO_CAPABILITY_RESPONSE 0x32
/**
* @format B4
* @param bd_addr
* @param numeric_value
*/
#define HCI_EVENT_USER_CONFIRMATION_REQUEST 0x33
/**
* @format B
* @param bd_addr
*/
#define HCI_EVENT_USER_PASSKEY_REQUEST 0x34
/**
* @format B
* @param bd_addr
*/
#define HCI_EVENT_REMOTE_OOB_DATA_REQUEST 0x35
/**
* @format 1B
* @param status
* @param bd_addr
*/
#define HCI_EVENT_SIMPLE_PAIRING_COMPLETE 0x36
#define HCI_EVENT_LINK_SUPPERVISION_TIMEOUT_CHANGE_EVENT 0x38
#define HCI_EVENT_USER_PRESSKEY_NOTIFICATION 0x3B
#define HCI_EVENT_REMOTE_KEYPRESS_NOTIFICATION 0x3C
#define HCI_EVENT_REMOTE_SUPPORTED_FEATURES_NOTIFICATION 0x3D
#define HCI_EVENT_LE_META 0x3E
// last used HCI_EVENT in 2.1 is 0x3d
// last used HCI_EVENT in 4.1 is 0x57
#define HCI_EVENT_VENDOR_SETUP_COMPLETE 0xF9
#define HCI_EVENT_VENDOR_DUT 0xFA
#define HCI_EVENT_VENDOR_OSC_INTERNAL 0xFB
#define HCI_EVENT_VENDOR_FAST_TEST 0xFC
#define HCI_EVENT_VENDOR_REMOTE_UPDATE 0xFD
#define HCI_EVENT_VENDOR_REMOTE_TEST 0xFE
#define HCI_EVENT_VENDOR_SPECIFIC 0xFF
/**
* @format 11H11B2221
* @param subevent_code
* @param status
* @param connection_handle
* @param role
* @param peer_address_type
* @param peer_address
* @param conn_interval
* @param conn_latency
* @param supervision_timeout
* @param master_clock_accuracy
*/
#define HCI_SUBEVENT_LE_CONNECTION_COMPLETE 0x01
// array of advertisements, not handled by event accessor generator
#define HCI_SUBEVENT_LE_ADVERTISING_REPORT 0x02
/**
* @format 11H222
* @param subevent_code
* @param status
* @param connection_handle
* @param conn_interval
* @param conn_latency
* @param supervision_timeout
*/
#define HCI_SUBEVENT_LE_CONNECTION_UPDATE_COMPLETE 0x03
/**
* @format 1HD2
* @param subevent_code
* @param connection_handle
* @param random_number
* @param encryption_diversifier
*/
#define HCI_SUBEVENT_LE_READ_REMOTE_USED_FEATURES_COMPLETE 0x04
/**
* @format 1HD2
* @param subevent_code
* @param connection_handle
* @param random_number
* @param encryption_diversifier
*/
#define HCI_SUBEVENT_LE_LONG_TERM_KEY_REQUEST 0x05
/**
* @format 1H2222
* @param subevent_code
* @param connection_handle
* @param interval_min
* @param interval_max
* @param latency
* @param timeout
*/
#define HCI_SUBEVENT_LE_REMOTE_CONNECTION_PARAMETER_REQUEST 0x06
/**
* @format 1H2222
* @param subevent_code
* @param connection_handle
* @param max_tx_octets
* @param max_tx_time
* @param max_rx_octets
* @param max_rx_time
*/
#define HCI_SUBEVENT_LE_DATA_LENGTH_CHANGE 0x07
/**
* @format 11QQ
* @param subevent_code
* @param status
* @param dhkey_x x coordinate of P256 public key
* @param dhkey_y y coordinate of P256 public key
*/
#define HCI_SUBEVENT_LE_READ_LOCAL_P256_PUBLIC_KEY_COMPLETE 0x08
/**
* @format 11Q
* @param subevent_code
* @param status
* @param dhkey Diffie-Hellman key
*/
#define HCI_SUBEVENT_LE_GENERATE_DHKEY_COMPLETE 0x09
/**
* @format 11H11BBB2221
* @param subevent_code
* @param status
* @param connection_handle
* @param role
* @param peer_address_type
* @param perr_addresss
* @param local_resolvable_private_addres
* @param peer_resolvable_private_addres
* @param conn_interval
* @param conn_latency
* @param supervision_timeout
* @param master_clock_accuracy
*/
#define HCI_SUBEVENT_LE_ENHANCED_CONNECTION_COMPLETE 0x0A
// array of advertisements, not handled by event accessor generator
#define HCI_SUBEVENT_LE_DIRECT_ADVERTISING_REPORT 0x0B
/**
* @format 11211
* @param subevent_code
* @param status
* @param connection_handle
* @param TX_PHY
* @param RX_PHY
*/
#define HCI_SUBEVENT_LE_PHY_UPDATE_COMPLETE 0x0C
// array of advertisements, not handled by event accessor generator
#define HCI_SUBEVENT_LE_EXTENDED_ADVERTISING_REPORT 0x0D
#define HCI_SUBEVENT_LE_PERIODIC_ADVERTISING_SYNC_ESTABLISHED 0x0E
/**
* @format 1211111B
* @param subevent_code
* @param sync_handle
* @param tx_power
* @param rssi
* @param unused
* @param data_status
* @param data_length
* @param data
*/
#define HCI_SUBEVENT_LE_PERIODIC_ADVERTISING_REPORT 0x0F
/**
* @format 2
* @param sync_handle
*/
#define HCI_SUBEVENT_LE_PERIODIC_ADVERTISING_SYNC_LOST 0x10
/**
* @format
*/
#define HCI_SUBEVENT_LE_SCAN_TIMEOUT 0x11
/**
* @format 1121
* @param subevent_code
* @param status
* @param advertising_handle
* @param connection_handle
* @param num_completed_extended_advertising_events
*/
#define HCI_SUBEVENT_LE_ADVERTISING_SET_TERMINATED 0x12
/**
* @format 1116
* @param subevent_code
* @param advertising_handle
* @param scanner_address_type
* @param scanner_address
*/
#define HCI_SUBEVENT_LE_SCAN_REQUEST_RECEIVED 0x13
/**
* @format 21
* @param subevent_code
* @param connection_handle
* @param channel_selection_algorithm
*/
#define HCI_SUBEVENT_LE_CHANNEL_SELECTION_ALGORITHM 0x14
/**
* compact HCI Command packet description
*/
typedef struct {
uint16_t opcode;
const char *format;
} hci_cmd_t;
int hci_send_cmd(const hci_cmd_t *cmd, ...);
extern const hci_cmd_t hci_reset;
extern const hci_cmd_t hci_read_bd_addr;
extern const hci_cmd_t hci_read_local_supported_features;
extern const hci_cmd_t hci_read_buffer_size;
extern const hci_cmd_t hci_read_local_supported_commands;
extern const hci_cmd_t hci_read_local_version_information;
extern const hci_cmd_t hci_read_le_host_supported;
extern const hci_cmd_t hci_read_local_name;
extern const hci_cmd_t hci_write_class_of_device;
extern const hci_cmd_t hci_write_local_name;
extern const hci_cmd_t hci_write_scan_enable;
extern const hci_cmd_t hci_set_event_mask;
extern const hci_cmd_t hci_le_add_device_to_white_list;
extern const hci_cmd_t hci_le_clear_white_list;
extern const hci_cmd_t hci_le_connection_update;
extern const hci_cmd_t hci_le_create_connection;
extern const hci_cmd_t hci_le_create_connection_cancel;
extern const hci_cmd_t hci_le_encrypt;
extern const hci_cmd_t hci_le_generate_dhkey;
extern const hci_cmd_t hci_le_long_term_key_negative_reply;
extern const hci_cmd_t hci_le_long_term_key_request_reply;
extern const hci_cmd_t hci_le_rand;
extern const hci_cmd_t hci_le_read_advertising_channel_tx_power;
extern const hci_cmd_t hci_le_read_buffer_size;
extern const hci_cmd_t hci_le_read_channel_map;
extern const hci_cmd_t hci_le_read_local_p256_public_key;
extern const hci_cmd_t hci_le_read_maximum_data_length;
extern const hci_cmd_t hci_le_read_remote_used_features;
extern const hci_cmd_t hci_le_read_suggested_default_data_length;
extern const hci_cmd_t hci_le_read_supported_features;
extern const hci_cmd_t hci_le_read_supported_states;
extern const hci_cmd_t hci_le_read_white_list_size;
extern const hci_cmd_t hci_le_receiver_test;
extern const hci_cmd_t hci_le_remove_device_from_white_list;
extern const hci_cmd_t hci_le_set_advertise_enable;
extern const hci_cmd_t hci_le_set_advertising_data;
extern const hci_cmd_t hci_le_set_advertising_parameters;
extern const hci_cmd_t hci_le_set_data_length;
extern const hci_cmd_t hci_le_set_event_mask;
extern const hci_cmd_t hci_le_set_host_channel_classification;
extern const hci_cmd_t hci_le_set_random_address;
extern const hci_cmd_t hci_le_set_scan_enable;
extern const hci_cmd_t hci_le_set_scan_parameters;
extern const hci_cmd_t hci_le_set_scan_response_data;
extern const hci_cmd_t hci_le_start_encryption;
extern const hci_cmd_t hci_le_test_end;
extern const hci_cmd_t hci_le_transmitter_test;
extern const hci_cmd_t hci_le_write_suggested_default_data_length;
extern const hci_cmd_t hci_le_set_phy;
extern const hci_cmd_t hci_le_set_ext_advertising_parameters;
extern const hci_cmd_t hci_le_set_ext_advertising_data;
extern const hci_cmd_t hci_le_set_ext_advertise_enable;
extern const hci_cmd_t hci_le_set_ext_scan_parameters;
extern const hci_cmd_t hci_le_set_ext_scan_enable;
#endif
loader/ble_app_ota_update/include_lib/btstack/bt_profile_config.h
+29
View File
@@ -0,0 +1,29 @@
#ifndef BT_PROFILE_H
#define BT_PROFILE_H
#define BT_BTSTACK_CLASSIC BIT(0)
#define BT_BTSTACK_LE_ADV BIT(1)
#define BT_BTSTACK_LE BIT(2)
extern const int config_stack_modules;
#define STACK_MODULES_IS_SUPPORT(x) (config_stack_modules & (x))
extern u8 app_bredr_pool[];
extern u8 app_le_pool[];
extern u8 app_l2cap_pool[];
extern u8 app_bredr_profile[];
extern u16 get_bredr_pool_len(void);
extern u16 get_le_pool_len(void);
extern u16 get_l2cap_stack_len(void);
extern u16 get_profile_pool_len(void);
#endif
loader/ble_app_ota_update/include_lib/btstack/le_user.h
+250
View File
@@ -0,0 +1,250 @@
#ifndef _LE_USER_H_
#define _LE_USER_H_
#if defined __cplusplus
extern "C" {
#endif
#include "btstack/ble_api.h"
typedef void (*btstack_packet_handler_t)(uint8_t packet_type, uint16_t channel, uint8_t *packet, uint16_t size);
typedef int (*sm_stack_packet_handler_t)(uint8_t packet_type, uint8_t *packet, uint16_t size);
typedef void (*ble_cbk_handler_t)(void);
// Minimum/default MTU
#define ATT_DEFAULT_MTU 23
#define BT_NAME_LEN_MAX 29
#define ADV_RSP_PACKET_MAX 31
// hci con handles (12 bit): 0x0000..0x0fff
#define HCI_CON_HANDLE_INVALID 0xffff
#define BTSTACK_EVENT_STATE 0x60
#define L2CAP_EVENT_CONNECTION_PARAMETER_UPDATE_RESPONSE 0x77
#define ATT_EVENT_MTU_EXCHANGE_COMPLETE 0xB5
#define ATT_EVENT_HANDLE_VALUE_INDICATION_COMPLETE 0xB6
#define ATT_EVENT_CAN_SEND_NOW 0xB7
#define SM_EVENT_JUST_WORKS_REQUEST 0xD0
#define SM_EVENT_PASSKEY_DISPLAY_NUMBER 0xD2
#define ATT_TRANSACTION_MODE_NONE 0x0
#define ATT_TRANSACTION_MODE_ACTIVE 0x1
#define ATT_TRANSACTION_MODE_EXECUTE 0x2
#define ATT_TRANSACTION_MODE_CANCEL 0x3
#define ATT_TRANSACTION_MODE_VALIDATE 0x4
#define GATT_CLIENT_CHARACTERISTICS_CONFIGURATION_NONE 0
#define GATT_CLIENT_CHARACTERISTICS_CONFIGURATION_NOTIFICATION 1
#define GATT_CLIENT_CHARACTERISTICS_CONFIGURATION_INDICATION 2
#define ATT_PROPERTY_BROADCAST 0x01
#define ATT_PROPERTY_READ 0x02
#define ATT_PROPERTY_WRITE_WITHOUT_RESPONSE 0x04
#define ATT_PROPERTY_WRITE 0x08
#define ATT_PROPERTY_NOTIFY 0x10
#define ATT_PROPERTY_INDICATE 0x20
#define GATT_EVENT_NOTIFICATION 0xA7
#define GATT_EVENT_INDICATION 0xA8
#define GATT_EVENT_CHARACTERISTIC_VALUE_QUERY_RESULT 0xA5
#define GATT_EVENT_LONG_CHARACTERISTIC_VALUE_QUERY_RESULT 0xA6
// #define GATT_EVENT_SERVICE_QUERY_RESULT 0xA1
// #define GATT_EVENT_CHARACTERISTIC_QUERY_RESULT 0xA2
// #define GATT_EVENT_QUERY_COMPLETE 0xA0
#define GAP_EVENT_ADVERTISING_REPORT 0xE2
// Authentication requirement flags
#define SM_AUTHREQ_NO_BONDING 0x00
#define SM_AUTHREQ_BONDING 0x01
#define SM_AUTHREQ_MITM_PROTECTION 0x04
#define SM_AUTHREQ_SECURE_CONNECTION 0x08
#define SM_AUTHREQ_KEYPRESS 0x10
#define L2CAP_EVENT_CONNECTION_PARAMETER_UPDATE_RESPONSE 0x77
#define BT_OP_SUCCESS 0x00
#define BT_ERR_ADVERTISING_TIMEOUT 0x3C
//--------------------------------------------
enum {
HCI_STATE_OFF = 0,
HCI_STATE_INITIALIZING,
HCI_STATE_WORKING,
HCI_STATE_HALTING,
HCI_STATE_SLEEPING,
HCI_STATE_FALLING_ASLEEP
} ;
// IO Capability Values
typedef enum {
IO_CAPABILITY_DISPLAY_ONLY = 0,
IO_CAPABILITY_DISPLAY_YES_NO,
IO_CAPABILITY_KEYBOARD_ONLY,
IO_CAPABILITY_NO_INPUT_NO_OUTPUT,
IO_CAPABILITY_KEYBOARD_DISPLAY, // not used by secure simple pairing
} io_capability_t;
struct ble_server_operation_t {
int(*adv_enable)(void *priv, u32 enable);
int(*disconnect)(void *priv);
int(*get_buffer_vaild)(void *priv);
int(*send_data)(void *priv, void *buf, u16 len);
int(*regist_wakeup_send)(void *priv, void *cbk);
int(*regist_recieve_cbk)(void *priv, void *cbk);
int(*regist_state_cbk)(void *priv, void *cbk);
int(*latency_enable)(void *priv, u32 enable);
};
void ble_get_server_operation_table(struct ble_server_operation_t **interface_pt);
struct ble_client_operation_t {
int(*scan_enable)(void *priv, u32 enable);
int(*disconnect)(void *priv);
int(*get_buffer_vaild)(void *priv);
int(*write_data)(void *priv, void *buf, u16 len);
int(*read_do)(void *priv);
int(*regist_wakeup_send)(void *priv, void *cbk);
int(*regist_recieve_cbk)(void *priv, void *cbk);
int(*regist_state_cbk)(void *priv, void *cbk);
};
void ble_get_client_operation_table(struct ble_client_operation_t **interface_pt);
typedef struct {
//base info
uint8_t type; ///< See <btstack/hci_cmds.h> SM_...
uint8_t size;
hci_con_handle_t con_handle;
uint8_t addr_type;
uint8_t address[6];
//extend info
uint8_t data[4];
} sm_just_event_t;
static inline uint32_t ble_min(uint32_t a, uint32_t b)
{
return a < b ? a : b;
}
//---------------------------------------------------------------------------------------------------
// ATT Client Read Callback for Dynamic Data
// - if buffer == NULL, don't copy data, just return size of value
// - if buffer != NULL, copy data and return number bytes copied
// @param con_handle of hci le connection
// @param attribute_handle to be read
// @param offset defines start of attribute value
// @param buffer
// @param buffer_size
typedef uint16_t (*att_read_callback_t)(uint16_t con_handle, uint16_t attribute_handle, uint16_t offset, uint8_t *buffer, uint16_t buffer_size);
// ATT Client Write Callback for Dynamic Data
// @param con_handle of hci le connection
// @param attribute_handle to be written
// @param transaction - ATT_TRANSACTION_MODE_NONE for regular writes, ATT_TRANSACTION_MODE_ACTIVE for prepared writes and ATT_TRANSACTION_MODE_EXECUTE
// @param offset into the value - used for queued writes and long attributes
// @param buffer
// @param buffer_size
// @param signature used for signed write commmands
// @returns 0 if write was ok, ATT_ERROR_PREPARE_QUEUE_FULL if no space in queue, ATT_ERROR_INVALID_OFFSET if offset is larger than max buffer
typedef int (*att_write_callback_t)(uint16_t con_handle, uint16_t attribute_handle, uint16_t transaction_mode, uint16_t offset, uint8_t *buffer, uint16_t buffer_size);
//----------------------------------------
extern uint16_t little_endian_read_16(const uint8_t *buffer, int pos);
extern uint32_t little_endian_read_24(const uint8_t *buffer, int pos);
extern uint32_t little_endian_read_32(const uint8_t *buffer, int pos);
//----------------------------------------
//--------------------------------------
static inline hci_con_handle_t hci_subevent_le_connection_update_complete_get_connection_handle(const uint8_t *event)
{
return little_endian_read_16(event, 4);
}
static inline uint16_t hci_subevent_le_connection_update_complete_get_conn_interval(const uint8_t *event)
{
return little_endian_read_16(event, 6);
}
static inline uint16_t hci_subevent_le_connection_update_complete_get_conn_latency(const uint8_t *event)
{
return little_endian_read_16(event, 8);
}
static inline uint16_t hci_subevent_le_connection_update_complete_get_supervision_timeout(const uint8_t *event)
{
return little_endian_read_16(event, 10);
}
static inline uint8_t hci_event_packet_get_type(const uint8_t *event)
{
return event[0];
}
static inline uint8_t hci_event_le_meta_get_subevent_code(const uint8_t *event)
{
return event[2];
}
static inline uint16_t att_event_mtu_exchange_complete_get_MTU(const uint8_t *event)
{
return little_endian_read_16(event, 4);
}
static inline uint8_t btstack_event_state_get_state(const uint8_t *event)
{
return event[2];
}
static inline uint16_t hci_event_disconnection_complete_get_connection_handle(const uint8_t *event)
{
return little_endian_read_16(event, 3);
}
static inline hci_con_handle_t hci_subevent_le_connection_complete_get_connection_handle(const uint8_t *event)
{
return little_endian_read_16(event, 4);
}
static inline uint16_t hci_subevent_le_connection_complete_get_conn_interval(const uint8_t *event)
{
return little_endian_read_16(event, 14);
}
static inline hci_con_handle_t att_event_mtu_exchange_complete_get_handle(const uint8_t *event)
{
return little_endian_read_16(event, 2);
}
static inline hci_con_handle_t sm_event_just_works_request_get_handle(const uint8_t *event)
{
return little_endian_read_16(event, 2);
}
extern void ble_sm_setup_init(io_capability_t io_type, u8 auth_req, uint8_t min_key_size, u8 security_en);
extern void sm_just_works_confirm(hci_con_handle_t con_handle);
extern void sm_init(void);
extern void sm_set_io_capabilities(io_capability_t io_capability);
extern void sm_set_authentication_requirements(uint8_t auth_req);
extern void sm_set_encryption_key_size_range(uint8_t min_size, uint8_t max_size);
extern void sm_set_request_security(int enable);
extern void sm_event_callback_set(void(*cbk_sm_ph)(uint8_t packet_type, uint16_t channel, uint8_t *packet, uint16_t size));
extern void att_server_init(uint8_t const *db, att_read_callback_t read_callback, att_write_callback_t write_callback);
extern void att_server_register_packet_handler(btstack_packet_handler_t handler);
extern void hci_event_callback_set(void(*cbk_ph)(uint8_t packet_type, uint16_t channel, uint8_t *packet, uint16_t size));
extern void ll_hci_connection_updata(u8 *data);
#endif
loader/ble_app_ota_update/include_lib/driver/common/dec.h
+16
View File
@@ -0,0 +1,16 @@
#ifndef __DEC_H__
#define __DEC_H__
#include "typedef.h"
void doe(u16 k, void *pBuf, u32 lenIn, u32 addr);
u16 doe_continue(u16 k, void *pBuf, u32 lenIn, u8 init_flag);
void decode(u16 key, u8 *buf, u32 len, u32 offset);
u8 dec_isd_cfg_ini(const char *cfg, void *value, const u8 *ptr);
#endif
loader/ble_app_ota_update/include_lib/driver/common/printf.h
+40
View File
@@ -0,0 +1,40 @@
#ifndef __PRINTF_H__
#define __PRINTF_H__
#include <stdarg.h>
#include "typedef.h"
//#define NOFLOAT
// #ifdef __DEBUG
void put_u4hex(u8 dat);
void put_u8hex(unsigned char dat);
void put_u16hex(unsigned short dat);
void put_u32hex(unsigned int dat);
void put_buf(const u8 *buf, u32 len);
void printf_buf(u8 *buf, u32 len);
#ifdef __DEBUG
int printf(const char *format, ...);
int puts(const char *out);
#else
// #define put_u4hex(x)
// #define put_u8hex(x)
// #define put_u16hex(x)
// #define put_u32hex(x)
// #define put_buf(a, b)
// #define printf_buf(a, b)
#define printf(...)
#define puts(x)
#endif
int lib_putchar(int c);
extern int putchar(int a);
#endif
loader/ble_app_ota_update/include_lib/driver/cpu/br35/clock.h
+45
View File
@@ -0,0 +1,45 @@
#ifndef __CLOCK_H__
#define __CLOCK_H__
#include "typedef.h"
#define MHz (1000000L)
#define OSC_FREQ 24000000
#define SYS_CLK 48000000
enum {
UART_CLOCK_IN_DISABLE = 0,
UART_CLOCK_IN_STD48M,
UART_CLOCK_IN_STD24M,
UART_CLOCK_IN_EXT,
UART_CLOCK_IN_LSB,
};
#define UART_CLOCK_IN(x) SFR(JL_LSBCLK->PRP_CON0, 12, 3, x)
#define BT_CLOCK_IN(x) //SFR(JL_CLOCK->CLK_CON1, 14, 2, x)
//for MACRO - BT_CLOCK_IN
enum {
BT_CLOCK_IN_PLL48M = 0,
BT_CLOCK_IN_HSB,
BT_CLOCK_IN_LSB,
BT_CLOCK_IN_DISABLE,
};
void lrc_init(void);
void sys_clk_init(u32 osc_freq, u32 sys_clk);
void btosc_upgrade_cfg(void *cfg);
void sys_clk_reinit(void *clk_argv);
u32 clk_get(const char *clk);
#define CLR_DVDD_POR_PND() JL_HSBCLK->PWR_CON |= BIT(11)
#endif
loader/ble_app_ota_update/include_lib/driver/cpu/br35/crc.h
+21
View File
@@ -0,0 +1,21 @@
#ifndef __CRC_H__
#define __CRC_H__
#include "typedef.h"
u16 chip_crc16(void *ptr, u32 len);
u16 chip_crc16_with_init(void *ptr, u32 len, u16 init);
void CrcDecode(void *buf, u16 len);
void crc_encode(void *buf, u32 len, const u8 *crckey, u32 offset);
#define CRC16(x,y) chip_crc16(x,y)
#endif
loader/ble_app_ota_update/include_lib/driver/cpu/br35/csfr.h
+412
View File
@@ -0,0 +1,412 @@
//*********************************************************************************//
// Module name : csfr.h //
// Description : q32DSP core sfr define //
// By Designer : zequan_liu //
// Dat changed : //
//*********************************************************************************//
#ifndef __Q32DSP_CSFR__
#define __Q32DSP_CSFR__
#define __RW volatile // read write
#define __RO volatile const // only read
#define __WO volatile // only write
#define __u8 unsigned int // u8 to u32 special for struct
#define __u16 unsigned int // u16 to u32 special for struct
#define __u32 unsigned int
#define csfr_base 0xff0000
//*********************************************************************************
//
// hcore_sfr
//
//*********************************************************************************
//............. 0x0000 - 0x00ff............
typedef struct {
__RW __u32 CON0;
__RW __u32 FTMAX;
} JL_CMNG_TypeDef;
#define JL_CMNG_BASE (csfr_base + map_adr(0x00, 0x00))
#define JL_CMNG ((JL_CMNG_TypeDef *)JL_CMNG_BASE)
//............. 0x0100 - 0x01ff............
//typedef struct {
// __RW __u32 CON;
// __RW __u32 KEY;
//} JL_SDTAP_TypeDef;
//#define JL_SDTAP_BASE (csfr_base + map_adr(0x01, 0x00))
//#define JL_SDTAP ((JL_SDTAP_TypeDef *)JL_SDTAP_BASE)
//............. 0x0200 - 0x02ff............
typedef struct {
__RW __u32 WREN;
__RW __u32 CON0;
__RW __u32 CON1;
__RW __u32 CON2;
__RW __u32 CON3;
__RW __u32 MSG0;
__RW __u32 MSG1;
__RW __u32 MSG2;
__RW __u32 MSG3;
__RO __u32 ID;
} JL_CEMU_TypeDef;
#define JL_CEMU_BASE (csfr_base + map_adr(0x02, 0x00))
#define JL_CEMU ((JL_CEMU_TypeDef *)JL_CEMU_BASE)
//............. 0x0300 - 0x03ff............
#define MPU_INV (1<<31)
#define MPU_PWEN (1<<16)
#define MPU_PREN (1<<8)
#define MPU_PEN (MPU_PWEN | MPU_PREN)
#define MPU_XEN (1<<2)
#define MPU_WEN (1<<1)
#define MPU_REN (1<<0)
#define MPU_IDx_cfg(n, id) (id<<(n*8))
#define MPU_IDx_pen(n, pr, pw) ((pr<<(9+n)) | (pw<<(17+n)))
typedef struct {
__RW __u32 CON[15]; // 0-1 used in br35
__RO __u32 REV0;
__RW __u32 CID[15]; // 0-1 used in br35
__RO __u32 REV1;
__RW __u32 BEG[15]; // 0-1 used in br35
__RO __u32 REV2;
__RW __u32 END[15]; // 0-1 used in br35
__RW __u32 WREN;
} JL_MPU_TypeDef;
#define JL_MPU_BASE (csfr_base + map_adr(0x03, 0x00))
#define JL_MPU ((JL_MPU_TypeDef *)JL_MPU_BASE)
//............. 0x0400 - 0x04ff............
typedef struct {
__RW __u32 CON;
__RW __u32 TLB1_BEG;
__RW __u32 TLB1_END;
} JL_MMU_TypeDef;
#define JL_MMU_BASE (csfr_base + map_adr(0x04, 0x00))
#define JL_MMU ((JL_MMU_TypeDef *)JL_MMU_BASE)
typedef struct {
short page: 14;
short vld: 1;
} JL_MMU_TLB1_TypeDef;
#define JL_MMU_TLB1 ((JL_MMU_TLB1_TypeDef *)(JL_MMU->TLB1_BEG))
//............. 0x0500 - 0x05ff............
//#define JL_TypeDef_L1P JL_TypeDef_q32DSP_ICU
#define JL_TypeDef_L1P JL_TypeDef_q32DSP_DCU
#define JL_L1P_BASE (csfr_base + map_adr(0x05, 0x00))
#define JL_L1P ((JL_TypeDef_L1P *)JL_L1P_BASE)
//............. 0x0600 - 0x06ff............
#define JL_TypeDef_L2I JL_TypeDef_q32DSP_ICU
#define JL_L2I_BASE (csfr_base + map_adr(0x06, 0x00))
#define JL_L2I ((JL_TypeDef_L2I *)JL_L2I_BASE)
//............. 0x0700 - 0x07ff............
#define JL_TypeDef_L2D JL_TypeDef_q32DSP_DCU
#define JL_L2D_BASE (csfr_base + map_adr(0x07, 0x00))
#define JL_L2D ((JL_TypeDef_L2D *)JL_L2D_BASE)
//............. 0x0800 - 0x08ff............
typedef struct {
__RO __u32 CHIP_ID;
__RO __u32 CHIP_VER;
} JL_SYSTEM_TypeDef;
#define JL_SYSTEM_BASE (csfr_base + map_adr(0x08, 0x00))
#define JL_SYSTEM ((JL_SYSTEM_TypeDef *)JL_SYSTEM_BASE)
//............. 0x0900 - 0x09ff............
typedef struct {
__RW __u32 CON;
__RW __u32 BEG;
__RW __u32 END;
__RW __u32 DAT_VLD0;
__RW __u32 DAT_VLD1;
__RW __u32 DAT_VLD2;
__RW __u32 DAT_VLD3;
__RO __u32 ROM_CRC;
__RW __u32 MCFG0_SEL;
__RW __u32 MCFG1_SEL;
__RW __u32 MCFG0_RF1P;
__RW __u32 MCFG0_RF2P;
__RW __u32 MCFG0_RM1P;
__RW __u32 MCFG0_RM2P;
__RW __u32 MCFG0_VROM;
__RW __u32 MCFG1_RM1P;
__RW __u32 MCFG0_CON[2];
__RW __u32 MCFG1_CON[2];
} JL_MBIST_TypeDef;
#define JL_MBIST_BASE (csfr_base + map_adr(0x09, 0x00))
#define JL_MBIST ((JL_MBIST_TypeDef *)JL_MBIST_BASE)
//............. 0x0a00 - 0x0aff............
//typedef struct {
// __RW __u32 CON;
// __RW __u32 CADR;
// __RW __u32 ACC0L;
// __RW __u32 ACC0H;
// __RW __u32 ACC1L;
// __RW __u32 ACC1H;
// __RW __u32 CONST;
// __RW __u32 TEST1;
//} JL_FFT_TypeDef;
//
//#define JL_FFT_BASE (csfr_base + map_adr(0x0a, 0x00))
//#define JL_FFT ((JL_FFT_TypeDef *)JL_FFT_BASE)
//............. 0x0b00 - 0x0bff............
//typedef struct {
///* 00 */ __RW __u32 CON0;
///* 01 */ __RW __u32 LPEN_CON;
///* 02 */ __RW __u32 LSEN_CON;
///* 03 */ __RO __u32 LS_PND;
///* 04 */ __RO __u32 CE_PND;
///* 05 */ __RW __u32 LS_PRD_32K;
///* 06 */ __RW __u32 CE_PRD_32K;
///* 07 */ __RW __u32 LS_PRD_64K;
///* 08 */ __RW __u32 CE_PRD_64K;
///* 09 */ __RW __u32 LS_PRD_ROM;
///* 0a */ __RW __u32 CE_PRD_ROM;
//} JL_ATOLP_TypeDef;
//#define JL_ATOLP_BASE (csfr_base + map_adr(0x0b, 0x00))
//#define JL_ATOLP ((JL_ATOLP_TypeDef *)JL_ATOLP_BASE)
//*********************************************************************************
//
// q32DSP_sfr
//
//*********************************************************************************
//---------------------------------------------//
// q32DSP define
//---------------------------------------------//
#define q32DSP_sfr_offset 0x000800
#define q32DSP_sfr_base (csfr_base + 0xe000)
#define q32DSP_cpu_base (q32DSP_sfr_base + 0x0000)
#define q32DSP_icu_base (q32DSP_sfr_base + 0x0400)
#define q32DSP(n) ((JL_TypeDef_q32DSP *)(q32DSP_sfr_base + q32DSP_sfr_offset*n))
#define q32DSP_icu(n) ((JL_TypeDef_q32DSP_ICU *)(q32DSP_icu_base + q32DSP_sfr_offset*n))
//---------------------------------------------//
// q32DSP core sfr
//---------------------------------------------//
typedef struct {
/* 00 */ __RO __u32 DR00;
/* 01 */ __RO __u32 DR01;
/* 02 */ __RO __u32 DR02;
/* 03 */ __RO __u32 DR03;
/* 04 */ __RO __u32 DR04;
/* 05 */ __RO __u32 DR05;
/* 06 */ __RO __u32 DR06;
/* 07 */ __RO __u32 DR07;
/* 08 */ __RO __u32 DR08;
/* 09 */ __RO __u32 DR09;
/* 0a */ __RO __u32 DR10;
/* 0b */ __RO __u32 DR11;
/* 0c */ __RO __u32 DR12;
/* 0d */ __RO __u32 DR13;
/* 0e */ __RO __u32 DR14;
/* 0f */ __RO __u32 DR15;
/* 10 */ __RO __u32 RETI;
/* 11 */ __RO __u32 RETE;
/* 12 */ __RO __u32 RETX;
/* 13 */ __RO __u32 RETS;
/* 14 */ __RO __u32 SR04;
/* 15 */ __RO __u32 PSR;
/* 16 */ __RO __u32 CNUM;
/* 17 */ __RO __u32 SR07;
/* 18 */ __RO __u32 SR08;
/* 19 */ __RO __u32 SR09;
/* 1a */ __RO __u32 SR10;
/* 1b */ __RO __u32 ICFG;
/* 1c */ __RO __u32 USP;
/* 1d */ __RO __u32 SSP;
/* 1e */ __RO __u32 SP;
/* 1f */ __RO __u32 PCRS;
/* 20 */ __RW __u32 BPCON;
/* 21 */ __RW __u32 BSP;
/* 22 */ __RW __u32 BP0;
/* 23 */ __RW __u32 BP1;
/* 24 */ __RW __u32 BP2;
/* 25 */ __RW __u32 BP3;
/* 26 */ __WO __u32 CMD_PAUSE;
/* 27 */ __RW __u32 BP4;
/* 28 */ __RW __u32 BP5;
/* 29 */ __RW __u32 BP6;
/* 2a */ __RW __u32 BP7;
/* */ __RO __u32 REV2a[0x30 - 0x2a - 1];
/* 30 */ __RW __u32 PMU_CON0;
/* 31 */ __RW __u32 PMU_CON1;
/* 32 */ __RO __u32 RST_ADDR;
/* */ __RO __u32 REV32[0x3b - 0x32 - 1];
/* 3b */ __RW __u8 TTMR_CON;
/* 3c */ __RW __u32 TTMR_CNT;
/* 3d */ __RW __u32 TTMR_PRD;
/* */ __RO __u32 REV3d[0x40 - 0x3d - 1];
/* 40 */ __RW __u32 ICFG00;
/* 41 */ __RW __u32 ICFG01;
/* 42 */ __RW __u32 ICFG02;
/* 43 */ __RW __u32 ICFG03;
/* 44 */ __RW __u32 ICFG04;
/* 45 */ __RW __u32 ICFG05;
/* 46 */ __RW __u32 ICFG06;
/* 47 */ __RW __u32 ICFG07;
/* 48 */ __RW __u32 ICFG08;
/* 49 */ __RW __u32 ICFG09;
/* 4a */ __RW __u32 ICFG10;
/* 4b */ __RW __u32 ICFG11;
/* 4c */ __RW __u32 ICFG12;
/* 4d */ __RW __u32 ICFG13;
/* 4e */ __RW __u32 ICFG14;
/* 4f */ __RW __u32 ICFG15;
/* 50 */ __RW __u32 ICFG16;
/* 51 */ __RW __u32 ICFG17;
/* 52 */ __RW __u32 ICFG18;
/* 53 */ __RW __u32 ICFG19;
/* 54 */ __RW __u32 ICFG20;
/* 55 */ __RW __u32 ICFG21;
/* 56 */ __RW __u32 ICFG22;
/* 57 */ __RW __u32 ICFG23;
/* 58 */ __RW __u32 ICFG24;
/* 59 */ __RW __u32 ICFG25;
/* 5a */ __RW __u32 ICFG26;
/* 5b */ __RW __u32 ICFG27;
/* 5c */ __RW __u32 ICFG28;
/* 5d */ __RW __u32 ICFG29;
/* 5e */ __RW __u32 ICFG30;
/* 5f */ __RW __u32 ICFG31;
/* 60 */ __RO __u32 IPND0;
/* 61 */ __RO __u32 IPND1;
/* 62 */ __RO __u32 IPND2;
/* 63 */ __RO __u32 IPND3;
/* 64 */ __RO __u32 IPND4;
/* 65 */ __RO __u32 IPND5;
/* 66 */ __RO __u32 IPND6;
/* 67 */ __RO __u32 IPND7;
/* 68 */ __WO __u32 ILAT_SET;
/* 69 */ __WO __u32 ILAT_CLR;
/* 6a */ __RW __u32 IPMASK;
/* 6b */ __RW __u32 GIEMASK;
/* 6c */ __RW __u32 IWKUP_NUM;
/* */ __RO __u32 REV6c[0x70 - 0x6c - 1];
/* 70 */ __RW __u32 ETM_CON;
/* 71 */ __RO __u32 ETM_PC0;
/* 72 */ __RO __u32 ETM_PC1;
/* 73 */ __RO __u32 ETM_PC2;
/* 74 */ __RO __u32 ETM_PC3;
/* 75 */ __RW __u32 WP0_ADRH;
/* 76 */ __RW __u32 WP0_ADRL;
/* 77 */ __RW __u32 WP0_DATH;
/* 78 */ __RW __u32 WP0_DATL;
/* 79 */ __RO __u32 WP0_PC;
/* 7a */ __RO __u32 WP0_AMSG;
/* */ __RO __u32 REV7b[0x80 - 0x7a - 1];
/* 80 */ __RW __u32 EMU_CON;
/* 81 */ __RW __u32 EMU_MSG;
/* 82 */ __RW __u32 EMU_SSP_H;
/* 83 */ __RW __u32 EMU_SSP_L;
/* 84 */ __RW __u32 EMU_USP_H;
/* 85 */ __RW __u32 EMU_USP_L;
/* 86 */ __RW __u32 LIM_PC0_H;
/* 87 */ __RW __u32 LIM_PC0_L;
/* 88 */ __RW __u32 LIM_PC1_H;
/* 89 */ __RW __u32 LIM_PC1_L;
/* 8a */ __RW __u32 LIM_PC2_H;
/* 8b */ __RW __u32 LIM_PC2_L;
/* */ __RO __u32 REV8b[0x90 - 0x8b - 1];
/* 90 */ __RW __u32 ESU_CON;
/* 91 */ __RO __u32 CNT_CHIT;
/* 92 */ __RO __u32 CNT_CMIS;
/* 93 */ __RO __u32 CNT_FILL;
/* 94 */ __RO __u32 CNT_IHIT;
/* 95 */ __RO __u32 CNT_IMIS;
/* 96 */ __RO __u32 CNT_RHIT;
/* 97 */ __RO __u32 CNT_RMIS;
/* 98 */ __RO __u32 CNT_WHIT;
/* 99 */ __RO __u32 CNT_WMIS;
} JL_TypeDef_q32DSP;
//---------------------------------------------//
// q32DSP icache sfr
//---------------------------------------------//
typedef struct {
__RW __u32 CON;
__RW __u32 EMU_CON;
__RW __u32 EMU_MSG;
__RW __u32 EMU_ID;
__RW __u32 CMD_CON;
__RW __u32 CMD_BEG;
__RW __u32 CMD_END;
__RW __u32 CNT_RACK;
__RW __u32 CNT_RNAK;
__RW __u32 MBIST_SEL;
__RW __u32 MCFG0_CON[2];
} JL_TypeDef_q32DSP_ICU;
//---------------------------------------------//
// q32DSP dcache sfr
//---------------------------------------------//
typedef struct {
__RW __u32 CON;
__RW __u32 EMU_CON;
__RW __u32 EMU_MSG;
__RW __u32 EMU_ID;
__RW __u32 CNT_WACK;
__RW __u32 CNT_WNAK;
__RW __u32 CNT_RACK;
__RW __u32 CNT_RNAK;
__RW __u32 CMD_CON[4];
__RW __u32 CMD_BEG[4];
__RW __u32 CMD_END[4];
__RW __u32 MBIST_SEL;
__RW __u32 MCFG0_CON[2];
__RO __u32 REV1[0x20 - 0x16 - 1];
__WO __u32 CMO[32];
} JL_TypeDef_q32DSP_DCU;
#undef __RW
#undef __RO
#undef __WO
#undef __u8
#undef __u16
#undef __u32
//*********************************************************************************//
// //
// end of this module //
// //
//*********************************************************************************//
#endif
loader/ble_app_ota_update/include_lib/driver/cpu/br35/delay.h
+17
View File
@@ -0,0 +1,17 @@
#ifndef __DELAY_H__
#define __DELAY_H__
#include "typedef.h"
void udelay(u32 usec);
void mdelay(u32 msec);
void delay(volatile u32 t);
void rc_udelay(u32 usec);
void rc_mdelay(u32 msec);
#endif
loader/ble_app_ota_update/include_lib/driver/cpu/br35/gpio.h
+788
View File
@@ -0,0 +1,788 @@
/**
* @file gpio.h
* @brief
* @author @zh-jieli.com
* @version 1.0.0
* @date 2018-10-11
*/
#ifndef __GPIO_H__
#define __GPIO_H__
#include "typedef.h"
#define IO_GROUP_NUM 16
#define IO_PORTA_00 (IO_GROUP_NUM * 0 + 0)
#define IO_PORTA_01 (IO_GROUP_NUM * 0 + 1)
#define IO_PORTA_02 (IO_GROUP_NUM * 0 + 2)
#define IO_PORTA_03 (IO_GROUP_NUM * 0 + 3)
#define IO_PORTA_04 (IO_GROUP_NUM * 0 + 4)
#define IO_PORTA_05 (IO_GROUP_NUM * 0 + 5)
#define IO_PORTA_06 (IO_GROUP_NUM * 0 + 6)
#define IO_PORTA_07 (IO_GROUP_NUM * 0 + 7)
#define IO_PORTA_08 (IO_GROUP_NUM * 0 + 8)
#define IO_PORTA_09 (IO_GROUP_NUM * 0 + 9)
#define IO_PORTA_10 (IO_GROUP_NUM * 0 + 10)
#define IO_PORTA_11 (IO_GROUP_NUM * 0 + 11)
#define IO_PORTA_12 (IO_GROUP_NUM * 0 + 12)
#define IO_PORTA_13 (IO_GROUP_NUM * 0 + 13)
#define IO_PORT_PA_MASK 0x3fff
#define IO_PORTB_00 (IO_GROUP_NUM * 1 + 0)
#define IO_PORTB_01 (IO_GROUP_NUM * 1 + 1)
#define IO_PORTB_02 (IO_GROUP_NUM * 1 + 2)
#define IO_PORTB_03 (IO_GROUP_NUM * 1 + 3)
#define IO_PORTB_04 (IO_GROUP_NUM * 1 + 4)
#define IO_PORTB_05 (IO_GROUP_NUM * 1 + 5)
#define IO_PORTB_06 (IO_GROUP_NUM * 1 + 6)
#define IO_PORTB_07 (IO_GROUP_NUM * 1 + 7)
#define IO_PORTB_08 (IO_GROUP_NUM * 1 + 8)
#define IO_PORT_PB_MASK 0x01ff
#define IO_PORTC_00 (IO_GROUP_NUM * 2 + 0)
#define IO_PORTC_01 (IO_GROUP_NUM * 2 + 1)
#define IO_PORTC_02 (IO_GROUP_NUM * 2 + 2)
#define IO_PORTC_03 (IO_GROUP_NUM * 2 + 3)
#define IO_PORTC_04 (IO_GROUP_NUM * 2 + 4)
#define IO_PORTC_05 (IO_GROUP_NUM * 2 + 5)
#define IO_PORTC_06 (IO_GROUP_NUM * 2 + 6)
#define IO_PORTC_07 (IO_GROUP_NUM * 2 + 7)
#define IO_PORTC_08 (IO_GROUP_NUM * 2 + 8)
#define IO_PORTC_09 (IO_GROUP_NUM * 2 + 9)
#define IO_PORTC_10 (IO_GROUP_NUM * 2 + 10)
#define IO_PORTC_11 (IO_GROUP_NUM * 2 + 11)
#define IO_PORT_PC_MASK 0x0fff
#define IO_PORTF_00 (IO_GROUP_NUM * 3 + 0)
#define IO_PORTF_01 (IO_GROUP_NUM * 3 + 1)
#define IO_PORTF_02 (IO_GROUP_NUM * 3 + 2)
#define IO_PORTF_03 (IO_GROUP_NUM * 3 + 3)
#define IO_PORTF_04 (IO_GROUP_NUM * 3 + 4)
#define IO_PORTF_05 (IO_GROUP_NUM * 3 + 5)
#define IO_PORT_PF_MASK 0x003f
#define IO_PORTP_00 (IO_GROUP_NUM * 4 + 0)
#define IO_PORT_PP_MASK 0x0001
#define IO_PORT_LDOIN IO_PORTP_00
#define IO_MAX_NUM (IO_PORTP_00 + 1)
#define IO_PORT_DP (IO_GROUP_NUM * 5 + 0)
#define IO_PORT_DM (IO_GROUP_NUM * 5 + 1)
#define IO_PORT_USB_MASK 0x03
#define IS_PORT_USB(x) (x <= IO_PORT_DM)//无usb赋0
//br50无pr
// #define IO_PORT_PR_00 (IO_GROUP_NUM * 15 + 0)//pr固定15
// #define IO_PORT_PR_01 (IO_GROUP_NUM * 15 + 1)
// #define IO_PORT_PR_MASK 0x03
#define IO_PORT_MAX (IO_PORT_DM + 1)
#define P33_IO_OFFSET 0
#define IO_CHGFL_DET (IO_PORT_MAX + P33_IO_OFFSET + 0)
#define IO_VBGOK_DET (IO_PORT_MAX + P33_IO_OFFSET + 1)
#define IO_VBTCH_DET (IO_PORT_MAX + P33_IO_OFFSET + 2)
#define IO_LDOIN_DET (IO_PORT_MAX + P33_IO_OFFSET + 3)
#define IO_VBATDT_DET (IO_PORT_MAX + P33_IO_OFFSET + 4)
#define PG_IO_OFFSET 5
#define IO_LCD_PG (IO_PORT_MAX + PG_IO_OFFSET + 0)
#define IO_MT_PG (IO_PORT_MAX + PG_IO_OFFSET + 1)
#define IO_FS_PG2 (IO_PORT_MAX + PG_IO_OFFSET + 2)
#define GPIOA (IO_GROUP_NUM * 0)
#define GPIOB (IO_GROUP_NUM * 1)
#define GPIOC (IO_GROUP_NUM * 2)
#define GPIOF (IO_GROUP_NUM * 3)
#define GPIOP (IO_GROUP_NUM * 4)
#define GPIOUSB (IO_GROUP_NUM * 5)
// #define GPIOR (IO_GROUP_NUM * 15) //br50 no pr
#define GPIOP33 (IO_PORT_MAX + P33_IO_OFFSET)
enum {
INPUT_CH0,
INPUT_CH1,
INPUT_CH2,
INPUT_CH3,
};
enum {
LOW_POWER_FREE = 0,
LOW_POWER_KEEP = 1,
};
enum gpio_op_mode {
GPIO_SET = 1,
GPIO_AND,
GPIO_OR,
GPIO_XOR,
};
enum gpio_direction {
GPIO_OUT = 0,
GPIO_IN = 1,
};
struct gpio_reg {
volatile unsigned int in;
volatile unsigned int out;
volatile unsigned int dir;
volatile unsigned int die;
volatile unsigned int dieh;
volatile unsigned int pu0;
volatile unsigned int pu1;
volatile unsigned int pd0;
volatile unsigned int pd1;
volatile unsigned int hd0;
volatile unsigned int hd1;
volatile unsigned int spl;
volatile unsigned int con;
};
struct gpio_platform_data {
unsigned int gpio;
};
#define GPIO_PLATFORM_DATA_BEGIN(data) \
static const struct gpio_platform_data data = { \
#define GPIO_PLATFORM_DATA_END() \
};
/**
* @brief usb_iomode
*
* @param enable 1，使能；0，关闭
*/
void usb_iomode(u32 enable);
/**
* @brief gpio_direction_input
*
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
* @param dir 1，输入；0，输出
*
* @return
*/
int gpio_set_direction(u32 gpio, u32 dir);
/**
* @brief gpio_direction_input
*
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
* @param value 1，输出1, 0，输出0
*
* @return
*/
int gpio_set_output_value(u32 gpio, u32 dir);
/**
* @brief gpio_dir
*
* @param gpio [GPIOA GPIOB GPIOC GPIOD GPIOR GPIOUSB]
* @param start [0-15]，GPIOR[0-3]，GPIOUSB[0-1]
* @param len [0-15]，GPIOR[0-3]，GPIOUSB[0-1]
* @param dat 1，输入；0，输出
*
* @return
*/
u32 gpio_dir(u32 gpio, u32 start, u32 len, u32 dat, enum gpio_op_mode op);
/**
* @brief gpio_direction_output
*
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
* @param value 1，输出1；0，输出0
*
* @return
*/
int gpio_direction_output(u32 gpio, int value);
/**
* @brief gpio_out
*
* @param gpio [GPIOA GPIOB GPIOC GPIOD GPIOR GPIOUSB]
* @param start [0-15]，GPIOR[0-3]，GPIOUSB[0-1]
* @param len [0-15]，GPIOR[0-3]，GPIOUSB[0-1]
* @param dat 1，输入；0，输出
*
* @return
*/
u32 gpio_out(u32 gpio, u32 start, u32 len, u32 dat);
/**
* @brief gpio_set_pull_up
*
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
* @param value 1，上拉；0，不上拉
*
* @return
*/
int gpio_set_pull_up(u32 gpio, int value);
/**
* @brief gpio_set_pu
*
* @param gpio [GPIOA GPIOB GPIOC GPIOD GPIOR GPIOUSB]
* @param start [0-15]，GPIOR[0-3]，GPIOUSB[0-1]
* @param len [0-15]，GPIOR[0-3]，GPIOUSB[0-1]
* @param dat 1，上拉；0，不上拉
*
* @return
*/
u32 gpio_set_pu0(u32 gpio, u32 start, u32 len, u32 dat, enum gpio_op_mode op);
u32 gpio_set_pu1(u32 gpio, u32 start, u32 len, u32 dat, enum gpio_op_mode op);
/**
* @brief gpio_set_pull_down
*
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
* @param value 1，下拉；0，不下拉
*
* @return
*/
int gpio_set_pull_down(u32 gpio, int value);
/**
* @brief gpio_set_pd
*
* @param gpio [GPIOA GPIOB GPIOC GPIOD GPIOR GPIOUSB]
* @param start [0-15]，GPIOR[0-3]，GPIOUSB[0-1]
* @param len [0-15]，GPIOR[0-3]，GPIOUSB[0-1]
* @param dat 1，下拉；0，不下拉
*
* @return
*/
u32 gpio_set_pd0(u32 gpio, u32 start, u32 len, u32 dat, enum gpio_op_mode op);
u32 gpio_set_pd1(u32 gpio, u32 start, u32 len, u32 dat, enum gpio_op_mode op);
enum GPIO_HDRIVE {
GPIO_HDRIVE_2_4_MA = 0, //2.4mA
GPIO_HDRIVE_8_MA, //8mA
GPIO_HDRIVE_26_4_MA, //26.4mA
GPIO_HDRIVE_40_MA, //40mA
};
/**
* @brief gpio_set_hd
*
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
* @param value see enum GPIO_HDRIVE
*
* @return 0:ok, <0:fail
*/
int gpio_set_hd(u32 gpio, int value);
/**
* @brief gpio_set_die
*
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
* @param value 1，IO普通输入；0，IO模拟输入
*
* @return
*/
int gpio_set_die(u32 gpio, int value);
/**
* @brief gpio_set_dieh
*
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
* @param value 1，IO普通输入；0，IO模拟输入
*
* @return
*/
u32 gpio_set_dieh(u32 gpio, u32 value);
/**
* @brief gpio_die
*
* @param gpio [GPIOA GPIOB GPIOC GPIOD GPIOR GPIOUSB]
* @param start [0-15]，GPIOR[0-3]，GPIOUSB[0-1]
* @param len [0-15]，GPIOR[0-3]，GPIOUSB[0-1]
* @param dat 1，IO普通输入；0，IO模拟输入
*
* @return
*/
u32 gpio_die(u32 gpio, u32 start, u32 len, u32 dat, enum gpio_op_mode op);
/**
* @brief gpio_dieh
*
* @param gpio [GPIOA GPIOB GPIOC GPIOD GPIOR GPIOUSB]
* @param start [0-15]，GPIOR[0-3]，GPIOUSB[0-1]
* @param len [0-15]，GPIOR[0-3]，GPIOUSB[0-1]
* @param dat 1，IO普通输入；0，IO模拟输入
*
* @return
*/
u32 gpio_dieh(u32 gpio, u32 start, u32 len, u32 dat, enum gpio_op_mode op);
/**
* @brief gpio_set_output_channle
*
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
* @param clk 参考枚举CHx_UTx_TX，如CH0_UT0_TX
*
* @return
*/
u32 gpio_output_channle(u32 gpio, u32 clk);
/**
* @brief gpio_read
*
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
*
* @return
*/
int gpio_read(u32 gpio);
/**
* @brief gpio_in
*
* @param gpio [GPIOA GPIOB GPIOC GPIOD GPIOR GPIOUSB]
*
* @return
*/
u32 gpio_in(u32 gpio);
/**
* @brief gpio_write
*
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
* @param value 1，输出1；0，输出0
*
* @return
*/
u32 gpio_write(u32 gpio, u32 value);
/**
* @brief gpio_wakeup0 use IN_CHNL0_SEL
*
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
*
* @return
*/
u32 gpio_wakeup0(u32 gpio);
/**
* @brief gpio_irflt_in use IN_CHNL1_SEL
*
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
*
* @return
*/
u32 gpio_irflt_in(u32 gpio);
/**
* @brief gpio_cap_mux use IN_CHNL2_SEL
*
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
*
* @return
*/
u32 gpio_cap_mux(u32 gpio);
/**
* @brief gpio_uart_rx_input
*
* @param gpio
* @param ut
* @param ch
*
* @return
*/
u32 gpio_uart_rx_input(u32 gpio, u32 ut, u32 ch);
/**
* @brief
*
* @return
*/
u32 gpio_close_uart0(void);
/**
* @brief
*
* @return
*/
u32 gpio_close_uart1(void);
/**
* @brief
*
* @return
*/
u32 gpio_close_uart2(void);
/**
* @brief gpio_set_uart0
*
* @param ch 0:3 选择对应IO br22
* |ch|tx|rx|
* |- |- |- |
* |0|PA5_TX|PA6_RX|
* |1|PB7_TX|PB8_RX|
* |2|PA7_TX|PA8_RX|
* |3|预留|预留|
* |-1|关闭对应的IO口串口功能|no|
*
* @return
*/
u32 gpio_set_uart0(u32 ch);
/**
* @brief gpio_set_uart1
*
* @param ch 0:3 选择对应IO br22
* |ch|tx|rx|
* |- |- |- |
* |0|PB5_TX|PB6_RX|
* |1|预留|预留|
* |2|PA1_TX|PA2_RX|
* |3|USBDP |USBDM |
* |-1|关闭对应的IO口串口功能|no|
*
* @return
*/
u32 gpio_set_uart1(u32 ch);
/**
* @brief gpio_set_uart2
*
* @param ch 0:3 选择对应IO br22
* |ch|tx|rx|
* |- |- |- |
* |0|PA3_TX|PA4_RX|
* |1|预留|预留|
* |2|预留|预留|
* |3|PA9_TX|PA10_RX|
* |-1|关闭对应的IO口串口功能|no|
*
* @return
*/
u32 gpio_set_uart2(u32 ch);
enum {
IRFLT_LSB,
// IRFLT_LSB,
IRFLT_STD12M = 2,
IRFLT_STD24M,
};
enum {
IRFLT_DIV1,
IRFLT_DIV2,
IRFLT_DIV4,
IRFLT_DIV8,
IRFLT_DIV16,
IRFLT_DIV32,
IRFLT_DIV64,
IRFLT_DIV128,
IRFLT_DIV256,
IRFLT_DIV512,
IRFLT_DIV1024,
IRFLT_DIV2048,
IRFLT_DIV4096,
IRFLT_DIV8192,
IRFLT_DIV16384,
IRFLT_DIV32768,
};
/* u32 irflt_config(u32 osc, u32 div); */
/**
* @brief gpio_irflt_to_timer
*
* @param t: [0-3]
*
* @return
*/
u32 gpio_irflt_to_timer(u32 t);
u32 get_gpio(const char *p);
const char *gpio_get_name(u32 gpio);
//===================================================//
// BR50 Crossbar API
//===================================================//
enum PFI_TABLE {
PFI_GP_ICH0 = ((u32)(&(JL_IMAP->FI_GP_ICH0))),
PFI_GP_ICH1 = ((u32)(&(JL_IMAP->FI_GP_ICH1))),
PFI_GP_ICH2 = ((u32)(&(JL_IMAP->FI_GP_ICH2))),
PFI_GP_ICH3 = ((u32)(&(JL_IMAP->FI_GP_ICH3))),
PFI_GP_ICH4 = ((u32)(&(JL_IMAP->FI_GP_ICH4))),
PFI_GP_ICH5 = ((u32)(&(JL_IMAP->FI_GP_ICH5))),
PFI_SD0_CMD = ((u32)(&(JL_IMAP->FI_SD0_CMD))),
PFI_SD0_DA0 = ((u32)(&(JL_IMAP->FI_SD0_DA0))),
PFI_SD0_DA1 = ((u32)(&(JL_IMAP->FI_SD0_DA1))),
PFI_SD0_DA2 = ((u32)(&(JL_IMAP->FI_SD0_DA2))),
PFI_SD0_DA3 = ((u32)(&(JL_IMAP->FI_SD0_DA3))),
// PFI_SPI0_CLK = ((u32)(&(JL_IMAP->FI_SPI0_CLK))),
// PFI_SPI0_DA0 = ((u32)(&(JL_IMAP->FI_SPI0_DA0))),
// PFI_SPI0_DA1 = ((u32)(&(JL_IMAP->FI_SPI0_DA1))),
// PFI_SPI0_DA2 = ((u32)(&(JL_IMAP->FI_SPI0_DA2))),
// PFI_SPI0_DA3 = ((u32)(&(JL_IMAP->FI_SPI0_DA3))),
PFI_SPI1_CLK = ((u32)(&(JL_IMAP->FI_SPI1_CLK))),
PFI_SPI1_DA0 = ((u32)(&(JL_IMAP->FI_SPI1_DA0))),
PFI_SPI1_DA1 = ((u32)(&(JL_IMAP->FI_SPI1_DA1))),
PFI_SPI1_DA2 = ((u32)(&(JL_IMAP->FI_SPI1_DA2))),
PFI_SPI1_DA3 = ((u32)(&(JL_IMAP->FI_SPI1_DA3))),
PFI_SPI2_CLK = ((u32)(&(JL_IMAP->FI_SPI2_CLK))),
PFI_SPI2_DA0 = ((u32)(&(JL_IMAP->FI_SPI2_DA0))),
PFI_SPI2_DA1 = ((u32)(&(JL_IMAP->FI_SPI2_DA1))),
// PFI_SD0_DA1 = ((u32)(&(JL_IMAP->FI_SD0_DA1))),
// PFI_SD0_DA2 = ((u32)(&(JL_IMAP->FI_SD0_DA2))),
// PFI_SD0_DA3 = ((u32)(&(JL_IMAP->FI_SD0_DA3))),
PFI_IIC0_SCL = ((u32)(&(JL_IMAP->FI_IIC0_SCL))),
PFI_IIC0_SDA = ((u32)(&(JL_IMAP->FI_IIC0_SDA))),
PFI_UART0_RX = ((u32)(&(JL_IMAP->FI_UART0_RX))),
PFI_UART1_RX = ((u32)(&(JL_IMAP->FI_UART1_RX))),
// PFI_UART1_CTS = ((u32)(&(JL_IMAP->FI_UART1_CTS))),
PFI_UART2_RX = ((u32)(&(JL_IMAP->FI_UART2_RX))),
// PFI_TDM_S_WCK = ((u32)(&(JL_IMAP->FI_TDM_S_WCK))),
// PFI_TDM_S_BCK = ((u32)(&(JL_IMAP->FI_TDM_S_BCK))),
// PFI_TDM_M_DA = ((u32)(&(JL_IMAP->FI_TDM_M_DA))),
// PFI_RDEC0_DAT0 = ((u32)(&(JL_IMAP->FI_RDEC0_DAT0))),
// PFI_RDEC0_DAT1 = ((u32)(&(JL_IMAP->FI_RDEC0_DAT1))),
// PFI_RDEC1_DAT0 = ((u32)(&(JL_IMAP->FI_RDEC1_DAT0))),
// PFI_RDEC1_DAT1 = ((u32)(&(JL_IMAP->FI_RDEC1_DAT1))),
// PFI_RDEC2_DAT0 = ((u32)(&(JL_IMAP->FI_RDEC2_DAT0))),
// PFI_RDEC2_DAT1 = ((u32)(&(JL_IMAP->FI_RDEC2_DAT1))),
//PFI_ALNK0_MCLK = ((u32)(&(JL_IMAP->FI_ALNK0_MCLK))),
//PFI_ALNK0_LRCK = ((u32)(&(JL_IMAP->FI_ALNK0_LRCK))),
//PFI_ALNK0_SCLK = ((u32)(&(JL_IMAP->FI_ALNK0_SCLK))),
//PFI_ALNK0_DAT0 = ((u32)(&(JL_IMAP->FI_ALNK0_DAT0))),
//PFI_ALNK0_DAT1 = ((u32)(&(JL_IMAP->FI_ALNK0_DAT1))),
//PFI_ALNK0_DAT2 = ((u32)(&(JL_IMAP->FI_ALNK0_DAT2))),
//PFI_ALNK0_DAT3 = ((u32)(&(JL_IMAP->FI_ALNK0_DAT3))),
//PFI_SPDIF_DIA = ((u32)(&(JL_IMAP->FI_SPDIF_DIA))),
//PFI_SPDIF_DIB = ((u32)(&(JL_IMAP->FI_SPDIF_DIB))),
//PFI_SPDIF_DIC = ((u32)(&(JL_IMAP->FI_SPDIF_DIC))),
//PFI_SPDIF_DID = ((u32)(&(JL_IMAP->FI_SPDIF_DID))),
//PFI_PLNK_DAT0 = ((u32)(&(JL_IMAP->FI_PLNK_DAT0))),
//PFI_PLNK_DAT1 = ((u32)(&(JL_IMAP->FI_PLNK_DAT1))),
//PFI_CAN_RX = ((u32)(&(JL_IMAP->FI_CAN_RX))),
PFI_QDEC0_A = ((u32)(&(JL_IMAP->FI_QDEC0_A))),
PFI_QDEC0_B = ((u32)(&(JL_IMAP->FI_QDEC0_B))),
PFI_CHAIN_IN0 = ((u32)(&(JL_IMAP->FI_CHAIN_IN0))),
PFI_CHAIN_IN1 = ((u32)(&(JL_IMAP->FI_CHAIN_IN1))),
PFI_CHAIN_IN2 = ((u32)(&(JL_IMAP->FI_CHAIN_IN2))),
PFI_CHAIN_IN3 = ((u32)(&(JL_IMAP->FI_CHAIN_IN3))),
PFI_CHAIN_RST = ((u32)(&(JL_IMAP->FI_CHAIN_RST))),
PFI_TOTAl = ((u32)(&(JL_IMAP->FI_TOTAL))),
};
enum OUTPUT_CH_SIGNAL {
OUTPUT_CH_SIGNAL_TIMER0_PWM,//8
OUTPUT_CH_SIGNAL_TIMER1_PWM,
OUTPUT_CH_SIGNAL_TIMER2_PWM,
OUTPUT_CH_SIGNAL_TIMER3_PWM,
OUTPUT_CH_SIGNAL_TIMER4_PWM,
OUTPUT_CH_SIGNAL_TIMER5_PWM,
OUTPUT_CH_SIGNAL_MCPWM0_H,
OUTPUT_CH_SIGNAL_MCPWM0_L,
OUTPUT_CH_SIGNAL_MCPWM1_H,
OUTPUT_CH_SIGNAL_MCPWM1_L,
OUTPUT_CH_SIGNAL_UART1_RTS,
OUTPUT_CH_SIGNAL_CLOCK_OUT0,
OUTPUT_CH_SIGNAL_CLOCK_OUT1,//br50无clk out1
OUTPUT_CH_SIGNAL_CLOCK_OUT2,
OUTPUT_CH_SIGNAL_GP_ICH0,
OUTPUT_CH_SIGNAL_GP_ICH1,
OUTPUT_CH_SIGNAL_LEDC0_OUT = 32,
OUTPUT_CH_SIGNAL_LEDC1_OUT = 33,
};
enum INPUT_CH_TYPE {
INPUT_CH_TYPE_GP_ICH = 0,
INPUT_CH_TYPE_TIME2_PWM = 6,
INPUT_CH_TYPE_TIME3_PWM,
INPUT_CH_TYPE_MAX = 8,
};
enum INPUT_CH_SIGNAL {
//ICH_CON0
INPUT_CH_SIGNAL_TIMER0_CIN = 0,//5
INPUT_CH_SIGNAL_TIMER1_CIN,
INPUT_CH_SIGNAL_TIMER2_CIN,
INPUT_CH_SIGNAL_TIMER3_CIN,
INPUT_CH_SIGNAL_TIMER4_CIN,
INPUT_CH_SIGNAL_TIMER5_CIN,
//ICH_CON1
INPUT_CH_SIGNAL_TIMER0_CAPTURE,
INPUT_CH_SIGNAL_TIMER1_CAPTURE,
INPUT_CH_SIGNAL_TIMER2_CAPTURE,
INPUT_CH_SIGNAL_TIMER3_CAPTURE,
INPUT_CH_SIGNAL_TIMER4_CAPTURE,
INPUT_CH_SIGNAL_TIMER5_CAPTURE,
//ICH_CON2
INPUT_CH_SIGNAL_MCPWM0_CK,
INPUT_CH_SIGNAL_MCPWM1_CK,
INPUT_CH_SIGNAL_MCPWM0_FP,
INPUT_CH_SIGNAL_MCPWM1_FP,
INPUT_CH_SIGNAL_IRFLT,
INPUT_CH_SIGNAL_UART1_CTS,
//ICH_CON3
INPUT_CH_SIGNAL_QDEC_SIN0,
INPUT_CH_SIGNAL_QDEC_SIN1,
INPUT_CH_SIGNAL_WLC_EXT_ACT,
INPUT_CH_SIGNAL_CAP,
INPUT_CH_SIGNAL_CLK_PIN,
INPUT_CH_SIGNAL_EXT_CLK,
//ICH_CON4
INPUT_CH_SIGNAL_AUD_DBG_DATI,
INPUT_CH_SIGNAL_RESERVE0,
INPUT_CH_SIGNAL_RESERVE1,
INPUT_CH_SIGNAL_RESERVE2,
INPUT_CH_SIGNAL_RESERVE3,
INPUT_CH_SIGNAL_RESERVE4,
};
//=================================================================================//
//@brief: CrossBar 获取某IO的输出映射寄存器
//@input:
// gpio: 需要输出外设信号的IO口; 如IO_PORTA_00
//@return:
// 输出映射寄存器地址; 如&(JL_OMAP->PA0_OUT)
//=================================================================================//
u32 *gpio2crossbar_outreg(u32 gpio);
//=================================================================================//
//@brief: CrossBar 获取某IO的输入映射序号
//@input:
// gpio: 需要输出外设信号的IO口; 如IO_PORTA_00
//@return:
// 输出映射序号; 如PA0_IN
//=================================================================================//
u32 gpio2crossbar_inport(u32 gpio);
//=================================================================================//
//@brief: CrossBar 输出设置 API, 将指定IO口设置为某个外设的输出
//@input:
// gpio: 需要输出外设信号的IO口;
// fun_index: 需要输出到指定IO口的外设信号, 可以输出外设信号列表请查看io_omap.h文件;
// dir_ctl: IO口方向由外设控制使能, 常设为1;
// data_ctl: IO口电平状态由外设控制使能, 常设为1;
// low_power_mode: 低功耗状态是否保持io功能;
//@return:
// 1)0: 执行正确;
// 2)-EINVAL: 传参出错;
//@note: 所映射的IO需要在设置IO状态为输出配置;
//@example: 将UART0的Tx信号输出到IO_PORTA_05口:
// gpio_direction_output(IO_PORTA_05, 1); //设置IO为输出状态
// gpio_set_fun_output_port(IO_PORTA_05, FO_UART0_TX, 1, 1); //将UART0的Tx信号输出到IO_PORTA_05口
//=================================================================================//
int gpio_set_fun_output_port(u32 gpio, u32 fun_index, u8 dir_ctl, u8 data_ctl, u8 low_power_mode);
u32 gpio_get_ompap_low_power_mode(u32 offset);
//=================================================================================//
//@brief: CrossBar 输出设置 API, 将指定IO释放外设控制, 变为普通IO;
//@input:
// gpio: 需要释放外设控制IO口, 释放后变为普通IO模式;
//@return:
// 1)0: 执行正确;
// 2)-EINVAL: 传参出错;
//@note:
//@example: 将IO_PORTA_05口被某一外设控制状态释放:
// gpio_disable_fun_output_port(IO_PORTA_05);
//=================================================================================//
int gpio_disable_fun_output_port(u32 gpio);
//=================================================================================//
//@brief: CrossBar 输入设置 API, 将某个外设的输入设置为从某个IO输入
//@input:
// gpio: 需要输入外设信号的IO口;
// pfun: 需要从指定IO输入的外设信号, 可以输入的外设信号列表请查看gpio.h文件enum PFI_TABLE枚举项;
// low_power_mode: 低功耗状态是否保持io功能;
//@return:
// 1)0: 执行正确;
// 2)-EINVAL: 传参出错;
//@note: 所映射的IO需要在设置IO状态为输入配置;
//@example: 将UART0的Rx信号设置为IO_PORTA_05口输入:
// gpio_set_die(IO_PORTA_05, 1); //数字输入使能
// gpio_set_pull_up(IO_PORTA_05, 1); //上拉输入使能
// gpio_direction_input(IO_PORTA_05); //设置IO为输入状态
// gpio_set_fun_input_port(IO_PORTA_05, PFI_UART0_RX); //将UART0的Rx信号设置为IO_PORTA_05口输入
//=================================================================================//
int gpio_set_fun_input_port(u32 gpio, enum PFI_TABLE pfun, u32 low_power_mode);
u32 gpio_get_impap_low_power_mode(u32 offset);
//=================================================================================//
//@brief: CrossBar 输入设置 API, 将某个外设信号释放IO口控制, 变为普通IO;
//@input:
// pfun: 需要释放由某个IO口输入的外设信号, 外设信号列表请查看gpio.h文件enum PFI_TABLE枚举项;
//@return: 默认为0, 无出错处理;
//@note:
//@example: 将外设信号PFI_UART0_RX释放由某个IO输入:
// gpio_disable_fun_input_port(PFI_UART0_RX);
//=================================================================================//
int gpio_disable_fun_input_port(enum PFI_TABLE pfun);
//=================================================================================//
//@brief: Output Channel输出设置 API, 将指定IO口设置为某个外设的输出
//@input:
// gpio: 需要输出外设信号的IO口;
// signal: 将enum OUTPUT_CH_SIGNAL列表中需要输出到指定IO口的外设信号, 可以输出的外设信号列表请查看gpio.h文件的enum OUTPUT_CH_SIGNAL枚举项;
//@return: 默认为0, 出错内部触发ASSERT;
//@note: 所映射的IO需要在设置IO状态为输出配置;
//@example: 将OUTPUT_CH_SIGNAL_MC_PWM0_H的Tx信号输出到IO_PORTA_05口:
// gpio_direction_output(IO_PORTA_05, 1); //设置IO为输出状态
// gpio_och_sel_output_signal(IO_PORTA_05, OUTPUT_CH_SIGNAL_MC_PWM0_H); //将OUTPUT_CH_SIGNAL_MC_PWM0_H信号输出到IO_PORTA_05口
//=================================================================================//
int gpio_och_sel_output_signal(u32 gpio, enum OUTPUT_CH_SIGNAL signal);
//=================================================================================//
//@brief: Output Channel 输出设置 API, 将指定IO释放外设控制, 变为普通IO;
//@input:
// gpio: 需要释放外设控制IO口, 释放后变为普通IO模式;
// signal: 将enum OUTPUT_CH_SIGNAL列表中需要取消输出的外设信号, 外设信号列表请查看gpio.h文件的enum OUTPUT_CH_SIGNAL枚举项;;
//@return: 默认为0, 无出错处理;
//@note:
//@example: 将OUTPUT_CH_SIGNAL_MC_PWM0_H取消输出IO_PORTA_05:
// gpio_och_disable_output_signal(IO_PORTA_05, OUTPUT_CH_SIGNAL_MC_PWM0_H);
//=================================================================================//
int gpio_och_disable_output_signal(u32 gpio, enum OUTPUT_CH_SIGNAL signal);
//=================================================================================//
//@brief: Input Channel 输入设置 API, 将某个外设的输入设置为从某个IO输入
//@input:
// gpio: 需要输入外设信号的IO口;
// signal: 需要从指定IO输入的外设信号, 可以输入的外设信号列表请查看gpio.h文件enum INPUT_CH_SIGNAL枚举项;
// type: INPUT_CH 类型, 常设为INPUT_CH_TYPE_GP_ICH;
//@return: 默认为0, 出错内部触发ASSERT;
//@note: 所映射的IO需要在设置IO状态为输入配置;
//@example: 将INPUT_CH_SIGNAL_TIMER0_CIN信号设置为IO_PORTA_05口输入:
// gpio_set_die(IO_PORTA_05, 1); //数字输入使能
// gpio_set_pull_up(IO_PORTA_05, 1); //上拉输入使能
// gpio_direction_input(IO_PORTA_05); //设置IO为输入状态
// gpio_ich_sel_input_signal(IO_PORTA_05, INPUT_CH_SIGNAL_TIMER0_CIN, INPUT_CH_TYPE_GP_ICH); //将INPUT_CH_SIGNAL_TIMER0_CIN信号设置为IO_PORTA_05口输入
//=================================================================================//
int gpio_ich_sel_input_signal(u32 gpio, enum INPUT_CH_SIGNAL signal, enum INPUT_CH_TYPE type);
//=================================================================================//
//@brief: Input Channel 输入设置 API, 将某个外设信号释放IO口控制, 变为普通IO;
//@input:
// gpio: 需要取消输入外设信号的IO口;
// signal: 需要取消输入的外设信号, 外设信号列表请查看gpio.h文件enum INPUT_CH_SIGNAL枚举项;
// type: INPUT_CH 类型, 常设为INPUT_CH_TYPE_GP_ICH;
//@return: 默认为0, 无出错处理;
//@note:
//@example: 将外设信号INPUT_CH_SIGNAL_TIMER0_CIN释放由某个IO输入:
// gpio_ich_disable_input_signal(IO_PORTA_05, INPUT_CH_SIGNAL_TIMER0_CIN, INPUT_CH_TYPE_GP_ICH);
//=================================================================================//
int gpio_ich_disable_input_signal(u32 gpio, enum INPUT_CH_SIGNAL signal, enum INPUT_CH_TYPE type);
#endif /*GPIO_H*/
loader/ble_app_ota_update/include_lib/driver/cpu/br35/io_imap.h
+91
View File
@@ -0,0 +1,91 @@
//===============================================================================//
//
// input IO define
//
//===============================================================================//
#define PA0_IN 1
#define PA1_IN 2
#define PA2_IN 3
#define PA3_IN 4
#define PA4_IN 5
#define PA5_IN 6
#define PA6_IN 7
#define PA7_IN 8
#define PA8_IN 9
#define PA9_IN 10
#define PA10_IN 11
#define PA11_IN 12
#define PA12_IN 13
#define PA13_IN 14
#define PB0_IN 15
#define PB1_IN 16
#define PB2_IN 17
#define PB3_IN 18
#define PB4_IN 19
#define PB5_IN 20
#define PB6_IN 21
#define PB7_IN 22
#define PB8_IN 23
#define PC0_IN 24
#define PC1_IN 25
#define PC2_IN 26
#define PC3_IN 27
#define PC4_IN 28
#define PC5_IN 29
#define PC6_IN 30
#define PC7_IN 31
#define PC8_IN 32
#define PC9_IN 33
#define PC10_IN 34
#define PC11_IN 35
#define USBDP_IN 36
#define USBDM_IN 37
#define PP0_IN 38
//===============================================================================//
//
// function input select sfr
//
//===============================================================================//
typedef struct {
__RW __u8 FI_GP_ICH0;
__RW __u8 FI_GP_ICH1;
__RW __u8 FI_GP_ICH2;
__RW __u8 FI_GP_ICH3;
__RW __u8 FI_GP_ICH4;
__RW __u8 FI_GP_ICH5;
__RW __u8 FI_SD0_CMD;
__RW __u8 FI_SD0_DA0;
__RW __u8 FI_SD0_DA1;
__RW __u8 FI_SD0_DA2;
__RW __u8 FI_SD0_DA3;
__RW __u8 FI_SPI1_CLK;
__RW __u8 FI_SPI1_DA0;
__RW __u8 FI_SPI1_DA1;
__RW __u8 FI_SPI1_DA2;
__RW __u8 FI_SPI1_DA3;
__RW __u8 FI_SPI2_CLK;
__RW __u8 FI_SPI2_DA0;
__RW __u8 FI_SPI2_DA1;
__RW __u8 FI_SPI2_DA2;
__RW __u8 FI_SPI2_DA3;
__RW __u8 FI_IIC0_SCL;
__RW __u8 FI_IIC0_SDA;
__RW __u8 FI_UART0_RX;
__RW __u8 FI_UART1_RX;
__RW __u8 FI_UART2_RX;
__RW __u8 FI_QDEC0_A;
__RW __u8 FI_QDEC0_B;
__RW __u8 FI_CHAIN_IN0;
__RW __u8 FI_CHAIN_IN1;
__RW __u8 FI_CHAIN_IN2;
__RW __u8 FI_CHAIN_IN3;
__RW __u8 FI_CHAIN_RST;
__RW __u8 FI_TOTAL;
} JL_IMAP_TypeDef;
#define JL_IMAP_BASE (ls_base + map_adr(0x3a, 0x00))
#define JL_IMAP ((JL_IMAP_TypeDef *)JL_IMAP_BASE)
loader/ble_app_ota_update/include_lib/driver/cpu/br35/io_omap.h
+94
View File
@@ -0,0 +1,94 @@
//===============================================================================//
//
// output function define
//
//===============================================================================//
#define FO_GP_OCH0 ((0 << 2)|BIT(1))
#define FO_GP_OCH1 ((1 << 2)|BIT(1))
#define FO_GP_OCH2 ((2 << 2)|BIT(1))
#define FO_GP_OCH3 ((3 << 2)|BIT(1))
#define FO_GP_OCH4 ((4 << 2)|BIT(1))
#define FO_GP_OCH5 ((5 << 2)|BIT(1))
#define FO_GP_OCH6 ((6 << 2)|BIT(1))
#define FO_GP_OCH7 ((7 << 2)|BIT(1))
#define FO_SD0_CLK ((8 << 2)|BIT(1)|BIT(0))
#define FO_SD0_CMD ((9 << 2)|BIT(1)|BIT(0))
#define FO_SD0_DA0 ((10 << 2)|BIT(1)|BIT(0))
#define FO_SD0_DA1 ((11 << 2)|BIT(1)|BIT(0))
#define FO_SD0_DA2 ((12 << 2)|BIT(1)|BIT(0))
#define FO_SD0_DA3 ((13 << 2)|BIT(1)|BIT(0))
#define FO_SPI1_CLK ((14 << 2)|BIT(1)|BIT(0))
#define FO_SPI1_DA0 ((15 << 2)|BIT(1)|BIT(0))
#define FO_SPI1_DA1 ((16 << 2)|BIT(1)|BIT(0))
#define FO_SPI1_DA2 ((17 << 2)|BIT(1)|BIT(0))
#define FO_SPI1_DA3 ((18 << 2)|BIT(1)|BIT(0))
#define FO_SPI2_CLK ((19 << 2)|BIT(1)|BIT(0))
#define FO_SPI2_DA0 ((20 << 2)|BIT(1)|BIT(0))
#define FO_SPI2_DA1 ((21 << 2)|BIT(1)|BIT(0))
#define FO_SPI2_DA2 ((22 << 2)|BIT(1)|BIT(0))
#define FO_SPI2_DA3 ((23 << 2)|BIT(1)|BIT(0))
#define FO_IIC0_SCL ((24 << 2)|BIT(1)|BIT(0))
#define FO_IIC0_SDA ((25 << 2)|BIT(1)|BIT(0))
#define FO_UART0_TX ((26 << 2)|BIT(1)|BIT(0))
#define FO_UART1_TX ((27 << 2)|BIT(1)|BIT(0))
#define FO_UART2_TX ((28 << 2)|BIT(1)|BIT(0))
#define FO_MCPWM0_H ((29 << 2)|BIT(1)|BIT(0))
#define FO_MCPWM1_H ((30 << 2)|BIT(1)|BIT(0))
#define FO_MCPWM0_L ((31 << 2)|BIT(1)|BIT(0))
#define FO_MCPWM1_L ((32 << 2)|BIT(1)|BIT(0))
#define FO_CHAIN_OUT0 ((33 << 2)|BIT(1)|BIT(0))
#define FO_CHAIN_OUT1 ((34 << 2)|BIT(1)|BIT(0))
#define FO_CHAIN_OUT2 ((35 << 2)|BIT(1)|BIT(0))
#define FO_CHAIN_OUT3 ((36 << 2)|BIT(1)|BIT(0))
//===============================================================================//
//
// IO output select sfr
//
//===============================================================================//
typedef struct {
__RW __u8 PA0_OUT;
__RW __u8 PA1_OUT;
__RW __u8 PA2_OUT;
__RW __u8 PA3_OUT;
__RW __u8 PA4_OUT;
__RW __u8 PA5_OUT;
__RW __u8 PA6_OUT;
__RW __u8 PA7_OUT;
__RW __u8 PA8_OUT;
__RW __u8 PA9_OUT;
__RW __u8 PA10_OUT;
__RW __u8 PA11_OUT;
__RW __u8 PA12_OUT;
__RW __u8 PA13_OUT;
__RW __u8 PB0_OUT;
__RW __u8 PB1_OUT;
__RW __u8 PB2_OUT;
__RW __u8 PB3_OUT;
__RW __u8 PB4_OUT;
__RW __u8 PB5_OUT;
__RW __u8 PB6_OUT;
__RW __u8 PB7_OUT;
__RW __u8 PB8_OUT;
__RW __u8 PC0_OUT;
__RW __u8 PC1_OUT;
__RW __u8 PC2_OUT;
__RW __u8 PC3_OUT;
__RW __u8 PC4_OUT;
__RW __u8 PC5_OUT;
__RW __u8 PC6_OUT;
__RW __u8 PC7_OUT;
__RW __u8 PC8_OUT;
__RW __u8 PC9_OUT;
__RW __u8 PC10_OUT;
__RW __u8 PC11_OUT;
__RW __u8 USBDP_OUT;
__RW __u8 USBDM_OUT;
__RW __u8 PP0_OUT;
} JL_OMAP_TypeDef;
#define JL_OMAP_BASE (ls_base + map_adr(0x36, 0x00))
#define JL_OMAP ((JL_OMAP_TypeDef *)JL_OMAP_BASE)
loader/ble_app_ota_update/include_lib/driver/cpu/br35/irq.h
+190
View File
@@ -0,0 +1,190 @@
#ifndef __IRQ_H__
#define __IRQ_H__
#include "typedef.h"
//=================================================
#define IRQ_EMUEXCPT_IDX 0
#define IRQ_EXCEPTION_IDX 1
#define IRQ_SYSCALL_IDX 2
#define IRQ_TICK_TMR_IDX 3
#define IRQ_TIME0_IDX 4
#define IRQ_TIME1_IDX 5
#define IRQ_TIME2_IDX 6
#define IRQ_UART0_IDX 7
#define IRQ_UART1_IDX 8
#define IRQ_SPI1_IDX 10
#define IRQ_IIC0_IDX 11
#define IRQ_PORT_IDX 12
#define IRQ_GPADC_IDX 13
#define IRQ_UART2_IDX 14
#define IRQ_LRCT_IDX 15
#define IRQ_GPCNT0_IDX 16
#define IRQ_QDEC0_IDX 17
#define IRQ_SD0_IDX 18
#define IRQ_USB_SOF_IDX 19
#define IRQ_USB_CTRL_IDX 20
#define IRQ_TIME3_IDX 22
#define IRQ_LED_IDX 23
#define IRQ_SD0_BRK_IDX 24
#define IRQ_MCPWM_TMR_IDX 25
#define IRQ_MCPWM_CHX_IDX 26
#define IRQ_PMU_TMR0_IDX 27
#define IRQ_PMU_TMR1_IDX 28
#define IRQ_SPI2_IDX 31
#define IRQ_P33_IDX 33
#define IRQ_PINR_IDX 34
#define IRQ_PMU_SOFT0_IDX 35
#define IRQ_PMU_SOFT1_IDX 36
#define IRQ_PMU_SOFT2_IDX 37
#define IRQ_PMU_SOFT3_IDX 38
#define IRQ_PMU_TMR2_IDX 40
#define IRQ_PMU_TMR3_IDX 41
#define IRQ_SRC0_IDX 66
#define IRQ_SPI0_IDX 68
#define IRQ_DCP_IDX 70
#define IRQ_IMD_IDX 72
#define IRQ_JPG_IDX 73
#define IRQ_GPU_IDX 74
#define IRQ_ADC_IDX 88
#define IRQ_AUDIO_IDX 89
#define IRQ_BT_TIMEBASE_IDX 100
#define IRQ_BLE_RX_IDX 101
#define IRQ_BLE_EVENT_IDX 102
#define IRQ_BT_CLKN_IDX 103
#define IRQ_BREDR_IDX 104
#define IRQ_BT_RXMCH 105
#define IRQ_SYNC_IDX 106
#define IRQ_SOFT0_IDX 120
#define IRQ_SOFT1_IDX 121
#define IRQ_SOFT2_IDX 122
#define IRQ_SOFT3_IDX 123
#define IRQ_SOFT4_IDX 124
#define IRQ_SOFT5_IDX 125
#define IRQ_SOFT6_IDX 126
#define IRQ_SOFT7_IDX 127
#define MAX_IRQ_ENTRY_NUM 128
extern u32 _IRQ_MEM_ADDR[];
#define IRQ_MEM_ADDR (_IRQ_MEM_ADDR)
extern int ISR_BASE;
#define ISR_ENTRY (u32)&ISR_BASE
void interrupt_init();
//---------------------------------------------//
// interrupt cli/sti
//---------------------------------------------//
static inline int int_cli(void)
{
int msg;
asm volatile("cli %0" : "=r"(msg) :);
return msg;
}
static inline void int_sti(int msg)
{
asm volatile("sti %0" :: "r"(msg));
}
void irq_common_handler(u32 irq_idx);
void irq_set_pending(u32 irq_idx);
//---------------------------------------------//
// low power waiting
//---------------------------------------------//
__attribute__((always_inline))
static inline void lp_waiting(int *ptr, int pnd, int cpd, char inum)
{
#if 0
q32DSP(core_num())->IWKUP_NUM = inum;
while (!(*ptr & pnd)) {
asm volatile("idle");
}
*ptr |= cpd;
#else
int con;
q32DSP(core_num())->IWKUP_NUM = inum;
asm volatile(
" goto 2f \n\t"
" 1: \n\t"
" idle \n\t"
" 2: \n\t"
" %0 = [%1] \n\t"
" rep 1 { \n\t" // disable_bpu
" if((%0 & %2)==0) goto 1b \n\t"
" } \n\t"
:"=&r"(con)
:"r"(ptr), "r"(pnd), "0"(con)
:
);
*ptr = con | cpd;
#endif
}
// void irq_unmask_set(u8 index, u8 priority, u8 cpu_id);
// bool irq_read(u32 index);
void bit_clr_ie(unsigned char index);
void bit_set_ie(unsigned char index);
void request_irq(u8 index, u8 priority, void (*handler)(void), u8 cpu_id);
void unrequest_irq(u8 index);
void HWI_Install(unsigned int index, unsigned int isr, unsigned int priority);
void reg_set_ip(unsigned char index, unsigned char priority, u8 cpu_id);
void irq_init();
void irq_set_pending(u32 irq_idx);
void irq_common_handler(u32 irq_idx);
void ENABLE_INT(void);
#define enable_int ENABLE_INT
void DISABLE_INT(void);
#define disable_int DISABLE_INT
void local_irq_disable();
void local_irq_enable();
#ifdef IRQ_TIME_COUNT_EN
void irq_handler_enter(int irq);
void irq_handler_exit(int irq);
void irq_handler_times_dump();
#else
#define irq_handler_enter(irq) do { }while(0)
#define irq_handler_exit(irq) do { }while(0)
#define irq_handler_times_dump() do { }while(0)
#endif
#endif
loader/ble_app_ota_update/include_lib/driver/cpu/br35/mask_api.h
+21
View File
@@ -0,0 +1,21 @@
#ifndef __MASK_API_H__
#define __MASK_API_H__
#include "typedef.h"
#include "maskrom.h"
void exception_analyze(u32 *sp);
static void mask_api_init(void *pchar, void *exp_hook)
{
struct maskrom_argv table;
memset((void *)&table, 0, sizeof(struct maskrom_argv));
table.exp_hook = exp_hook;
table.pchar = pchar;
mask_init(&table);
}
#endif /*MASK_API_H*/
loader/ble_app_ota_update/include_lib/driver/cpu/br35/maskrom.h
+39
View File
@@ -0,0 +1,39 @@
#ifndef __MASKROM_H__
#define __MASKROM_H__
struct os_argv_table {
void *f;
void *m;
void *stack_free;
void *stack_malloc;
void *log_e;
void *enter_critical;
void *exit_critical;
void *get_ms;
void *cpu_task_sw;
int (*cpu_irq_disabled)(void);
void *jiffies_addr;
void *jiffies_unit_addr;
void *task_info_update_runtime;
struct xbuf_lock_api {
void *lock_init;
void *lock;
void *unlock;
} lock;
};
struct maskrom_argv {
void (*pchar)(char);
void (*exp_hook)(u32 *);
void (*local_irq_enable)();
void (*local_irq_disable)();
char *(*flt)(char **str, char *end, double num, int size, int precision, char fmt, int flags);
struct os_argv_table os_argv;
};
void mask_init(const struct maskrom_argv *argv);
#endif /*MASKROM_H*/
loader/ble_app_ota_update/include_lib/driver/cpu/br35/maskrom_stubs.ld
+209
View File
@@ -0,0 +1,209 @@
__local_irq_enable = ABSOLUTE(0xffd5c);
__local_irq_disable = ABSOLUTE(0xffd60);
request_irq = ABSOLUTE(0xffd64);
lp_signature_set = ABSOLUTE(0xffd68);
memcpy = ABSOLUTE(0xffd6c);
memmove = ABSOLUTE(0xffd70);
memcmp = ABSOLUTE(0xffd74);
memset = ABSOLUTE(0xffd78);
memchr = ABSOLUTE(0xffd7c);
strcmp = ABSOLUTE(0xffd80);
strcpy = ABSOLUTE(0xffd84);
strncpy = ABSOLUTE(0xffd88);
strlen = ABSOLUTE(0xffd8c);
strncmp = ABSOLUTE(0xffd90);
strstr = ABSOLUTE(0xffd94);
strchr = ABSOLUTE(0xffd98);
strrchr = ABSOLUTE(0xffd9c);
strcat = ABSOLUTE(0xffda0);
__divdi3 = ABSOLUTE(0xffda4);
__umoddi3 = ABSOLUTE(0xffda8);
__muldi3 = ABSOLUTE(0xffdac);
__udivdi3 = ABSOLUTE(0xffdb0);
__udivmoddi4 = ABSOLUTE(0xffdb4);
ic_pll_init = ABSOLUTE(0xffdb8);
sfc_suspend = ABSOLUTE(0xffdbc);
sfc_resume = ABSOLUTE(0xffdc0);
sfc_drop_cache = ABSOLUTE(0xffdc4);
sfc_boot = ABSOLUTE(0xffdc8);
sfc_entry_continue_mode = ABSOLUTE(0xffdcc);
ota_jump_mode = ABSOLUTE(0xffdd0);
DcuInitial = ABSOLUTE(0xffdd4);
DcuFlushinvAll = ABSOLUTE(0xffdd8);
DcuWaitIdle = ABSOLUTE(0xffddc);
IcuInitial = ABSOLUTE(0xffde0);
IcuFlushinvAll = ABSOLUTE(0xffde4);
IcuWaitIdle = ABSOLUTE(0xffde8);
DcuEnable = ABSOLUTE(0xffdec);
DcuFlushRegion = ABSOLUTE(0xffdf0);
chip_crc16 = ABSOLUTE(0xffdf4);
CrcDecode = ABSOLUTE(0xffdf8);
mask_init = ABSOLUTE(0xffdfc);
wdt_clear = ABSOLUTE(0xffe00);
nvram_set_boot_state = ABSOLUTE(0xffe04);
chip_reset = ABSOLUTE(0xffe08);
flash_poweron = ABSOLUTE(0xffe0c);
flash_poweron_base = ABSOLUTE(0xffe10);
flash_poweroff = ABSOLUTE(0xffe14);
flash_poweroff_base = ABSOLUTE(0xffe18);
spi_io_mount = ABSOLUTE(0xffe1c);
spi_io_unmount = ABSOLUTE(0xffe20);
get_sfc_read_mode = ABSOLUTE(0xffe24);
spi_port_io_init = ABSOLUTE(0xffe28);
spi_port_io_uninit = ABSOLUTE(0xffe2c);
usb_slave_mode = ABSOLUTE(0xffe30);
uart_set_dma_dir = ABSOLUTE(0xffe34);
doe = ABSOLUTE(0xffe38);
LZ4_setStreamDecode = ABSOLUTE(0xffe3c);
LZ4_decompress_safe_continue = ABSOLUTE(0xffe40);
LZ4_decompress_generic = ABSOLUTE(0xffe44);
LZ4_decompress_safe_usingDict = ABSOLUTE(0xffe48);
dec_isd_cfg_ini = ABSOLUTE(0xffe4c);
rom_nand_flash_get_features = ABSOLUTE(0xffe50);
rom_nand_flash_set_features = ABSOLUTE(0xffe54);
pcTaskName = ABSOLUTE(0xffe58);
uxTaskStack = ABSOLUTE(0xffe5c);
uxTaskStackDepth = ABSOLUTE(0xffe60);
OSCtxSw2 = ABSOLUTE(0xffe64);
OSCtxSw = ABSOLUTE(0xffe68);
os_init = ABSOLUTE(0xffe6c);
os_current_task_prio = ABSOLUTE(0xffe70);
os_current_task_stask_size = ABSOLUTE(0xffe74);
os_time_get = ABSOLUTE(0xffe78);
os_task_create_static = ABSOLUTE(0xffe7c);
os_task_coreaffinityset = ABSOLUTE(0xffe80);
os_task_create_affinity_core = ABSOLUTE(0xffe84);
os_task_create = ABSOLUTE(0xffe88);
os_time_dly = ABSOLUTE(0xffe8c);
os_task_del_req = ABSOLUTE(0xffe90);
os_task_del_res = ABSOLUTE(0xffe94);
os_task_del = ABSOLUTE(0xffe98);
os_taskq_post = ABSOLUTE(0xffe9c);
os_taskq_accept = ABSOLUTE(0xffea0);
__os_taskq_pend = ABSOLUTE(0xffea4);
os_sem_create = ABSOLUTE(0xffea8);
os_sem_del = ABSOLUTE(0xffeac);
os_sem_pend = ABSOLUTE(0xffeb0);
os_sem_post = ABSOLUTE(0xffeb4);
os_sem_set = ABSOLUTE(0xffeb8);
os_sem_query = ABSOLUTE(0xffebc);
os_sem_valid = ABSOLUTE(0xffec0);
os_mutex_create = ABSOLUTE(0xffec4);
os_mutex_del = ABSOLUTE(0xffec8);
os_mutex_pend = ABSOLUTE(0xffecc);
os_mutex_post = ABSOLUTE(0xffed0);
os_mutex_valid = ABSOLUTE(0xffed4);
os_q_create = ABSOLUTE(0xffed8);
os_q_del = ABSOLUTE(0xffedc);
os_q_flush = ABSOLUTE(0xffee0);
os_taskq_flush = ABSOLUTE(0xffee4);
os_q_pend = ABSOLUTE(0xffee8);
os_q_recv = ABSOLUTE(0xffeec);
os_q_peek = ABSOLUTE(0xffef0);
os_q_post = ABSOLUTE(0xffef4);
os_q_post_to_back = ABSOLUTE(0xffef8);
os_q_post_to_front = ABSOLUTE(0xffefc);
os_q_query = ABSOLUTE(0xfff00);
os_q_valid = ABSOLUTE(0xfff04);
os_task_get_handle = ABSOLUTE(0xfff08);
OSInit = ABSOLUTE(0xfff0c);
OSSchedLock = ABSOLUTE(0xfff10);
OSSchedUnlock = ABSOLUTE(0xfff14);
OSIdleOtherCore = ABSOLUTE(0xfff18);
OSResumOtherCore = ABSOLUTE(0xfff1c);
os_time_tick = ABSOLUTE(0xfff20);
OS_SchedRoundRobin = ABSOLUTE(0xfff24);
OS_EventTaskRdy = ABSOLUTE(0xfff28);
OS_EventTaskWait = ABSOLUTE(0xfff2c);
OS_EventTO = ABSOLUTE(0xfff30);
OS_Sched = ABSOLUTE(0xfff34);
OSUpdateIdleTime = ABSOLUTE(0xfff38);
prvGetExpectedIdleTime = ABSOLUTE(0xfff3c);
os_taskq_post_msg = ABSOLUTE(0xfff40);
os_taskq_post_event = ABSOLUTE(0xfff44);
os_taskq_post_type = ABSOLUTE(0xfff48);
task_queue_post_event = ABSOLUTE(0xfff4c);
task_queue_post_msg = ABSOLUTE(0xfff50);
task_queue_post = ABSOLUTE(0xfff54);
OSTaskQFlush = ABSOLUTE(0xfff58);
__OSTaskQFlushMsg = ABSOLUTE(0xfff5c);
os_taskq_pend = ABSOLUTE(0xfff60);
os_taskq_pend_timeout = ABSOLUTE(0xfff64);
os_current_task_rom = ABSOLUTE(0xfff68);
OSTimeDly = ABSOLUTE(0xfff6c);
OSTimeDlyResume = ABSOLUTE(0xfff70);
OSTimeGet = ABSOLUTE(0xfff74);
OSTimeSet = ABSOLUTE(0xfff78);
OSTCBCur = ABSOLUTE(0x100328);
OSRunning = ABSOLUTE(0x100320);
OSRdyTbl = ABSOLUTE(0x10031c);
OSIdleCtr = ABSOLUTE(0x100318);
OSTCBHighRdy = ABSOLUTE(0x100324);
OSTCBPrioTbl = ABSOLUTE(0x10032c);
idle_tcb = ABSOLUTE(0x100430);
OSLockNesting = ABSOLUTE(0x100314);
OSNextTaskUnblockTime = ABSOLUTE(0x10042c);
cpu1_run_flag = ABSOLUTE(0x10048c);
OS_Affinity_Enable = ABSOLUTE(0x1002d2);
MASK_CONFIG_CPU_UNMASK_IRQ_ENABLE = ABSOLUTE(0x1002d0);
OS_Sw_Sf_Irq_Num = ABSOLUTE(0x1002d1);
OSTaskCreate = ABSOLUTE(0xfff7c);
os_taskq_del_type = ABSOLUTE(0xfff80);
pmalloc_init = ABSOLUTE(0xfff84);
pmalloc = ABSOLUTE(0xfff88);
pfree = ABSOLUTE(0xfff8c);
pmalloc_get_unused_pages = ABSOLUTE(0xfff90);
get_physic_address = ABSOLUTE(0xfff94);
pmalloc_get_hdl = ABSOLUTE(0xfff98);
vmm_init_ = ABSOLUTE(0xfff9c);
vmalloc_ = ABSOLUTE(0xfffa0);
vfree_ = ABSOLUTE(0xfffa4);
vmem_get_phy_adr = ABSOLUTE(0xfffa8);
vmem_start = ABSOLUTE(0xfffac);
vmem_end = ABSOLUTE(0xfffb0);
vmalloc_get_hdl = ABSOLUTE(0xfffb4);
vmalloc_v2 = ABSOLUTE(0xfffb8);
vfree_v2 = ABSOLUTE(0xfffbc);
vcopy_ = ABSOLUTE(0xfffc0);
lock_vir_mem = ABSOLUTE(0xfffc4);
unlock_vir_mem = ABSOLUTE(0xfffc8);
hw_mmu_disable = ABSOLUTE(0xfffcc);
get_sbc_frame_info = ABSOLUTE(0xfffd0);
get_sbc_dec_ops = ABSOLUTE(0xfffd4);
sbc_dec_loop_u = ABSOLUTE(0xfffd8);
sbc_unpack_frame_u = ABSOLUTE(0xfffdc);
sbc_synthesize_audio_u = ABSOLUTE(0xfffe0);
sbc_oput_deal_normal = ABSOLUTE(0xfffe4);
sbc_oput_deal_To_ch2 = ABSOLUTE(0xfffe8);
sbc_bit_offset4 = ABSOLUTE(0xf88c0);
sbc_bit_offset8 = ABSOLUTE(0xf8900);
sbc_proto4_m0 = ABSOLUTE(0xf8980);
sbc_proto4_m1 = ABSOLUTE(0xf89d0);
sbc_proto8_m0 = ABSOLUTE(0xf8a20);
sbc_proto8_m1 = ABSOLUTE(0xf8ac0);
syn_matrix4 = ABSOLUTE(0xf8b60);
syn_matrix8 = ABSOLUTE(0xf8be0);
crc8_table = ABSOLUTE(0xf87c0);
sbc_div_new_table = ABSOLUTE(0xf8de0);
need_fix_iir_filter_buf = ABSOLUTE(0xfffec);
fix_iir_filter_init = ABSOLUTE(0xffff0);
fix_iir_filter_update = ABSOLUTE(0xffff4);
fix_iir_filter_run = ABSOLUTE(0xffff8);
fix_iir_filter_clear_mem = ABSOLUTE(0xffffc);
_SFC_MEMORY_START_ADDR = ABSOLUTE(0xc000000);
_IRQ_MEM_ADDR = ABSOLUTE(0x100000);
_RAM_LIMIT_L = ABSOLUTE(0x100000);
_RAM_LIMIT_H = ABSOLUTE(0x137000);
_MASK_USED_MEM_END = ABSOLUTE(0x101310);
_MASK_EXPORT_MEM_BEGIN = ABSOLUTE(0x100200);
_MASK_EXPORT_MEM_SIZE = ABSOLUTE(0x34c);
_UBOOT_LOADER_RAM_START = ABSOLUTE(0x102600);
_UBOOT_LOADER_RAM_END = ABSOLUTE(0x137000);
_UBOOT_LOADER_RAM_SIZE = ABSOLUTE(0x34a00);
g_boot_soft_flag = ABSOLUTE(0x100204);
irq_lock_cnt = ABSOLUTE(0x1002b8);
efuse_page0 = ABSOLUTE(0x1002ac);
efuse_page1 = ABSOLUTE(0x1002b0);
efuse_page2 = ABSOLUTE(0x1002b4);
nvram_list = ABSOLUTE(0x100214);
/* exception_irq_handler = ABSOLUTE(0xf8004); */
loader/ble_app_ota_update/include_lib/driver/cpu/br35/power/p33.h
+67
View File
@@ -0,0 +1,67 @@
#ifndef __P33_H__
#define __P33_H__
#include "typedef.h"
#include "p33_sfr.h"
#include "p33_app.h"
//
//
// lvd
//
//
//
/****************************************************************/
typedef enum {
LVD_RESET_MODE, //复位模式
LVD_EXCEPTION_MODE, //异常模式，进入异常中断
LVD_WAKEUP_MODE, //唤醒模式，进入唤醒中断，callback参数为回调函数
} LVD_MODE;
typedef enum {
VLVD_SEL_166V = 0,
VLVD_SEL_177V,
VLVD_SEL_188V,
VLVD_SEL_199V,
VLVD_SEL_210V,
VLVD_SEL_221V,
VLVD_SEL_232V,
VLVD_SEL_243V,
VLVD_SEL_254V,
VLVD_SEL_265V,
VLVD_SEL_276V,
VLVD_SEL_287V,
VLVD_SEL_298V,
VLVD_SEL_309V,
VLVD_SEL_320V,
VLVD_SEL_331V,
} LVD_VOL;
void lvd_config(LVD_VOL vol, u8 expin_en, LVD_MODE mode, void (*callback));
void reset_pin_open(void);
void reset_pin_close(void);
void reset_pin_init(u32 pin, u32 level, u32 time);
void reset_pin1_init(u32 pin, u32 level, u32 time);
void chip_reset();
void set_vddio_level(u8 level);
void set_dvdd_leve(u8 level);
void set_dcvdd_leve(u8 level);
void p33_soft_reset(void);
void latch_reset(void);
#endif
loader/ble_app_ota_update/include_lib/driver/cpu/br35/power/p33_app.h
+825
View File
@@ -0,0 +1,825 @@
#ifndef __P33_APP_H__
#define __P33_APP_H__
#include "typedef.h"
#include "p33_sfr.h"
//=============================================================//
// P33 SFR //
//=============================================================//
//ROM
u8 p33_buf(u8 buf);
#define p33_xor_1byte(addr, data0) (*((volatile u8 *)&addr + 0x300*4) = data0); asm volatile ("csync")
//#define p33_xor_1byte(addr, data0) (*((volatile u8 *)&addr + 0x300*4) = data0)
// #define p33_xor_1byte(addr, data0) addr ^= (data0)
#define p33_or_1byte(addr, data0) (*((volatile u8 *)&addr + 0x200*4) = data0); asm volatile ("csync")
//#define p33_or_1byte(addr, data0) (*((volatile u8 *)&addr + 0x200*4) = data0)
// #define p33_or_1byte(addr, data0) addr |= (data0)
#define p33_and_1byte(addr, data0) (*((volatile u8 *)&addr + 0x100*4) = (data0)); asm volatile ("csync")
//#define p33_and_1byte(addr, data0) (*((volatile u8 *)&addr + 0x100*4) = (data0))
//#define p33_and_1byte(addr, data0) addr &= (data0)
// void p33_tx_1byte(u16 addr, u8 data0);
#define p33_tx_1byte(addr, data0) addr = data0
// u8 p33_rx_1byte(u16 addr);
#define p33_rx_1byte(addr) addr
#define P33_CON_SET(sfr, start, len, data) (sfr = (sfr & ~((~(0xffffffff << (len))) << (start))) | \
(((data) & (~(0xffffffff << (len)))) << (start)))
#define P33_CON_GET(sfr) (sfr)
#if 1
#define p33_fast_access(reg, data, en) \
{ \
if (en) { \
p33_or_1byte(reg, (data)); \
} else { \
p33_and_1byte(reg, ~(data)); \
} \
}
#else
#define p33_fast_access(reg, data, en) \
{ \
if (en) { \
reg |= (data); \
} else { \
reg &= ~(data); \
} \
}
#endif
//
//
// for p33_analog
//
//
//
/************************P3_PSW_CON0*****************************/
#define DVD2SVD_SHORT_EN(en) p33_fast_access(P3_PSW_CON0, BIT(6), en)
#define SVD2RVD2_SHORT_EN(en) p33_fast_access(P3_PSW_CON0, BIT(5), en)
#define SVD2RVD_SHORT_EN(en) p33_fast_access(P3_PSW_CON0, BIT(4), en)
#define RVDD2_CAP_EN(en) p33_fast_access(P3_PSW_CON0, BIT(3), en)
#define RVD2_EN(en) p33_fast_access(P3_PSW_CON0, BIT(2), en)
#define RVDD_CAP_EN(en) p33_fast_access(P3_PSW_CON0, BIT(1), en)
#define RVD_EN(en) p33_fast_access(P3_PSW_CON0, BIT(0), en)
#define NVD2IO_SHORT_EN(en) p33_fast_access(P3_PSW_CON1, BIT(7), en)
#define DVDD2_IFULL_EN(en) p33_fast_access(P3_PSW_CON1, BIT(6), en)
#define DVDD2_BYPASS_EN(en) p33_fast_access(P3_PSW_CON1, BIT(5), en)
#define DVDD2_EN(en) p33_fast_access(P3_PSW_CON1, BIT(4), en)
#define RVDD2_BYPASS_EN(en) p33_fast_access(P3_PSW_CON1, BIT(3), en)
#define RVDD_BYPASS_EN(en) p33_fast_access(P3_PSW_CON1, BIT(2), en)
#define WVD2SVD_SHORT_EN(en) p33_fast_access(P3_PSW_CON1, BIT(1), en)
#define WVDD_EN(en) p33_fast_access(P3_PSW_CON1, BIT(0), en)
#define WVDD_PDOWN_ENTER() P33_CON_SET(P3_PSW_CON1, 0, 2, 0x03); P33_CON_SET(P3_PSW_CON0, 4, 3, 0x7)
#define WVDD_POFF_ENTER() P33_CON_SET(P3_PSW_CON1, 0, 2, 0x03); P33_CON_SET(P3_PSW_CON0, 4, 3, 0x1)
#define WVDD_PDOWN_POFF_EXIT() P33_CON_SET(P3_PSW_CON0, 4, 3, 0x07); P33_CON_SET(P3_PSW_CON1, 1, 1, 0x00)
/************************P3_PSW_CON2*****************************/
//SS: soft start of VPQS
#define VQPS_SS_EN(en) p33_fast_access(P3_PSW_CON2, BIT(1), en)
#define VQPS_EN(en) p33_fast_access(P3_PSW_CON2, BIT(0), en)
/************************P3_ANA_CON*****************************/
//#define EVDD_IFULL_EN(en) p33_fast_access(P3_ANA_CON, BIT(0), en)
//DS: decrease undershoot and overshoot
//#define DVD_DS_EN(en) p33_fast_access(P3_ANA_CON, BIT(1), en)
//#define RVD_DS_EN(en) p33_fast_access(P3_ANA_CON, BIT(2), en)
/************************P3_PMU_ADC0*****************************/
enum {
VBG_TEST_SEL_WBG04,
VBG_TEST_SEL_MBG04,
VBG_TEST_SEL_MBG08,
VBG_TEST_SEL_LVDBG,
};
#define VBG_TEST_SEL(sel) P33_CON_SET(P3_PMU_ADC0, 4, 2, sel)
#define VBG_TEST_EN(en) p33_fast_access(P3_PMU_ADC0, BIT(3), en)
#define VBG_BUFFER_EN(en) p33_fast_access(P3_PMU_ADC0, BIT(2), en)
#define PMU_TOADC_OE(en) p33_fast_access(P3_PMU_ADC0, BIT(1), en)
#define PMU_TOADC_EN(en) p33_fast_access(P3_PMU_ADC0, BIT(0), en)
/************************P3_PMU_ADC1*****************************/
#define ADC_CHANNEL_SEL(ch) P33_CON_SET(P3_PMU_ADC1, 0, 4, ch)
/************************P3_VBG_CON0*****************************/
#define MVBG_SEL(sel) P33_CON_SET(P3_VBG_CON0, 0, 4, sel)
#define WVBG_SEL(sel) P33_CON_SET(P3_VBG_CON0, 4, 4, sel)
/************************P3_IOV_CON0*****************************/
#define VDDIOW_VOL_SEL(lev) P33_CON_SET(P3_IOV_CON0, 4, 4, lev)
#define GET_VDDIOW_VOL_SEL() (P33_CON_GET(P3_IOV_CON0)>>4 & 0xf)
//vddiom_lev
#define VDDIOM_VOL_SEL(lev) P33_CON_SET(P3_IOV_CON0, 0, 4, lev)
#define GET_VDDIOM_VOL_SEL() (P33_CON_GET(P3_IOV_CON0) & 0xf)
/************************P3_IOV_CON1*****************************/
#define VDDIO_HD_SEL(hd) P33_CON_SET(P3_IOV_CON1, 0, 2, hd)
/************************P3_DCV_CON0*****************************/
#define DCVD_DEOVSHOT_EN(en) p33_fast_access(P3_DCV_CON0, BIT(7), en)
#define DCVD_CAP_EN(en) p33_fast_access(P3_DCV_CON0, BIT(6), en)
#define DCVD_HD_SEL(sel) P33_CON_SET(P3_DCV_CON0, 4, 2, sel)
#define DCVDD_DEFAULT_VOL DCVDD_VOL_SEL_120V
#define GET_DCVDD_VOL_SEL() (P33_CON_GET(P3_DCV_CON0) & 0xf)
#define DCVDD_VOL_SEL(sel) P33_CON_SET(P3_DCV_CON0, 0, 4, sel)
/*******************************************************************/
/*
*-------------------P3_DCV_CON0
*/
enum {
DCVDD_VOL_SEL_100V = 0,
DCVDD_VOL_SEL_1025V,
DCVDD_VOL_SEL_105V,
DCVDD_VOL_SEL_1075V,
DCVDD_VOL_SEL_110V,
DCVDD_VOL_SEL_1125V,
DCVDD_VOL_SEL_115V,
DCVDD_VOL_SEL_1175V,
DCVDD_VOL_SEL_120V,
DCVDD_VOL_SEL_1225V,
DCVDD_VOL_SEL_125V,
DCVDD_VOL_SEL_1275V,
DCVDD_VOL_SEL_130V,
DCVDD_VOL_SEL_1325V,
DCVDD_VOL_SEL_135V,
DCVDD_VOL_SEL_1375V,
};
#define DCVD_SEL(sel) P3_DCV_CON0 = (P3_DCV_CON0 & (~0xf)) | sel
#define DCVDD_DEFAULT_VOL DCVDD_VOL_SEL_120V
/************************P3_DCD_CON0*****************************/
enum {
BTDCDC_OSC_SEL0520KHz = 0,
BTDCDC_OSC_SEL0762KHz,
BTDCDC_OSC_SEL0997KHz,
BTDCDC_OSC_SEL1220KHz,
BTDCDC_OSC_SEL1640KHz,
BTDCDC_OSC_SEL1840KHz,
BTDCDC_OSC_SEL2040KHz,
BTDCDC_OSC_SEL2220MHz,
};
#define BTDCDC_OSC_SEL(sel) P33_CON_SET(P3_DCD_CON0, 5, 3, sel)
#define BTDCDC_DUTY_SEL(sel) P33_CON_SET(P3_DCD_CON0, 3, 2, sel)
#define BTDCDC_V17_TEST_OE(en) p33_fast_access(P3_DCD_CON0, BIT(2), en);
#define BTDCDC_RAMP_SHORT(en) p33_fast_access(P3_DCD_CON0, BIT(1), en)
#define BTDCDC_PFM_MODE(en) p33_fast_access(P3_DCD_CON0, BIT(0), en)
#define GET_BTDCDC_PFM_MODE() (P33_CON_GET(P3_DCD_CON0) & BIT(0) ? 1 : 0)
/************************P3_DCD_CON1*****************************/
#define BTDCDC_COMP_HD(sel) P33_CON_SET(P3_DCD_CON1, 6, 2, sel)
#define BTDCDC_ISENSE_HD(sel) P33_CON_SET(P3_DCD_CON1, 4, 2, sel)
#define BTDCDC_DT_S(sel) P33_CON_SET(P3_DCD_CON1, 2, 2, sel)
#define BTDCDC_V21_RES_S(sel) P33_CON_SET(P3_DCD_CON1, 0, 2, sel)
/************************P3_DCD_CON2*****************************/
#define BTDCDC_PMOS_S(sel) P33_CON_SET(P3_DCD_CON2, 5, 3, sel)
#define BTDCDC_NMOS_S(sel) P33_CON_SET(P3_DCD_CON2, 1, 3, sel)
/************************P3_DCD_CON3*****************************/
#define BTDCDC_OSC_TEST_OE(en) p33_fast_access(P3_DCD_CON3, BIT(7), en)
#define BTDCDC_HD_BIAS_SEL(sel) P33_CON_SET(P3_DCD_CON3, 5, 2, sel)
#define BTDCDC_CLK_SEL(sel) p33_fast_access(P3_DCD_CON3, BIT(4), sel)
#define GET_BTDCDC_CLK_SEL() ((P33_CON_GET(P3_DCD_CON3) & BIT(4) ? 1 : 0))
#define BTDCDC_ZCD_RES(sel) P33_CON_SET(P3_DCD_CON3, 2, 2, sel)
#define BTDCDC_ZCD_EN(en) p33_fast_access(P3_DCD_CON3, BIT(0), en)
/************************P3_DCD_CON4*****************************/
#define BTDCDC_VHH_SEL(sel) P33_CON_SET(P3_DCD_CON4, 4, 3, sel)
#define BTDCDC_PFM_HYS_SEL(sel) P33_CON_SET(P3_DCD_CON4, 0, 2, sel)
/*******************************************************************/
/*
*-------------------P3_DVD_CON0
*/
enum {
DVDD_VOL_SEL_0725V = 0,
DVDD_VOL_SEL_075V,
DVDD_VOL_SEL_0775V,
DVDD_VOL_SEL_080V,
DVDD_VOL_SEL_0825V,
DVDD_VOL_SEL_0850V,
DVDD_VOL_SEL_0875V,
DVDD_VOL_SEL_090V,
DVDD_VOL_SEL_0925V,
DVDD_VOL_SEL_0950V,
DVDD_VOL_SEL_0975V,
DVDD_VOL_SEL_100V,
DVDD_VOL_SEL_1025V,
DVDD_VOL_SEL_105V,
DVDD_VOL_SEL_1075V,
DVDD_VOL_SEL_110V,
};
/************************P3_DVD_CON0*****************************/
#define DVDD_DEFAULT_VOL DVDD_VOL_SEL_090V
#define DVDD_VOL_SEL(sel) P33_CON_SET(P3_DVD_CON0, 0, 4, sel)
#define GET_DVDD_VOL_SEL() (P33_CON_GET(P3_DVD_CON0) & 0xf)
#define DVDD_HD_SEL(sel) P33_CON_SET(P3_DVD_CON0, 4, 2, sel)
#define DVDD_CAP_EN(en) p33_fast_access(P3_DVD_CON0, BIT(6), en)
/*******************************************************************/
/*
*-------------------P3_RVD_CON0
*/
enum {
RVDD_VOL_SEL_0725V = 0,
RVDD_VOL_SEL_075V,
RVDD_VOL_SEL_0775V,
RVDD_VOL_SEL_080V,
RVDD_VOL_SEL_0825V,
RVDD_VOL_SEL_0850V,
RVDD_VOL_SEL_0875V,
RVDD_VOL_SEL_090V,
RVDD_VOL_SEL_0925V,
RVDD_VOL_SEL_0950V,
RVDD_VOL_SEL_0975V,
RVDD_VOL_SEL_100V,
RVDD_VOL_SEL_1025V,
RVDD_VOL_SEL_105V,
RVDD_VOL_SEL_1075V,
RVDD_VOL_SEL_110V,
};
#define RVDD_VOL_SEL(sel) P33_CON_SET(P3_RVD_CON0, 0, 4, sel)
#define RVDD_DEFAULT_VOL RVDD_VOL_SEL_090V
#define GET_RVDD_VOL_SEL() (P33_CON_GET(P3_RVD_CON0) & 0xf)
#define RVDD_HD_SEL(en) P33_CON_SET(P3_RVD_CON0, 4, 2, en)
/************************P3_RVD_CON1*****************************/
#define RVDD_CMP_EN(en) p33_fast_access(P3_RVD_CON1, BIT(4), en)
#define PVDD_DCDC_LEV_SEL(sel) P33_CON_SET(P3_RVD_CON1, 0, 4, sel)
#define GET_PVDD_DCDC_LEV_SEL() (P33_CON_GET(P3_RVD_CON1) & 0xf)
/************************P3_WVD_CON0*****************************/
#define WVDD_LOAD_EN(en) p33_fast_access(P3_WVD_CON0, BIT(4), en)
#define WVDD_VOL_SEL(sel) P33_CON_SET(P3_WVD_CON0, 0, 4, sel)
/************************P3_PVD_CON0*****************************/
#define PVD_DEUDSHT_EN(en) p33_fast_access(P3_PVD_CON0, BIT(3), en)
#define GET_PVD_DEUDST_EN() ((P33_CON_GET(P3_PVD_CON0) & BIT(3)) ? 1:0)
#define PVDD_HD_SEL(sel) P33_CON_SET(P3_PVD_CON0, 0, 3, sel)
#define GET_PVDD_HD_SEL() (P33_CON_GET(P3_PVD_CON0) & 0x7)
/************************P3_EVD_CON0*****************************/
enum {
EVD_VOL_SEL_100V = 0,
EVD_VOL_SEL_105V,
EVD_VOL_SEL_110V,
EVD_VOL_SEL_115V,
};
#define EVD_CAP_EN(en) p33_fast_access(P3_EVD_CON0, BIT(4), en)
#define EVD_HD_SEL(sel) P33_CON_SET(P3_EVD_CON0, 2, 2, sel)
#define EVD_VOL_SEL(sel) P33_CON_SET(P3_EVD_CON0, 0, 2, sel)
#define RVD_DEUDSHT_EN(en) p33_fast_access(P3_ANA_MFIX, BIT(2), en)
#define DVD_DEUDSHT_EN(en) p33_fast_access(P3_ANA_MFIX, BIT(1), en)
#define EVD_ILMT_EN(en) p33_fast_access(P3_ANA_MFIX, BIT(0), en)
/************************P3_CHG_CON0*****************************/
#define LRC_Hz_DEFAULT (200 * 1000L)
#define LRC_CON0_INIT \
/* */ (0 << 7) |\
/* */ (0 << 6) |\
/*RC32K_RPPS_S1_33v */ (1 << 5) |\
/*RC32K_RPPS_S0_33v */ (1 << 4) |\
/* */ (0 << 3) |\
/* */ (0 << 2) |\
/*RC32K_RN_TRIM_33v */ (1 << 1) |\
/*RC32K_EN_33v */ (1 << 0)
#define LRC_CON1_INIT \
/* */ (0 << 7) |\
/*RC32K_CAP_S2_33v */ (0 << 6) |\
/*RC32K_CAP_S1_33v */ (1 << 5) |\
/*RC32K_CAP_S0_33v */ (1 << 4) |\
/* 2bit */ (0 << 2) |\
/*RC32K_RNPS_S1_33v */ (1 << 1) |\
/*RC32K_RNPS_S0_33v */ (0 << 0)
/************************P3_LRC_CON0*****************************/
#define LRC32K_RPPS_SEL(sel) P33_CON_SET(P3_LRC_CON0, 4, 2, sel)
#define LRC32K_RN_TRIM(en) p33_fast_access(P3_LRC_CON0, BIT(1), en)
#define LRC_EN(en) p33_fast_access(P3_LRC_CON0, BIT(0), en);\
p33_fast_access(P3_LRC_CON0, BIT(1), en)
/************************P3_LRC_CON1*****************************/
#define LRC32K_CAP_SEL(sel) P33_CON_SET(P3_LRC_CON1, 4, 3, sel)
#define LRC32K_PNPS_SEL(sel) P33_CON_SET(P3_LRC_CON1, 0, 2, sel)
#define CLOSE_LRC() p33_tx_1byte(P3_LRC_CON0, 0);\
p33_tx_1byte(P3_LRC_CON1, 0)
/*******************************************************************/
/************************P3_VLVD_CON0*****************************/
#define VLVD_PND() ((P33_CON_GET(P3_VLVD_CON0) & BIT(7)) ? 1 : 0)
#define VLVD_PND_CLR() p33_fast_access(P3_VLVD_CON0, BIT(6), 1)
#define P33_VLVD_PS(en) p33_fast_access(P3_VLVD_CON0, BIT(2), en)
#define P33_VLVD_OE(en) p33_fast_access(P3_VLVD_CON0, BIT(1), en)
#define P33_VLVD_EN(en) p33_fast_access(P3_VLVD_CON0, BIT(0), en)
#define GET_P33_VLVD_EN() ((P33_CON_GET(P3_VLVD_CON0) & BIT(0)) ? 1:0)
/************************P3_VLVD_FLT*****************************/
#define VLVD_FLT(sel) P33_CON_SET(P3_VLVD_FLT, 0, 2, sel);
/************************P3_RST_CON0*****************************/
#define PVDDOK_OE(en) p33_fast_access(P3_RST_CON0, BIT(7), en)
#define DVDDOK2_OE(en) p33_fast_access(P3_RST_CON0, BIT(6), en)
#define DVDDOK_OE(en) p33_fast_access(P3_RST_CON0, BIT(5), en)
#define PPOR_MASK(en) p33_fast_access(P3_RST_CON0, BIT(4), en)
#define DPOR2_MASK(en) p33_fast_access(P3_RST_CON0, BIT(3), en)
#define DPOR_MASK(en) p33_fast_access(P3_RST_CON0, BIT(2), en)
#define P11_TO_P33_RST_MASK(en) p33_fast_access(P3_RST_CON0, BIT(1), en)
#define FAST_PU_SYS(en) p33_fast_access(P3_RST_CON0, BIT(0), en)
/************************P3_RST_CON1*****************************/
#define IS_VCM_DET_EN() ((P33_CON_GET(P3_RST_CON1) & BIT(0)) ? 1: 0 )
#define DVD2_DRST_MASK(en) p33_fast_access(P3_RST_CON1, BIT(5), en)
#define DVD_DRST_MASK(en) p33_fast_access(P3_RST_CON1, BIT(4), en)
#define VLVD_WKUP_EN(en) p33_fast_access(P3_RST_CON1, BIT(3), en)
#define VLVD_RST_EN(en) p33_fast_access(P3_RST_CON1, BIT(2), en)
#define VLVD_EXPT_EN(en) p33_fast_access(P3_RST_CON1, BIT(1), en)
#define VCM_DET_EN(en) p33_fast_access(P3_RST_CON1, BIT(0), en)
/************************P3_CLK_CON0*****************************/
#define RC_250K_EN(a) p33_fast_access(P3_CLK_CON0, BIT(0), a)
/************************P3_VLD_KEEP*****************************/
#define RTC_WKUP_KEEP(a) p33_fast_access(P3_VLD_KEEP, BIT(1), a)
#define P33_WKUP_P11_EN(a) p33_fast_access(P3_VLD_KEEP, BIT(2), a)
//
//
// for pmu flow
//
//
//
/************************P3_P11_CPU*****************************/
#define P11_CPU_BRANCH_POWEROFF(en) p33_fast_access(P3_P11_CPU, BIT(1), en)
#define P11_CPU_RELEASE(en) p33_fast_access(P3_P11_CPU, BIT(0), en)
/************************P3_LP_CTL*****************************/
//控制p11的低功耗
#define LP_FLOW_EN(en) p33_fast_access(P3_LP_CTL, BIT(0), en)
#define LP_FLOW_CPND() p33_fast_access(P3_LP_CTL, BIT(6), 1)
#define POWER_ON_END() ((P33_CON_GET(P3_LP_CTL) & BIT(5)) ? 1: 0 )
#define MBG_EN_EN(a) \
if (a) { \
p33_or_1byte(P3_ANA_FLOW0, BIT(7)); \
} else { \
p33_and_1byte(P3_ANA_FLOW0, ~BIT(7)); \
}
/************************P3_ANA_FLOW0*****************************/
#define DVD_EN(en) p33_fast_access(P3_ANA_FLOW0, BIT(0), en)
#define DCVD_TO_DIG_EN(en) p33_fast_access(P3_ANA_FLOW0, BIT(0)|BIT(1), en)
#define DCVD_LDO_EN(en) p33_fast_access(P3_ANA_FLOW0, BIT(2), en)
#define PAVD_LDO_EN(en) p33_fast_access(P3_ANA_FLOW0, BIT(3), en)
#define GET_DCVD_STA() ((P33_CON_GET(P3_ANA_FLOW0) & (BIT(2))) ? 1:0)
#define GET_PAVD_LDO_EN() ((P33_CON_GET(P3_ANA_FLOW0) & BIT(3)) ? 1:0)
#define PVDD_EN(en) p33_fast_access(P3_ANA_FLOW0, BIT(4), en)
#define MVIO_VBAT_EN(en) p33_fast_access(P3_ANA_FLOW0, BIT(5), en)
#define MVIO_VPWR_EN(en) p33_fast_access(P3_ANA_FLOW0, BIT(6), en)
#define PW_GATE_EN(en) p33_fast_access(P3_ANA_FLOW0, BIT(5)|BIT(6), en)
#define MBG_EN(en) p33_fast_access(P3_ANA_FLOW0, BIT(7), en)
#define MVIO_PVDD_MVBG_ONLY() p33_tx_1byte(P3_ANA_FLOW0, BIT(4) | BIT(5) | BIT(6) | BIT(7))
#define PVDD_MVBG_ONLY() p33_tx_1byte(P3_ANA_FLOW0, BIT(4) | BIT(7))
#define PVDD_ONLY() p33_tx_1byte(P3_ANA_FLOW0, BIT(4))
/************************P3_ANA_FLOW1*****************************/
#define MIOV_VLMT_EN(en) p33_fast_access(P3_ANA_FLOW1, BIT(4), en)
#define MIOV_IFULL_EN(en) p33_fast_access(P3_ANA_FLOW1, BIT(3), en)
#define PAVD_IFULL_EN(en) p33_fast_access(P3_ANA_FLOW1, BIT(2), en)
#define DCVD_IFULL_EN(en) p33_fast_access(P3_ANA_FLOW1, BIT(1), en)
#define DVD_IFULL_EN(en) p33_fast_access(P3_ANA_FLOW1, BIT(0), en)
/************************P3_ANA_FLOW2*****************************/
#define NVD2PVD_WSHORT_EN(en) p33_fast_access(P3_ANA_FLOW2, BIT(1), en)
#define NVD2PVD_SHORT_EN(en) p33_fast_access(P3_ANA_FLOW2, BIT(0), en)
/************************P3_NVRAM_PWR*****************************/
#define NVRAM_PWR_MODE(sel) P33_CON_SET(P3_NVRAM_PWR, 4, 2, sel)
/************************P3_PVDD0_AUTO*****************************/
#define PVDD_AUTO_PRD(sel) P33_CON_SET(P3_PVDD0_AUTO, 5, 3, sel);
#define PVDD_LEVEL_AUTO(en) p33_fast_access(P3_PVDD0_AUTO, BIT(4), en);
#define PVDD_LEVEL_LOW(sel) P33_CON_SET(P3_PVDD0_AUTO, 0, 4, sel);
/************************P3_PVDD1_AUTO*****************************/
#define PVDD_LEVEL_HIGH_NOW(sel) p33_tx_1byte(P3_PVDD1_AUTO, (sel<<4)|sel);
#define PVDD_LEVEL_HIGH(sel) P33_CON_SET(P3_PVDD1_AUTO, 4, 4, sel)
#define PVDD_LEVEL_NOW(sel) P33_CON_SET(P3_PVDD1_AUTO, 0, 4, sel)
#define GET_PVDD_LEVEL_NOW() (P33_CON_GET(P3_PVDD1_AUTO) & 0x0f)
//
//
// for ANA_control
//
//
/////
/*******************************************************************/
/************************P3_LS_XX*****************************/
enum PWR_LAT {
DVDDLS_LAT,
PVDDLS_LAT,
};
#define DVDDLS_OR_BIT(a) \
p33_or_1byte(P3_LS_IO_USR , BIT(a)); \
p33_or_1byte(P3_LS_IO_ROM , BIT(a));
#define SHALS_OR_BIT(a) \
p33_or_1byte(P3_LS_IO_SHA , BIT(a)); \
p33_or_1byte(P3_LS_IO_PINR , BIT(a));
#define PVDDLS_OR_BIT(a) \
p33_or_1byte(P3_LS_CTMU , BIT(a)); \
p33_or_1byte(P3_LS_P11 , BIT(a));
#define DVDDLS_AND_NBIT(a) \
p33_and_1byte(P3_LS_IO_USR , (u8)~BIT(a)); \
p33_and_1byte(P3_LS_IO_ROM , (u8)~BIT(a));
#define SHALS_AND_NBIT(a) \
p33_and_1byte(P3_LS_IO_SHA , (u8)~BIT(a)); \
p33_and_1byte(P3_LS_IO_PINR , (u8)~BIT(a));
#define PVDDLS_AND_NBIT(a) \
p33_and_1byte(P3_LS_CTMU , (u8)~BIT(a)); \
p33_and_1byte(P3_LS_P11 , (u8)~BIT(a));
#define DVDDLS_TX_BYTE(a) \
p33_tx_1byte(P3_LS_IO_USR , a); \
p33_tx_1byte(P3_LS_IO_ROM , a);
#define SHALS_TX_BYTE(a) \
p33_tx_1byte(P3_LS_IO_SHA , a); \
p33_tx_1byte(P3_LS_IO_PINR , a);
#define PVDDLS_TX_BYTE(a) \
p33_tx_1byte(P3_LS_CTMU , a); \
p33_tx_1byte(P3_LS_P11 , a);
#define DVDDLS_ANA_NBIT(a) \
p33_and_1byte(P3_LS_IO_USR , ~BIT(a)); \
p33_and_1byte(P3_LS_IO_ROM , ~BIT(a)); \
p33_and_1byte(P3_LS_IO_SHA , ~BIT(a)); \
p33_and_1byte(P3_LS_CTMU , ~BIT(a)); \
#define SHALS_ANA_NBIT(a) \
p33_and_1byte(P3_LS_IO_SHA , (u8)~BIT(a)); \
p33_and_1byte(P3_LS_CTMU , (u8)~BIT(a)); \
#define PVDDLS_ANA_NBIT(a) \
p33_and_1byte(P3_LS_P11 , ~BIT(a));
//
//
// for reset_source
//
//
//
/************************P3_PR_PWR*****************************/
#define P3_SOFT_RESET() P33_CON_SET(P3_PR_PWR, 4, 1, 1)
/************************P3_IVS_CLR*****************************/
#define PWVLD(a) \
if (a) { \
p33_tx_1byte(P3_IVS_SET, BIT(7)); \
} else { \
p33_tx_1byte(P3_IVS_CLR, BIT(7)); \
}
#define P33_SF_KICK_START() P33_CON_SET(P3_IVS_CLR, 0, 8, 0b00101010)
#define PWR_BY_SOFTWARE(a) \
if (a) { \
p33_or_1byte(P3_RST_CON1, BIT(6)); \
p33_tx_1byte(P3_ANA_KEEP0, 0xff); \
p33_tx_1byte(P3_ANA_KEEP1, 0xff); \
PWVLD(0); \
} else { \
PWVLD(1); \
p33_and_1byte(P3_RST_CON1, ~BIT(6)); \
}
/************************P3_RST_SRC*****************************/
#define GET_P33_SYS_RST_SRC() P33_CON_GET(P3_RST_SRC)
/************************P3_RST_FLAG*****************************/
#define GET_P33_SYS_POWER_FLAG() ((P33_CON_GET(P3_RST_FLAG) & BIT(3)) ? 1 : 0)
#define GET_P33_SYS_RST_LEVEL2() ((P33_CON_GET(P3_RST_FLAG) & BIT(3)) ? 1 : 0)
#define GET_P33_SYS_RST_LEVEL1() ((P33_CON_GET(P3_RST_FLAG) & BIT(5)) ? 1 : 0)
#define GET_P33_SYS_RST_LEVEL0() ((P33_CON_GET(P3_RST_FLAG) & BIT(7)) ? 1 : 0)
#define P33_LV2_RST_FLAG_CLR() (p33_fast_access(P3_RST_FLAG, BIT(2), 1))
#define P33_LV1_RST_FLAG_CLR() (p33_fast_access(P3_RST_FLAG, BIT(4), 1))
#define P33_LV0_RST_FLAG_CLR() (p33_fast_access(P3_RST_FLAG, BIT(6), 1))
//-----special operation----------
#define P33_WKUP_ENABLE() \
p33_or_1byte(P3_VLD_KEEP , BIT(2))
#define P33_WKUP_DISABLE() \
p33_and_1byte(P3_VLD_KEEP , ~BIT(2))
#define P33_IE_ENABLE() \
bit_set_ie(IRQ_P33_IDX)
#define P33_IE_DISABLE() \
bit_clr_ie(IRQ_P33_IDX)
#define IS_CHARGE_EN_NOW() (P3_CHG_CON0 & BIT(0))
/*
*-------------------P3_ANA_FLOW0
*/
#define DCVDD_EN(a) \
if (a) { \
p33_or_1byte(P3_ANA_FLOW0, BIT(2)); \
} else { \
p33_and_1byte(P3_ANA_FLOW0, ~BIT(2)); \
}
#define DCDC13_EN(a) \
if (a) { \
p33_or_1byte(P3_ANA_FLOW0, BIT(3)); \
} else { \
p33_and_1byte(P3_ANA_FLOW0, ~BIT(3)); \
}
#define IS_DCDC13_EN() ((P3_ANA_FLOW0 & BIT(3)) ? 1: 0 )
/*
*-------------------P3_ANA_FLOW1
*/
#define IOVD_IFULL_EN(a) \
if (a) { \
p33_or_1byte(P3_ANA_FLOW1, (BIT(0) | BIT(1))); \
} else { \
p33_and_1byte(P3_ANA_FLOW1, ~(BIT(0) | BIT(1))); \
}
#define IOVD_VLMT_EN(a) \
if (a) { \
p33_or_1byte(P3_ANA_FLOW1, (BIT(2) | BIT(3))); \
} else { \
p33_and_1byte(P3_ANA_FLOW1, ~(BIT(2) | BIT(3))); \
}
#define DVD_POR_EN(a) \
if (a) { \
p33_or_1byte(P3_ANA_FLOW1, BIT(6)); \
} else { \
p33_and_1byte(P3_ANA_FLOW1, ~BIT(6)); \
}
#define PVD_POR_EN(a) \
if (a) { \
p33_or_1byte(P3_ANA_FLOW1, BIT(7)); \
} else { \
p33_and_1byte(P3_ANA_FLOW1, ~BIT(7)); \
}
/*******************************************************************/
/*******************************************************************/
/*
*-------------------P3_VLVD_CON1
*/
#define VLVD_SEL(a) P3_VLVD_CON1 = (P3_VLVD_CON1 & (~0xf)) | a
//macro for VLVD_SEL
enum {
VLVD_sel_16V = 0,
VLVD_sel_17V,
VLVD_sel_18V,
VLVD_sel_19V,
VLVD_sel_20V,
VLVD_sel_21V,
VLVD_sel_22V,
VLVD_sel_23V,
VLVD_sel_24V,
VLVD_sel_25V,
VLVD_sel_26V,
VLVD_sel_27V,
VLVD_sel_28V,
VLVD_sel_29V,
VLVD_sel_30V,
VLVD_sel_31V,
};
/*******************************************************************/
/*******************************************************************/
/*
*-------------------P3_IOV_CON0
*/
//vddiom_lev
enum {
VDDIOM_VOL_21V = 0,
VDDIOM_VOL_22V,
VDDIOM_VOL_23V,
VDDIOM_VOL_24V,
VDDIOM_VOL_25V,
VDDIOM_VOL_26V,
VDDIOM_VOL_27V,
VDDIOM_VOL_28V,
VDDIOM_VOL_29V,
VDDIOM_VOL_30V,
VDDIOM_VOL_31V,
VDDIOM_VOL_32V,
VDDIOM_VOL_33V,
VDDIOM_VOL_34V,
VDDIOM_VOL_35V,
VDDIOM_VOL_36V,
};
#define GET_MVIO_SEL() (P3_IOV_CON0 & 0xf)
#define MVIO_SEL(a) P3_IOV_CON0 = (P3_IOV_CON0 & (~0xf)) | a
/*
* *-------------------P3_RST_FLAG
* */
#define P33_SYS_POWERUP_CLEAR() p33_or_1byte(P3_RST_FLAG, BIT(2)|BIT(4)|BIT(6))
//need 1mS to recorver
//P3_ANA_KEEP0 = 0; \
//P3_ANA_KEEP1 = 0;
//while(POWER_ON_END());
//P3_ANA_KEEP0 = 0; \
//P3_ANA_KEEP1 = 0;
#endif
loader/ble_app_ota_update/include_lib/driver/cpu/br35/power/p33_sfr.h
+340
View File
@@ -0,0 +1,340 @@
#ifndef __P33_SFR_H__
#define __P33_SFR_H__
#include "typedef.h"
#ifdef PMU_SYSTEM
#define P33_ACCESS(x) (*(volatile u32 *)(0xc000 + x*4))
#else
#define P33_ACCESS(x) (*(volatile u32 *)(0xf20000 + 0xc000 + x*4))
#endif
#ifdef PMU_SYSTEM
#define RTC_ACCESS(x) (*(volatile u32 *)(0xd000 + x*4))
#else
#define RTC_ACCESS(x) (*(volatile u32 *)(0xf20000 + 0xd000 + x*4))
#endif
//===========
//===============================================================================//
//
//
//
//===============================================================================//
//............. 0x0000 - 0x000f............
//#define P3_VLMT_CON P33_ACCESS(0x01)
//#define P3_POR_CON P33_ACCESS(0x02)
#define P3_VLVD_CON0 P33_ACCESS(0x03)
#define P3_VLVD_CON1 P33_ACCESS(0x04)
#define P3_VLVD_FLT P33_ACCESS(0x05)
#define P3_WDT_CON P33_ACCESS(0x06)
#define P3_OCP_CON0 P33_ACCESS(0x07)
#define P3_ANA_FLOW0 P33_ACCESS(0x08)
#define P3_ANA_FLOW1 P33_ACCESS(0x09)
#define P3_ANA_FLOW2 P33_ACCESS(0x0a)
#define P3_ANA_KEEP0 P33_ACCESS(0x0c)
#define P3_ANA_KEEP1 P33_ACCESS(0x0d)
#define P3_ANA_KEEP2 P33_ACCESS(0x0e)
//............. 0X0010 - 0X001F.........for analog others
#define P3_OSL_CON P33_ACCESS(0x10)
#define P3_RST_FLAG P33_ACCESS(0x11)
#define P3_VBAT_TYPE P33_ACCESS(0x12)
#define P3_LRC_CON0 P33_ACCESS(0x13)
#define P3_LRC_CON1 P33_ACCESS(0x14)
#define P3_RST_CON0 P33_ACCESS(0x15)
#define P3_RST_CON1 P33_ACCESS(0x16)
#define P3_RST_CON2 P33_ACCESS(0x17)
#define P3_VLD_KEEP P33_ACCESS(0x18)
#define P3_CLK_CON0 P33_ACCESS(0x19)
#define P3_ANA_READ P33_ACCESS(0x1a)
#define P3_CHG_CON0 P33_ACCESS(0x1b)
#define P3_CHG_CON1 P33_ACCESS(0x1c)
#define P3_CHG_CON2 P33_ACCESS(0x1d)
#define P3_CHG_CON3 P33_ACCESS(0x1e)
#define P3_CHG_CON4 P33_ACCESS(0x1f)
//............. 0X0020 - 0X002F............ for buck circuit
//#define P3_BUCK1_CON0 P33_ACCESS(0x20)
//#define P3_BUCK1_CON1 P33_ACCESS(0x21)
//#define P3_BUCK1_CON2 P33_ACCESS(0x22)
//#define P3_BUCK1_CON3 P33_ACCESS(0x23)
//#define P3_BUCK1_CON4 P33_ACCESS(0x24)
//#define P3_BUCK1_CON5 P33_ACCESS(0x25)
//#define P3_BUCK1_CON6 P33_ACCESS(0x26)
//#define P3_BUCK1_CON7 P33_ACCESS(0x27)
#define P3_BUCK2_CON0 P33_ACCESS(0x20)
#define P3_BUCK2_CON1 P33_ACCESS(0x21)
#define P3_BUCK2_CON2 P33_ACCESS(0x22)
#define P3_BUCK2_CON3 P33_ACCESS(0x23)
#define P3_BUCK2_CON4 P33_ACCESS(0x24)
#define P3_BUCK2_CON5 P33_ACCESS(0x25)
#define P3_BUCK2_CON6 P33_ACCESS(0x26)
#define P3_BUCK2_CON7 P33_ACCESS(0x27)
//#define P3_BUCK3_CON0 P33_ACCESS(0x28)
//#define P3_BUCK3_CON1 P33_ACCESS(0x29)
//#define P3_BUCK3_CON2 P33_ACCESS(0x2a)
//#define P3_BUCK3_CON3 P33_ACCESS(0x2b)
//#define P3_BUCK3_CON4 P33_ACCESS(0x2c)
//#define P3_BUCK3_CON5 P33_ACCESS(0x2d)
//#define P3_BUCK3_CON6 P33_ACCESS(0x2e)
//#define P3_BUCK3_CON7 P33_ACCESS(0x2f)
//............. 0X0030 - 0X003F............ for PMU manager
#define P3_SFLAG0 P33_ACCESS(0x30)
#define P3_SFLAG1 P33_ACCESS(0x31)
#define P3_SFLAG2 P33_ACCESS(0x32)
#define P3_SFLAG3 P33_ACCESS(0x33)
#define P3_SFLAG4 P33_ACCESS(0x34)
#define P3_SFLAG5 P33_ACCESS(0x35)
#define P3_SFLAG6 P33_ACCESS(0x36)
#define P3_SFLAG7 P33_ACCESS(0x37)
#define P3_SFLAG8 P33_ACCESS(0x38)
#define P3_SFLAG9 P33_ACCESS(0x39)
#define P3_SFLAGA P33_ACCESS(0x3a)
#define P3_SFLAGB P33_ACCESS(0x3b)
//............. 0X0040 - 0X004F............ for
#define P3_IVS_RD P33_ACCESS(0x40)
#define P3_IVS_SET P33_ACCESS(0x41)
#define P3_IVS_CLR P33_ACCESS(0x42)
#define P3_PVDD0_AUTO P33_ACCESS(0x43)
#define P3_PVDD1_AUTO P33_ACCESS(0x44)
#define P3_WKUP_DLY P33_ACCESS(0x45)
#define P3_PCNT_FLT P33_ACCESS(0x48)
#define P3_PCNT_CON P33_ACCESS(0x49)
#define P3_PCNT_SET0 P33_ACCESS(0x4a)
#define P3_PCNT_SET1 P33_ACCESS(0x4b)
#define P3_PCNT_DAT0 P33_ACCESS(0x4c)
#define P3_PCNT_DAT1 P33_ACCESS(0x4d)
#define P3_P11_CPU P33_ACCESS(0x4f)
//............. 0X0050 - 0X005F............ for port wake up
#define P3_WKUP_FLT_EN0 P33_ACCESS(0x50)
#define P3_WKUP_P_IE0 P33_ACCESS(0x51)
#define P3_WKUP_N_IE0 P33_ACCESS(0x52)
#define P3_WKUP_LEVEL0 P33_ACCESS(0x53)
#define P3_WKUP_P_CPND0 P33_ACCESS(0x54)
#define P3_WKUP_N_CPND0 P33_ACCESS(0x55)
#define P3_WKUP_P_PND0 P33_ACCESS(0x56)
#define P3_WKUP_N_PND0 P33_ACCESS(0x57)
#define P3_WKUP_FLT_EN1 P33_ACCESS(0x58)
#define P3_WKUP_P_IE1 P33_ACCESS(0x59)
#define P3_WKUP_N_IE1 P33_ACCESS(0x5a)
#define P3_WKUP_LEVEL1 P33_ACCESS(0x5b)
#define P3_WKUP_P_CPND1 P33_ACCESS(0x5c)
#define P3_WKUP_N_CPND1 P33_ACCESS(0x5d)
#define P3_WKUP_P_PND1 P33_ACCESS(0x5e)
#define P3_WKUP_N_PND1 P33_ACCESS(0x5f)
//............. 0X0060 - 0X006F............ for analog wake up
#define P3_AWKUP_FLT_EN P33_ACCESS(0x60)
#define P3_AWKUP_P_IE P33_ACCESS(0x61)
#define P3_AWKUP_N_IE P33_ACCESS(0x62)
#define P3_AWKUP_LEVEL P33_ACCESS(0x63)
#define P3_AWKUP_P_PND P33_ACCESS(0x64)
#define P3_AWKUP_N_PND P33_ACCESS(0x65)
#define P3_AWKUP_P_CPND P33_ACCESS(0x66)
#define P3_AWKUP_N_CPND P33_ACCESS(0x67)
#define P3_WKUP_CLK_SEL P33_ACCESS(0x68)
#define P3_AWKUP_CLK_SEL P33_ACCESS(0x69)
#define P3_SYS_PWR0 P33_ACCESS(0x6a)
#define P3_SYS_PWR1 P33_ACCESS(0x6b)
#define P3_SYS_PWR2 P33_ACCESS(0x6c)
#define P3_SYS_PWR3 P33_ACCESS(0x6d)
#define P3_SYS_PWR4 P33_ACCESS(0x6e)
#define P3_SYS_PWR5 P33_ACCESS(0x6f)
//............. 0X0070 - 0X007F............ for
#define P3_PGDR_CON0 P33_ACCESS(0x70)
#define P3_PGDR_CON1 P33_ACCESS(0x71)
#define P3_PGSD_CON P33_ACCESS(0x72)
#define P3_LP_CTL P33_ACCESS(0x74)
#define P3_LP_CFG P33_ACCESS(0x75)
#define P3_NVRAM_PWR P33_ACCESS(0x76)
#define P3_WVD_CON0 P33_ACCESS(0x77)
#define P3_PVD_CON0 P33_ACCESS(0x78)
#define P3_EVD_CON0 P33_ACCESS(0x79)
#define P3_PMU_CON0 P33_ACCESS(0x7a)
#define P3_PMU_CON4 P33_ACCESS(0x7e)
#define P3_PMU_CON5 P33_ACCESS(0x7f)
//............. 0X0080 - 0X008F............ for
#define P3_PINR_CON P33_ACCESS(0x80)
#define P3_PINR_CON1 P33_ACCESS(0x81)
#define P3_PINR_SAFE P33_ACCESS(0x82)
#define P3_PINR_SAFE1 P33_ACCESS(0x83)
#define P3_PINR_PND1 P33_ACCESS(0x84)
#define P3_RST_SRC0 P33_ACCESS(0x8e)
#define P3_RST_SRC1 P33_ACCESS(0x8f)
//............. 0X0090 - 0X009F............ for
#define P3_PSW_CON0 P33_ACCESS(0x90)
#define P3_PSW_CON1 P33_ACCESS(0x91)
#define P3_PSW_CON2 P33_ACCESS(0x92)
#define P3_PMU_ADC0 P33_ACCESS(0x93)
#define P3_PMU_ADC1 P33_ACCESS(0x94)
#define P3_VBG_CON0 P33_ACCESS(0x95)
#define P3_VBG_CON1 P33_ACCESS(0x96)
#define P3_IOV_CON0 P33_ACCESS(0x97)
#define P3_IOV_CON1 P33_ACCESS(0x98)
#define P3_PAVD_CON0 P33_ACCESS(0x99)
#define P3_DCV_CON0 P33_ACCESS(0x9a)
#define P3_DVD_CON0 P33_ACCESS(0x9b)
#define P3_DVD2_CON0 P33_ACCESS(0x9c)
#define P3_RVD_CON0 P33_ACCESS(0x9d)
#define P3_RVD_CON1 P33_ACCESS(0x9e)
#define P3_RVD2_CON0 P33_ACCESS(0x9f)
//............. 0X00A0 - 0X00AF............
#define P3_PR_PWR P33_ACCESS(0xa0)
#define P3_VPWR_CON0 P33_ACCESS(0xa1)
#define P3_VPWR_CON1 P33_ACCESS(0xa2)
#define P3_RTC_ADC0 P33_ACCESS(0xa3)
#define P3_LS_P11 P33_ACCESS(0xa4)
#define P3_LS_EN P33_ACCESS(0xa5)
#define P3_EXT_EFUSE_CON P33_ACCESS(0xa6)
#define P3_WKUP_SRC P33_ACCESS(0xa8)
#define P3_ANA_MFIX P33_ACCESS(0xa9)
#define P3_DBG_CON0 P33_ACCESS(0xaa)
#define P3_DBG_CON1 P33_ACCESS(0xab)
#define P3_MFIX_OPT P33_ACCESS(0xac)
//............. 0X00B0 - 0X00BF............ for EFUSE
#define P3_EFUSE_CON0 P33_ACCESS(0xb0)
#define P3_EFUSE_CON1 P33_ACCESS(0xb1)
#define P3_EFUSE_CON2 P33_ACCESS(0xb2)
#define P3_EFUSE_RDAT P33_ACCESS(0xb3)
#define P3_EFUSE_PU_DAT0 P33_ACCESS(0xb4)
#define P3_EFUSE_PU_DAT1 P33_ACCESS(0xb5)
#define P3_EFUSE_PU_DAT2 P33_ACCESS(0xb6)
#define P3_EFUSE_PU_DAT3 P33_ACCESS(0xb7)
#define P3_FUNC_EN P33_ACCESS(0xb8)
#define P3_FUNC_CTL0 P33_ACCESS(0xb9)
#define P3_FUNC_CTL1 P33_ACCESS(0xba)
#define P3_FUNC_CTL2 P33_ACCESS(0xbb)
#define P3_EFUSE_ANA0 P33_ACCESS(0xbc)
//............. 0X00C0 - 0X00CF............ for port input select
#define P3_PORT_SEL0 P33_ACCESS(0xc0)
#define P3_PORT_SEL1 P33_ACCESS(0xc1)
#define P3_PORT_SEL2 P33_ACCESS(0xc2)
#define P3_PORT_SEL3 P33_ACCESS(0xc3)
#define P3_PORT_SEL4 P33_ACCESS(0xc4)
#define P3_PORT_SEL5 P33_ACCESS(0xc5)
#define P3_PORT_SEL6 P33_ACCESS(0xc6)
#define P3_PORT_SEL7 P33_ACCESS(0xc7)
//............. 0x00d0 - 0x00df............
#define P3_LS_IO_USR P33_ACCESS(0xd0) //TODO: check sync with verilog head file chip_def.v LEVEL_SHIFTER
#define P3_LS_IO_ROM P33_ACCESS(0xd1)
#define P3_LS_IO_PINR P33_ACCESS(0xd2)
#define P3_LS_CTMU P33_ACCESS(0xd3)
#define P3_LS_IO_SHA P33_ACCESS(0xd4)
#define P3_LS_LRC24M P33_ACCESS(0xd5)
#define P3_LS_BT P33_ACCESS(0xd6)
#define P3_LS_PLL P33_ACCESS(0xd7)
//............. 0X00E0 - 0X00FF............ for p33 lp timer
#define P3_LP_RSC00 P33_ACCESS(0xe0)
#define P3_LP_RSC01 P33_ACCESS(0xe1)
#define P3_LP_RSC02 P33_ACCESS(0xe2)
#define P3_LP_RSC03 P33_ACCESS(0xe3)
#define P3_LP_PRD00 P33_ACCESS(0xe4)
#define P3_LP_PRD01 P33_ACCESS(0xe5)
#define P3_LP_PRD02 P33_ACCESS(0xe6)
#define P3_LP_PRD03 P33_ACCESS(0xe7)
#define P3_LP_RSC10 P33_ACCESS(0xe8)
#define P3_LP_RSC11 P33_ACCESS(0xe9)
#define P3_LP_RSC12 P33_ACCESS(0xea)
#define P3_LP_RSC13 P33_ACCESS(0xeb)
#define P3_LP_RSC14 P33_ACCESS(0xec)
#define P3_LP_RSC15 P33_ACCESS(0xed)
#define P3_LP_PRD10 P33_ACCESS(0xee)
#define P3_LP_PRD11 P33_ACCESS(0xef)
#define P3_LP_PRD12 P33_ACCESS(0xf0)
#define P3_LP_PRD13 P33_ACCESS(0xf1)
#define P3_LP_PRD14 P33_ACCESS(0xf2)
#define P3_LP_PRD15 P33_ACCESS(0xf3)
#define P3_LP_TMR0_CLK P33_ACCESS(0xf4)
#define P3_LP_TMR1_CLK P33_ACCESS(0xf5)
#define P3_LP_TMR0_CON P33_ACCESS(0xf6)
#define P3_LP_TMR1_CON P33_ACCESS(0xf7)
#define P3_LP_TMR_CFG P33_ACCESS(0xf8)
#define P3_LP_CNTRD0 P33_ACCESS(0xf9)
#define P3_LP_CNT0 P33_ACCESS(0xfa)
#define P3_LP_CNT1 P33_ACCESS(0xfb)
#define P3_LP_CNT2 P33_ACCESS(0xfc)
#define P3_LP_CNT3 P33_ACCESS(0xfd)
#define P3_LP_CNT4 P33_ACCESS(0xfe)
#define P3_LP_CNT5 P33_ACCESS(0xff)
//===============================================================================//
//
// P33 RTCVDD
//
//===============================================================================//
//............. 0X0080 - 0X008F............ for RTC
#define R3_ALM_CON RTC_ACCESS(0x80)
#define R3_RTC_CON0 RTC_ACCESS(0x84)
#define R3_RTC_CON1 RTC_ACCESS(0x85)
#define R3_RTC_DAT0 RTC_ACCESS(0x86)
#define R3_RTC_DAT1 RTC_ACCESS(0x87)
#define R3_RTC_DAT2 RTC_ACCESS(0x88)
#define R3_RTC_DAT3 RTC_ACCESS(0x89)
#define R3_RTC_DAT4 RTC_ACCESS(0x8a)
#define R3_ALM_DAT0 RTC_ACCESS(0x8b)
#define R3_ALM_DAT1 RTC_ACCESS(0x8c)
#define R3_ALM_DAT2 RTC_ACCESS(0x8d)
#define R3_ALM_DAT3 RTC_ACCESS(0x8e)
#define R3_ALM_DAT4 RTC_ACCESS(0x8f)
//............. 0X0090 - 0X009F............ for wake up
#define R3_WKUP_EN RTC_ACCESS(0x90)
#define R3_WKUP_EDGE RTC_ACCESS(0x91)
#define R3_WKUP_CPND RTC_ACCESS(0x92)
#define R3_WKUP_PND RTC_ACCESS(0x93)
#define R3_WKUP_LEVEL RTC_ACCESS(0x94)
//............. 0X00A0 - 0X00AF............ for system
#define R3_TIME_CON RTC_ACCESS(0xa0)
#define R3_TIME_CPND RTC_ACCESS(0xa1)
#define R3_TIME_PND RTC_ACCESS(0xa2)
#define R3_ADC_CON RTC_ACCESS(0xa4)
#define R3_OSL_CON RTC_ACCESS(0xa5)
#define R3_WKUP_SRC RTC_ACCESS(0xa8)
#define R3_RST_SRC RTC_ACCESS(0xa9)
#define R3_RST_CON RTC_ACCESS(0xab)
#define R3_CLK_CON RTC_ACCESS(0xac)
//............. 0X00B0 - 0X00BF............ for PORT control
#define R3_PR_IN RTC_ACCESS(0xb0)
#define R3_PR_OUT RTC_ACCESS(0xb1)
#define R3_PR_DIR RTC_ACCESS(0xb2)
#define R3_PR_DIE RTC_ACCESS(0xb3)
#define R3_PR_PU0 RTC_ACCESS(0xb4)
#define R3_PR_PU1 RTC_ACCESS(0xb5)
#define R3_PR_PD0 RTC_ACCESS(0xb6)
#define R3_PR_PD1 RTC_ACCESS(0xb7)
#define R3_PR_HD0 RTC_ACCESS(0xb8)
#define R3_PR_HD1 RTC_ACCESS(0xb9)
#endif
loader/ble_app_ota_update/include_lib/driver/cpu/br35/sfr.h
+1541
View File
File diff suppressed because it is too large Load Diff
loader/ble_app_ota_update/include_lib/driver/cpu/br35/timer.h
+17
View File
@@ -0,0 +1,17 @@
#ifndef __TIMER_H__
#define __TIMER_H__
#include "typedef.h"
u32 tmr_2ms_cnt_get(void);
void sys_tmr_init(void (*cb)(void));
void sys_tmr_close(void);
#endif
loader/ble_app_ota_update/include_lib/driver/cpu/br35/uart.h
+10
View File
@@ -0,0 +1,10 @@
#ifndef __UART_H__
#define __UART_H__
#include "typedef.h"
int putchar(int a);
void uart_init(const char *tx_io, u32 baud);
void uart_close(void);
#endif
loader/ble_app_ota_update/include_lib/driver/cpu/br35/wdt.h
+32
View File
@@ -0,0 +1,32 @@
#ifndef __WDT_H__
#define __WDT_H__
#include "typedef.h"
enum {
WDT_1ms = 0,
WDT_2ms,
WDT_4ms,
WDT_8ms,
WDT_16ms,
WDT_32ms,
WDT_64ms,
WDT_128ms,
WDT_256ms,
WDT_512ms,
WDT_1s,
WDT_2s,
WDT_4s,
WDT_8s,
WDT_16s,
WDT_32s,
};
void wdt_init(u32 level);
void wdt_clear();
#endif /*WDT_H*/
loader/ble_app_ota_update/include_lib/driver/device/dev_mg/device_errno.h
+44
View File
@@ -0,0 +1,44 @@
//设备错误代码：
typedef enum dev_err {
DEV_ERR_NONE = 0,
DEV_ERR_NOT_MOUNT,
DEV_ERR_OVER_CAPACITY,
DEV_ERR_UNKNOW_CLASS,
DEV_ERR_NOT_READY,//设备已经在线，但是没初始化完成
DEV_ERR_LUN,
DEV_ERR_TIMEOUT,
DEV_ERR_CMD_TIMEOUT,
DEV_ERR_READ_TIMEOUT,//0x08
DEV_ERR_WRITE_TIMEOUT,
DEV_ERR_OFFLINE,//0x0a
DEV_ERR_CRC,
DEV_ERR_CMD_CRC,
DEV_ERR_READ_CRC,
DEV_ERR_WRITE_CRC,
DEV_ERR_CONTROL_STALL,
DEV_ERR_RXSTALL,//0x10
DEV_ERR_TXSTALL,
DEV_ERR_CONTROL,
DEV_ERR_NOT_STORAGE,
DEV_ERR_INVALID_PATH,
DEV_ERR_INVALID_DATA,
DEV_ERR_OUTOFMEMORY,
DEV_ERR_HANDLE_FREE,
DEV_ERR_INVALID_HANDLE,//24
DEV_ERR_INVALID_BUF,
DEV_ERR_INUSE,
DEV_ERR_NO_READ,
DEV_ERR_NO_WRITE,
DEV_ERR_NO_IOCTL,
DEV_ERR_NO_POWER,
DEV_ERR_NOT_EXIST,
DEV_ERR_UNKNOW,
} DEV_ERR;
loader/ble_app_ota_update/include_lib/driver/device/norflash/norflash.h
+264
View File
@@ -0,0 +1,264 @@
#ifndef __NORFLASH_H__
#define __NORFLASH_H__
#include "typedef.h"
//spi_width:
#define SPI_MODE_UNIDIR_1BIT 0//半双工，do分时发送/接收
#define SPI_MODE_BIDIR_1BIT 1//全双工，di接收，do发送
#define SPI_MODE_UNIDIR_2BIT 2//半双工，di & do共2bit分时发送/接收
#define SPI_MODE_UNIDIR_4BIT 4//半双工，di & do & wp & hold 共4bit分时发送/接收
#define WINBOND_WRITE_ENABLE 0x06
#define WINBOND_WRITE_SR_ENABLE 0x50
#define WINBOND_JEDEC_ID 0x9F
#define WINBOND_UUID 0x4B
#define WINBOND_READ_SR1 0x05
#define WINBOND_READ_SR2 0x35
#define WINBOND_READ_SR3 0x15
#define WINBOND_WRITE_SR1 0x01
#define WINBOND_WRITE_SR2 0x31
#define WINBOND_WRITE_SR3 0x11
#define WINBOND_FAST_READ 0x0B
#define WINBOND_FAST_READ_DUAL_OUTPUT 0x3B
#define WINBOND_FAST_READ_QUAD_OUTPUT 0x6B
#define WINBOND_FAST_READ_DUAL_IO 0xBB
#define WINBOND_FAST_READ_QUAD_IO 0xEB
#define WINBOND_CONTINUOUS_READ_NORMAL_MODE 0x00
#define WINBOND_CONTINUOUS_READ_ENHANCE_MODE 0x20
#define WINBOND_PAGE_PROGRAM 0x02
#define WINBOND_PAGE_ERASE 0x81
#define WINBOND_SECTOR_ERASE 0x20
#define WINBOND_BLOCK_ERASE 0xD8
#define WINBOND_CHIP_ERASE 0xC7
#define WINBOND_POWER_DOWN 0xB9
#define WINBOND_RELEASE 0xAB
struct flash_info_t {
u8 uuid[16];
u32 id;
u32 capacity;
};
struct flash_wp_arg {
u32 id;
u8 split_mode: 1; //0 连续写，1，分开写
u8 write_en_use_50h: 1; //0:06H 1:50H
u8 res: 2;
u8 numOfwp_array: 4; //写保护参数的个数
struct {
u8 sr1;
u8 sr2;
u16 wp_addr; //写保护结束地址,单位K
} wp_array[15];
} __attribute__((packed));
struct custom_data_t {
u16 u16crc;
u16 len;
u8 otp_mode;//0xa0:flash_mode 0xa1:otp mode
union {
struct {
u8 wr_sr_cmd[2];//寄存器的写命令，当两个命令是一样的，就使用连续写模式
u8 otp_lock_sr1;
u8 otp_lock_sr1_mask;//mask ==0 就忽略此寄存器
u8 otp_lock_sr2;
u8 otp_lock_sr2_mask;//mask ==0 就忽略此寄存器
u16 otp_page_num;
u16 otp_page_size;
u32 otp_offset[5];
} __attribute__((packed)) otp_info;
u8 user_info_data[59];
} __attribute__((packed)) u;
} __attribute__((packed));
struct spi_platform_data {
u8 spi_idx;
u8 width;
u8 clk_div;
u8 port;
u8 cs_port;
u8 clk_port;
u8 do_port;
u8 di_port;
u8 d2_port;
u8 d3_port;
};
enum DEV_FLASH_TYPE {
DEV_FLASH_INTERNAL_NORFLASH,
DEV_FLASH_EXTERNAL_NORFLASH,
DEV_FLASH_NANDFLASH,
DEV_FLASH_NANDFLASH_FTL,
};
struct flash_platform_data {
enum DEV_FLASH_TYPE flash_type;
u8 read_mode;
u8 power_io;
u8 power_io_level;
u8 power_ldo_io;
u8 power_ldo_io_level;
u8 qe_position;
struct spi_platform_data spi_pdata;
};
struct flash_info_t *get_flash_info(void);
void flash_poweron_base(u32 port, u32 out0_time, u32 poweron_time, void (*custom_udelay)(u32), void (*custom_mdelay)(u32));
void flash_poweroff_base(u32 port, u32 out0_time, u32 discharge_time, void (*custom_udelay)(u32), void (*custom_mdelay)(u32));
u8 get_flash_is4byte_mode(void);
u32 get_flash_capacity(void);
u32 norflash_get_id(void);
void norflash_get_uuid(u8 *buffer);
u16 norflash_cmd_custom(void);
void norflash_read_status_reg(u8 *status_reg1, u8 *status_reg2);
u8 norflash_spi_write_sr_reg(u8 reg1, u8 reg2) ;
int norflash_write_protect(u8 sr_mode, u8 wr_en_mode, u32 sr1, u32 sr2);
int norflash_write_protect_config(u32 addr, const struct flash_wp_arg *p);
#define TZFLASH_STA_NUM 4
struct flash_reg {
u8 cmd[4];
u8 sr_value[4];
u8 sr_mask[4];
u8 num_of_reg: 2;
u8 wr_en_mode: 1;
u8 continue_mode: 4;
u8 rev: 1;
};
struct flash_func_len {
u16 all_len;
u8 version;
u8 func_len;//lb
u8 sta_len;//lb
u8 func_otp;//lb
u8 func_dtr;
u8 func_wp;//bp,tb,sec,cmp
u8 func_wps;
u8 func_wps_op;
u8 func_qe;
u8 func_srp;
u8 func_sus;
u8 func_dc;
u8 func_drv;
u8 func_mpm;//dp
u8 func_qpi;
u8 func_init;
u8 func_read_continue;
} __attribute__((packed));
#define TZFLASH_STA_NUM 4
struct flash_sta_cmd {
u8 sta_cmd_r[TZFLASH_STA_NUM];
u8 sta_cmd_w[TZFLASH_STA_NUM];
} __attribute__((packed));
#define FLASH_SUPPORT_MPM_FUNC 0
struct flash_dev_sta_info {
struct flash_func_len func_cfg;
struct flash_sta_cmd sta_cfg;
u8 *cfg_ptr;
};
struct flash_otp_cfg {//flash otp信息
u32 otp_offset[5];//otp page的偏移地址组数
u16 otp_page_size;//otp的page大小
u8 otp_NumberOfpage;//otp的page数量
// struct flash_reg lock_cfg[2];//read,write
u8 wr_en_cmd;//0x50h:sr,0x06h:wr_en
u8 sr_mask[TZFLASH_STA_NUM];
u8 sr_value[TZFLASH_STA_NUM];//注意:锁定后不可擦写,sr的值也常是1
} __attribute__((packed));
struct flash_wps_cfg {//flash wps信息
u8 wr_en_cmd;//0x50h:sr,0x06h:wr_en
u8 sr_mask[TZFLASH_STA_NUM];
u8 sr_value[TZFLASH_STA_NUM];
// struct flash_reg r_reg_cfg;//read
// struct flash_reg w_reg_cfg;//write
} __attribute__((packed));
struct flash_wp_cfg { //写保护配置信息
u8 numOfwp_array;//写保护参数的个数
u8 wr_en_cmd;//0x50h:sr,06h:
u8 sr_mask[TZFLASH_STA_NUM]; //sr要保留或修改的bit
struct {
u8 sr_value[TZFLASH_STA_NUM]; //写保护sr取值
u16 wp_addr;//写保护结束地址,单位K
} wp_array[0]; //写保护的组数，修改可变长
} __attribute__((packed));
struct flash_dtr_cfg {
s8 x1_dummy;//-1:使用默认值
s8 x2_dummy;//-1:使用默认值
s8 x4_dummy;//-1:使用默认值,-2:不支持
} __attribute__((packed));
struct flash_reg_param {
int reg_mask;//需配置的reg映射
u8 sr_mask[TZFLASH_STA_NUM];
u8 sr_value[TZFLASH_STA_NUM];
u8 wr_en_cmd;//0x50h:sr,0x06h:wr_en
};
struct wps_addr_info {
u8 lock_en;
u32 wp_saddr;
u32 wp_eaddr;
};
int norflash_cfg_wpl(struct flash_wps_cfg *cfg);
int norflash_set_wps_addr(u8 lock, u32 saddr, u32 eaddr);
int norflash_params_v3_wp(u32 wp_addr, int index, struct flash_wp_cfg *cfg);
int norflash_get_flash_v3_wp_func_value(u8 *cfg_buf);
int norflash_get_flash_v3_dtr_func_value(u8 *cfg_buf);
void norflash_exit_continue_mode(void);
#ifdef __SFC_DTR
void __dtr_norflash_exit_continue_mode(void);
#endif
int norflash_read(u8 *buf, u32 addr, u32 len);
int norflash_write(u8 *buf, u32 addr, u32 len);
int norflash_write_async(u8 *buf, u32 offset, u32 len);
u8 norflash_eraser(u32 eraser_cmd, u32 addr);
u8 norflash_read_otp_lb(void);
u32 norflash_erase_otp(u32 page);
u32 norflash_write_otp(u8 *buffer, u32 len, u32 page, u32 offset);
void norflash_read_otp(u8 *buffer, u32 len, u32 page, u32 offset);
void norflash_read_otp_page(u8 *buffer, u32 len, u32 addr);
#ifdef BFLT_AUTH_BURN
u32 bflt_norflash_read_otp(u8 *buffer, u32 len, u32 offset) ;
u32 bflt_norflash_write_otp(u8 *buffer, u32 len, u32 offset) ;
u32 bflt_norflash_erase_otp(u32 offset) ;
u32 norflash_otp_lock(u8 *custom) ;
#endif
void norflash_enter_powerdown(void);
void norflash_powerdown_release(u32 delay);
void norflash_soft_reset(u32 delay);
void norflash_init(struct flash_platform_data *pdata);
void norflash_read_bt_mac(u8 *mac);
int norflash_ioctl(u32 cmd, u32 arg);
void norflash_select_device(u32 index, u32 port);
u8 P25QXXH_flash_close_quad_page_mode();
extern const struct device_operations norflash_dev_ops;
#endif
loader/ble_app_ota_update/include_lib/driver/jlfs/jlfs.h
+76
View File
@@ -0,0 +1,76 @@
#ifndef __JLFS_H__
#define __JLFS_H__
#include "typedef.h"
typedef struct {
u32 addr; //flash里的绝对地址
u32 size; //文件大小
u32 pos; //操作的偏移量
u32 res; //预留参数
} JLFS_FILE;
struct jlfs_flash_head {
u16 head_crc;
u16 size4burner;
char vid[4];
u32 flash_size;
u8 fs_version;
u8 BlockAlignSize;
u16 SpecialOptFlag;
char pid[16];
};
struct jlfs_file_head {
u16 head_crc;
u16 data_crc;
u32 addr;
u32 len;
u8 attr;
u8 res;
u16 index;
char name[16];
};
struct jlfs_app_info_head {
u16 head_crc;
u16 data_crc;
u16 encodedata_crc;
u16 version;
u32 len;
u32 reserved;
char name[16];
};
void *get_global_buffer(u32 size);
u32 jlfs_get_flash_align_size(void);
u32 jlfs_get_flash_app_base_addr(void);
u32 jlfs_get_flash_eoffset_size(void);
u32 jlfs_get_app_entry_addr(void);
u8 *jlfs_get_isd_cfg_ptr(void);
u8 jlfs_read_isd_cfg_ini(const char *cfg, void *value);
u8 jlfs_mount(void);
u8 jlfs_fopen_by_addr(JLFS_FILE *file, u32 addr);
u8 jlfs_fopen_by_name(JLFS_FILE *file, const char *name, u8 mode);
u32 jlfs_fread(JLFS_FILE *file, u8 *buf, u32 len);
u32 jlfs_erase(JLFS_FILE *file, u32 len);
u32 jlfs_write(JLFS_FILE *file, u8 *buf, u32 len);
void jlfs_fseek(JLFS_FILE *file, u32 offset);
void jlfs_get_pid_vid(u8 *pid, u8 *vid);
void jlfs_get_bt_mac(u8 *mac);
u32 jlfs_get_flen_by_name(const char *name);
u32 jlfs_get_idle_bank_info(JLFS_FILE *file, u32 mode);
u32 jlfs_updata_dual_bank_info(JLFS_FILE *file, u16 data_crc);
/* --------------------------------------------------------------------------*/
/**
* @brief 选择哪个code跑，必须在 jlfs_mount() 前调用才有效
*
* @param code_index 0:code0 1:code1 -1:自动切换（原模式） >1的数值会被强制为code0
*/
/* ----------------------------------------------------------------------------*/
void jlfs_dual_bank_choose_code(u8 code_index);
#endif
loader/ble_app_ota_update/include_lib/driver/jlup/upgrade.h
+16
View File
@@ -0,0 +1,16 @@
#ifndef __UPGRADE_H__
#define __UPGRADE_H__
#include "typedef.h"
void *get_sdk_swap_addr();
void goto_uart_upgrade(void);
void goto_mask_usb_updata(void);
u8 update_loop_run(u32 flash_ota_addr);
u8 jl_check_upgrade(u8 jlfs_err);
#endif
loader/ble_app_ota_update/include_lib/driver/power/power_reset.h
+15
View File
@@ -0,0 +1,15 @@
#ifndef __POWER_RESET_H__
#define __POWER_RESET_H__
enum RESET_FLAG {
RESET_FLAG_RESERVE,
EXCEPTION_FLAG,
ASSERT_FLAG,
UPDATE_FLAG,
BT_FLAG,
LP_OSC_UP_TO,
};
void system_reset(enum RESET_FLAG flag);
#endif
loader/ble_app_ota_update/include_lib/jl_rcsp/JL_rcsp_api.h
+43
View File
@@ -0,0 +1,43 @@
#ifndef _JL_RCSP_LIB_API_H_
#define _JL_RCSP_LIB_API_H_
#include "typedef.h"
#define USE_LITTLE_ENDIAN 0
#define USE_BIG_ENDIAN 1
#define USE_ENDIAN_TYPE USE_LITTLE_ENDIAN
#define AI_LICENCE_LEN 16
enum {
TULING = 0,
DEEPBRAIN,
};
#pragma pack(1)
struct _AI_platform {
u8 platform;
u8 license[AI_LICENCE_LEN];
};
#pragma pack()
u16 app_htons(u16 n);
u16 app_ntohs(u16 n);
u32 app_htonl(u32 n);
u32 app_ntohl(u32 n);
void JL_rcsp_auth_init(int (*send)(void *, u8 *, u16), u8 *link_key, u8 *addr);
void JL_rcsp_auth_reset(void);
u8 JL_rcsp_get_auth_flag(void);
void JL_rcsp_auth_recieve(u8 *buffer, u16 len);
u8 get_rcsp_version(void);
void get_ai_platform(struct _AI_platform *p, u8 platform);
void JL_rcsp_set_no_auth(void);
void JL_rcsp_set_pvid_flag(u8 flag);
#endif //_JL_RCSP_LIB_H_
loader/ble_app_ota_update/include_lib/jl_rcsp/JL_rcsp_packet.h
+101
View File
@@ -0,0 +1,101 @@
#ifndef __JL_PACKET_H__
#define __JL_PACKET_H__
#include "typedef.h"
#define READ_BIG_U16(a) ((*((u8*)(a)) <<8) + *((u8*)(a)+1))
#define READ_BIG_U32(a) ((*((u8*)(a)) <<24) + (*((u8*)(a)+1)<<16) + (*((u8*)(a)+2)<<8) + *((u8*)(a)+3))
#define READ_LIT_U16(a) (*((u8*)(a)) + (*((u8*)(a)+1)<<8))
#define READ_LIT_U32(a) (*((u8*)(a)) + (*((u8*)(a)+1)<<8) + (*((u8*)(a)+2)<<16) + (*((u8*)(a)+3)<<24))
#define WRITE_BIG_U16(a,src) {*((u8*)(a)+0) = (u8)(src>>8); *((u8*)(a)+1) = (u8)(src&0xff); }
#define WRITE_BIG_U32(a,src) {*((u8*)(a)+0) = (u8)((src)>>24); *((u8*)(a)+1) = (u8)(((src)>>16)&0xff);*((u8*)(a)+2) = (u8)(((src)>>8)&0xff);*((u8*)(a)+3) = (u8)((src)&0xff);}
#define WRITE_LIT_U16(a,src) {*((u8*)(a)+1) = (u8)(src>>8); *((u8*)(a)+0) = (u8)(src&0xff); }
#define WRITE_LIT_U32(a,src) {*((u8*)(a)+3) = (u8)((src)>>24); *((u8*)(a)+2) = (u8)(((src)>>16)&0xff);*((u8*)(a)+1) = (u8)(((src)>>8)&0xff);*((u8*)(a)+0) = (u8)((src)&0xff);}
#pragma pack(1)
typedef union __HEAD_BIT {
struct {
u16 _OpCode: 8; //OpCode val
u16 _unsed : 6; //unsed
u16 _resp : 1; //request for response
u16 _type : 1; //command or response
} _i;
u16 _t;
} HEAD_BIT;
struct __JL_PACKET {
u8 tag[3];
HEAD_BIT head;
u16 length;
u8 data[0];
};
#pragma pack()
typedef struct __JL_PACKET JL_PACKET;
#define JL_PACK_START_TAG0 (0xfe)
#define JL_PACK_START_TAG1 (0xdc)
#define JL_PACK_START_TAG2 (0xba)
#define JL_PACK_END_TAG (0xef)
#define JL_ONE_PACKET_LEN(n) (sizeof(JL_PACKET) + n + 1)
#ifdef JL_RCSP_UBOOT_LIB
#if (defined(CONFIG_CPU_BD47) || defined(CONFIG_CPU_BR29)) && defined(BLE_APP_LOW_RAM_USED) // bd47 内存紧缺
#define JL_MTU_RESV (264L)
#else
#define JL_MTU_RESV (520L)
#endif
#define JL_MTU_SEND (264L)
#define JL_RECIEVE_BUF_SIZE ((JL_MTU_RESV + sizeof(JL_PACKET))*2)
#define JL_CMD_POOL_SIZE (JL_MTU_SEND)
#define JL_RESP_POOL_SIZE (JL_MTU_SEND*2)
#define JL_WAIT_RESP_POOL_SIZE (JL_MTU_SEND)
#else
#ifdef APP_USE_MOR_SPACE
#define JL_MTU_RESV (4106L)
#else
#if (defined(CONFIG_CPU_BD47) || defined(CONFIG_CPU_BR29)) && defined(BLE_APP_LOW_RAM_USED) // bd47 内存紧缺
#define JL_MTU_RESV (264L)
#else
#define JL_MTU_RESV (520L)
#endif
#endif
#define JL_MTU_SEND (264L)
#define JL_RECIEVE_BUF_SIZE (JL_MTU_RESV + sizeof(JL_PACKET) + 128)
#define JL_CMD_POOL_SIZE (JL_MTU_SEND*4)
#define JL_RESP_POOL_SIZE (JL_MTU_SEND*2)
#define JL_WAIT_RESP_POOL_SIZE (JL_MTU_SEND*2)
#endif
u32 rcsp_packet_need_buf_size(void);
u32 rcsp_packet_buf_init(u8 *buf, u32 len);
u16 JL_packet_get_rx_max_mtu(void);
u16 JL_packet_get_tx_max_mtu(void);
u16 JL_packet_set_mtu(u16 mtu);
void JL_packet_recieve(void *buf, u16 len);
u32 JL_pack_data_read_all(void *buf, u16 len);
void JL_packet_clear_all_data(void);
bool JL_packet_find(u8 *r_buf, JL_PACKET **packet);
void JL_packet_init(void);
void JL_packet_clear(void);
void JL_packet_packing(
JL_PACKET *packet,
u8 OpCode,
u8 type,
u8 request_rsp,
u8 *extra_param,
u16 extra_len,
u8 *data,
u16 len);
#endif//__JL_PACKET_H__
loader/ble_app_ota_update/include_lib/jl_rcsp/JL_rcsp_protocol.h
+175
View File
@@ -0,0 +1,175 @@
#ifndef __JL_PROTOCOL_H__
#define __JL_PROTOCOL_H__
#include "typedef.h"
#include "JL_rcsp_packet.h"
#define ATTR_TYPE_PROTOCOL_VERSION (0)
#define ATTR_TYPE_SYS_INFO (1)
#define ATTR_TYPE_EDR_ADDR (2)
#define ATTR_TYPE_PLATFORM (3)
#define ATTR_TYPE_FUNCTION_INFO (4)
#define ATTR_TYPE_DEV_VERSION (5)
#define ATTR_TYPE_SDK_TYPE (6)
#define ATTR_TYPE_UBOOT_VERSION (7)
#define ATTR_TYPE_DOUBLE_PARITION (8)
#define ATTR_TYPE_UPDATE_STATUS (9)
#define ATTR_TYPE_DEV_VID_PID (10)
#define ATTR_TYPE_DEV_AUTHKEY (11)
#define ATTR_TYPE_DEV_PROCODE (12)
#define ATTR_TYPE_DEV_MAX_MTU (13)
#define ATTR_TYPE_MD5_GAME_SUPPORT (19)
#define COMMON_INFO_ATTR_BATTERY (0)
#define COMMON_INFO_ATTR_VOL (1)
#define COMMON_INFO_ATTR_DEV (2)
#define COMMON_INFO_ATTR_ERR_REPORT (3)
#define COMMON_INFO_ATTR_EQ (4)
#define COMMON_INFO_ATTR_FILE_BROWSE_TYPE (5)
#define COMMON_INFO_ATTR_FUN_TYPE (6)
#define COMMON_INFO_ATTR_LIGHT (7)
#define COMMON_INFO_ATTR_FMTX (8)
#define BT_INFO_ATTR_01 (0)
#define MUSIC_INFO_ATTR_STATUS (0)
#define MUSIC_INFO_ATTR_FILE_NAME (1)
#define MUSIC_INFO_ATTR_FILE_PLAY_MODE (2)
#define RTC_INFO_ATTR_RTC_TIME (0)
#define RTC_INFO_ATTR_RTC_ALRAM (1)
#define LINEIN_INFO_ATTR_STATUS (0)
#define SDK_TYPE_AC690X 0x0
#define SDK_TYPE_AC692X 0x1
#define SDK_TYPE_AC693X 0x2
#define SDK_TYPE_AC695X 0x3
#define SDK_TYPE_AC697X 0x4
#define SDK_TYPE_AC693N 0x5
#define SDK_TYPE_AC698N 0x06
#if (defined CONFIG_CPU_BR21)
#define RCSP_SDK_TYPE SDK_TYPE_AC692X
#elif (defined CONFIG_CPU_BR22)
#define RCSP_SDK_TYPE SDK_TYPE_AC693X
#elif (defined CONFIG_CPU_BR23)
#define RCSP_SDK_TYPE SDK_TYPE_AC695X
#elif (defined CONFIG_CPU_BR30)
#define RCSP_SDK_TYPE SDK_TYPE_AC697X
#elif (defined CONFIG_CPU_BD29)
#define RCSP_SDK_TYPE SDK_TYPE_AC693N
#elif (defined CONFIG_CPU_BR34)
#define RCSP_SDK_TYPE SDK_TYPE_AC698N
#else
#define RCSP_SDK_TYPE SDK_TYPE_AC693X
#endif
enum {
JL_OPCODE_DATA = 0x01,
JL_OPCODE_GET_TARGET_FEATURE_MAP = 0x02,
JL_OPCODE_GET_TARGET_FEATURE = 0x03,
JL_OPCODE_SWITCH_DEVICE = 0x04,
JL_OPCODE_SYS_INFO_GET = 0x07,
JL_OPCODE_SYS_INFO_SET = 0x08,
JL_OPCODE_SYS_INFO_AUTO_UPDATE = 0x09,
JL_OPCODE_FILE_BROWSE_REQUEST_START = 0x0C,
JL_OPCODE_FILE_BROWSE_REQUEST_STOP = 0x0D,
JL_OPCODE_SYS_OPEN_BT_SCAN = 0x12,
JL_OPCODE_SYS_UPDATE_BT_STATUS = 0X13,
JL_OPCODE_SYS_STOP_BT_SCAN = 0X14,
JL_OPCODE_CUSTOMER_USER = 0xFF,
};
enum {
JL_NOT_NEED_RESPOND = 0,
JL_NEED_RESPOND,
};
enum {
JL_AUTH_NOTPASS = 0,
JL_AUTH_PASS,
};
typedef enum __JL_ERR {
JL_ERR_NONE = 0x0,
JL_ERR_SEND_DATA_OVER_LIMIT,
JL_ERR_SEND_BUSY,
JL_ERR_SEND_NOT_READY,
JL_ERR_EXIT,
} JL_ERR;
typedef enum __JL_PRO_STATUS {
JL_PRO_STATUS_SUCCESS = 0x0,
JL_PRO_STATUS_FAIL,
JL_PRO_STATUS_UNKOWN_CMD,
JL_PRO_STATUS_BUSY,
JL_PRO_STATUS_NO_RESPONSE,
JL_PRO_STATUS_CRC_ERR,
JL_PRO_STATUS_ALL_DATA_CRC_ERR,
JL_PRO_STATUS_PARAM_ERR,
JL_PRO_STATUS_RESP_DATA_OVER_LIMIT,
} JL_PRO_STATUS;
enum {
JL_ERR_PACKAGE_RETRY_OPT_FLAG_DISENABLE,
JL_ERR_PACKAGE_RETRY_OPT_FLAG_ENABLE,
JL_ERR_PACKAGE_RETRY_OPT_TRIGGER,
JL_ERR_PACKAGE_RETRY_OPT_PREPARE,
JL_ERR_PACKAGE_RETRY_OPT_QUERY,
JL_ERR_PACKAGE_RETRY_OPT_END,
};
///*< JL_CMD、JL_CMD_response、JL_DATA、JL_DATA_response packet send functions>*/
JL_ERR JL_CMD_send(u8 OpCode, u8 *data, u16 len, u8 request_rsp);
JL_ERR JL_CMD_response_send(u8 OpCode, u8 status, u8 sn, u8 *data, u16 len);
JL_ERR JL_DATA_send(u8 OpCode, u8 CMD_OpCode, u8 *data, u16 len, u8 request_rsp);
JL_ERR JL_DATA_response_send(u8 OpCode, u8 status, u8 sn, u8 CMD_OpCode, u8 *data, u16 len);
///*<JL_CMD、JL_CMD_response、JL_DATA、JL_DATA_response recieve>*/
typedef struct __JL_PRO_CB {
/*send function callback, SPP or ble*/
void *priv;
bool (*fw_ready)(void *priv);
s32(*fw_send)(void *priv, void *buf, u16 len);
/*JL_CMD、JL_CMD_response、JL_DATA、JL_DATA_response packet recieve callback*/
void (*CMD_resp)(void *priv, u8 OpCode, u8 OpCode_SN, u8 *data, u16 len);
void (*DATA_resp)(void *priv, u8 OpCode_SN, u8 CMD_OpCode, u8 *data, u16 len);
void (*CMD_no_resp)(void *priv, u8 OpCode, u8 *data, u16 len);
void (*DATA_no_resp)(void *priv, u8 CMD_OpCode, u8 *data, u16 len);
void (*CMD_recieve_resp)(void *priv, u8 OpCode, u8 status, u8 *data, u16 len);
void (*DATA_recieve_resp)(void *priv, u8 status, u8 CMD_OpCode, u8 *data, u16 len);
u8(*wait_resp_timeout)(void *priv, u8 OpCode, u8 counter);
void (*auth_pass_callback)(void *priv);
} JL_PRO_CB;
extern u32 rcsp_fw_ready(void);
extern u32 rcsp_protocol_need_buf_size(void);
extern void JL_protocol_init(u8 *buf, u32 len);
extern void JL_protocol_exit(void);
extern void JL_protocol_dev_switch(const JL_PRO_CB *cb);
extern void JL_protocol_data_recieve(void *priv, void *buf, u16 len);
extern void JL_protocol_resume(void);
extern void JL_protocol_process(void);
extern void set_auth_pass(u8 auth_pass);
extern void JL_set_cur_tick(u16 tick);
extern bool jl_rcsp_retry_handle(u8 opt);
#endif//__JL_PROTOCOL_H__
loader/ble_app_ota_update/include_lib/jl_rcsp/rcsp_control.h
+201
View File
@@ -0,0 +1,201 @@
#ifndef __RCSP_CONTROL_H__
#define __RCSP_CONTROL_H__
#define JL_RCSP_USER_COUSTOM_EN 0
#include "typedef.h"
//#include "custom_cfg.h"
//#include <le_user.h>
#if JL_RCSP_USER_COUSTOM_EN
#include "rcsp_user_api.h"
#endif
#ifdef USB_HID_MODULE_CONTROL
#include "rcsp_hid_inter.h"
#endif
#if (defined(CONFIG_CPU_BD47) || defined(CONFIG_CPU_BR29)) && defined(BLE_APP_LOW_RAM_USED) // bd47 内存紧缺
#define JL_CONTROLLER_POOL_SIZE (256 + 32)
#else
#define JL_CONTROLLER_POOL_SIZE 512
#endif
//for update cmd
#define JL_OPCODE_GET_DEVICE_UPDATE_FILE_INFO_OFFSET 0xe1 //rsp:addr[4]+len[2]
#define JL_OPCODE_INQUIRE_DEVICE_IF_CAN_UPDATE 0xe2 //req:len[2]+data[len]
#define JL_OPCODE_ENTER_UPDATE_MODE 0xe3 //
#define JL_OPCODE_EXIT_UPDATE_MODE 0xe4 //rsp:0x01(fail)
#define JL_OPCODE_SEND_FW_UPDATE_BLOCK 0xe5 //len:
#define JL_OPCODE_GET_DEVICE_REFRESH_FW_STATUS 0xe6
#define JL_OPCODE_SET_DEVICE_REBOOT 0xe7
#define JL_OPCODE_NOTIFY_TO_SWITCH_COMMUNICATION_WAY 0x0B //
#define JL_OPCODE_NOTIFY_UPDATE_CONENT_SIZE 0xe8
#define JL_OPCODE_GET_MD5 0xD4
#define JL_OPCODE_JL_PRIVATE 0xF0 //
#define JL_OPCODE_DATA_JL_PRIVATE 0xF1
//......................gpio.........................
//#ifndef UART_ENABLE
#define GET_GPIO_INFO_FLAG
//#endif
#define IO_GROUP_NUM 16
#define NUM_ERR 2
#define PARAM_ERR 1
#define NO_ERR 0
/*
typedef struct {
__RW __u32 OUT;
__RW __u32 IN;
__RW __u32 DIR;
__RW __u32 DIE;
__RW __u32 PU;
__RW __u32 PD;
__RW __u32 HD;
} JL_PORT_TypeDef;
#define JL_PORTA_BASE (ls_base + map_adr(0x01, 0x00))
#define JL_PORTA ((JL_PORT_TypeDef *)JL_PORTA_BASE)
#define JL_PORTB_BASE (ls_base + map_adr(0x01, 0x08))
#define JL_PORTB ((JL_PORT_TypeDef *)JL_PORTB_BASE)
#define JL_PORTC_BASE (ls_base + map_adr(0x01, 0x10))
#define JL_PORTC ((JL_PORT_TypeDef *)JL_PORTC_BASE)
#define JL_PORTD_BASE (ls_base + map_adr(0X01, 0X18))
#define JL_PORTD ((JL_PORT_TypeDef *)JL_PORTD_BASE)
*/
//......................gpio.........................
typedef enum __DEVICE_REFRESH_FW_STATUS {
DEVICE_UPDATE_STA_SUCCESS = 0, //升级成功(default)
DEVICE_UPDATE_STA_VERIFY_ERR, //升级完校验代码出错(default)
DEVICE_UPDATE_STA_FAIL, //升级失败(default)
DEVICE_UPDATE_STA_KEY_ERR, //加密key不匹配
DEVICE_UPDATE_STA_FILE_ERR, //升级文件出错
DEVICE_UPDATE_STA_TYPE_ERR, //升级类型出错,仅code_type;
DEVICE_UPDATE_STA_MAX_ERR,
} DEVICE_UPDATE_STA;
enum {
REBOOT_STA_READY = 0,
REBOOT_STA_NOT_ALLOW,
};
void rcsp_init(void (*)(void), void (*)(void));
void rcsp_dev_select(u8 type);
void function_change_inform(void);
bool common_msg_deal(u32 param);
bool ble_msg_deal(u32 param);
bool music_msg_deal(u32 param);
bool linein_msg_deal(u32 param);
bool rtc_msg_deal(u32 param);
u16 JL_rcsp_speech_data_send(u8 *buf, u16 len);
/* enum {
RCSP_BLE,
RCSP_SPP,
}; */
#define RCSP_BLE 0
#define RCSP_SPP 1
#define RCSP_HID 2
enum {
ANDROID,
APPLE_IOS,
};
struct ble_server_operation_t {
int(*adv_enable)(void *priv, u32 enable);
int(*disconnect)(void *priv);
int(*get_buffer_vaild)(void *priv);
int(*send_data)(void *priv, void *buf, u16 len);
int(*regist_wakeup_send)(void *priv, void *cbk);
int(*regist_recieve_cbk)(void *priv, void *cbk);
int(*regist_state_cbk)(void *priv, void *cbk);
int(*latency_enable)(void *priv, u32 enable);
int(*get_packet_num_of_not_sent)(void *priv);
int(*close)(void *priv);
};
struct JL_AI_VAR {
u8 JL_ble_status;
struct ble_server_operation_t *rcsp_ble;
u8 JL_spp_status;
struct spp_operation_t *rcsp_spp;
#ifdef USB_HID_MODULE_CONTROL
struct rcsp_hid_operation_t *rcsp_hid;
#endif
volatile u8 speech_state;
u32 feature_mask;
u8 device_type;
u8 phone_platform;
void (*start_speech)(void);
void (*stop_speech)(void);
u8 err_report;
volatile u8 file_browse_lock_flag;
u32 return_msg;
u8 spec_mode;
#if JL_RCSP_USER_COUSTOM_EN
struct __rcsp_user_var *rcsp_user;
#endif
volatile u8 rcsp_resume_cnt;
volatile u16 rcsp_tick_cnt;
};
struct _SPEECH_OVER_DEAL {
u8 last_task;
u8 status;
};
typedef enum __JL_ATTR_TYPE {
JL_ATTR_TYPE_PROTOCOL_VERSION = 0x0,
JL_ATTR_TYPE_SYS_INFO,
JL_ATTR_TYPE_EDR_INFO,
JL_ATTR_TYPE_PLATFORM,
JL_ATTR_TYPE_FUNCTION_INFO = 0x4,
JL_ATTR_TYPE_DEV_VERSION,
JL_ATTR_TYPE_SDK_TYPE,
JL_ATTR_TYPE_UBOOT_VERSION,
JL_ATTR_TYPE_FW_DOUBLE_BANK = 0x8,
JL_ATTR_TYPE_FORCE_UPDATE_STATUS,
JL_ATTR_TYPE_PID_VID,
#if 1//VER_INFO_EXT_CONUNT
JL_ATTR_TYPE_AUTH_KEY,
JL_ATTR_TYPE_PRO_CODE,
#endif
JL_ATTR_TYPE_CUSTOM_VER = 31,
JL_ATTR_TYPE_MAX,
} JL_ATTR_TYPE;
typedef struct _app_update_op_api_t {
void *(*data_send)(void *priv, u8 btupdata_sw, u8 seek_type, u32 offset_addr, u16 len);
void *(*notify_update_content_size)(void *priv, u32 size);
void *(*dev_disconnect)(void *priv);
int (*get_number_of_pkt_sending)(void *priv);
void (*register_update_data_handle)(void (*handle)(u8 *buf, u16 len));
void (*register_update_status_req_handle)(u8(*handle)(void));
void (*register_conn_state_change_handle)(void (*handle)(void *priv, u8 state));
void (*btstack_init)(void);
void (*task_run)(void);
void (*btstack_resume)(void);
void (*dev_set_discoverable_mode)(u8 mode);
void (*dev_close)(void);
} app_update_op_api_t;
extern struct JL_AI_VAR jl_ai_var;
extern struct _SPEECH_OVER_DEAL speech_deal_val;
extern void JL_controller_resp_udpate_status_request(u8 status);
extern void dev_get_update_opearation_table(app_update_op_api_t **interface_ptr);
#endif
loader/ble_app_ota_update/include_lib/lib_include.h
+237
View File
@@ -0,0 +1,237 @@
#ifndef __ALL_INCLUDE_H__
#define __ALL_INCLUDE_H__
//#include <string.h>
#include "typedef.h"
#include "common.h"
#include "printf.h"
#define UPDATE_GET_POWER_PIN 1 //获取power_pin脚
#define MUTIL_CPU_ENABLE 1 //多芯片升级支持
#define OTA_LOADER_RECORD_RST_INFO_CONFIG 1 //升级记录复位信息
#define OSC_1PIN_STABLE_EN 1 //osc 单脚牵引
//控制起来省空间。
#if defined(CONFIG_CPU_BR28) || defined(CONFIG_CPU_BR27) || defined(CONFIG_CPU_BR29) || defined(CONFIG_CPU_BR35)
#define UPDATE_COMPATIBILITY_EN 1 //升级兼容性处理
#else
#define UPDATE_COMPATIBILITY_EN 0 //升级兼容性处理
#endif
#if defined(CONFIG_CPU_BD49) || defined(CONFIG_CPU_SH58)
#undef UPDATE_GET_POWER_PIN
#undef MUTIL_CPU_ENABLE
#undef OTA_LOADER_RECORD_RST_INFO_CONFIG
#define UPDATE_GET_POWER_PIN 0 //获取power_pin脚
#define MUTIL_CPU_ENABLE 0 //多芯片升级支持
#define OTA_LOADER_RECORD_RST_INFO_CONFIG 0 //升级记录复位信息
#endif
#if OTA_LOADER_RECORD_RST_INFO_CONFIG
typedef struct {
///////////reset info////////////
u32 p3_rst_flag;
u32 p3_rst_src;
u32 p11_clock_pwr_con;
u32 p11_closk_rst_src;
u32 jl_lsbclk_pwr_con;
u32 jl_lsbrst_rst_src;
///////////exeception info////////////
u32 rets;
u32 reti;
u32 icfg;
u32 pc_trace5;
u32 pc_trace4;
u32 pc_trace3;
u32 pc_trace2;
u32 pc_trace1;
u32 pc_trace0;
u32 emu_msg;
u32 cemu_msg0;
u32 cemu_msg1;
u32 cemu_msg2;
u32 cemu_id;
u32 hemu_msg0;
u32 hemu_id;
u32 lemu_msg0;
u32 lemu_id;
} RESET_INFO;
u8 ota_loader_record_rst_info();
#endif
/*FPGA调试*/
//#define FPGA_MODE_DEBUG
/*串口打印控制器IO口占据*/
#define UART_ENABLE
//br23 用dp,br30yong usbdp
#define UART_DEBUG_IO "PA05"
#define UART_DEBUG_BAUD 1000000
/*打印调试信息*/
#if defined(CONFIG_CPU_BR22) || defined(CONFIG_CPU_BR26)
#define UART_API_USING_MASKROM_EN 0
#else
#define UART_API_USING_MASKROM_EN 0
#endif
/*升级设备在线检测使能位*/
#define UPDATA_DEV_ONLINE_CHECK_EN 0
#define UPDATA_FLASH_CONTROL 1//升级使能
#define BT_BREDR_EN BIT(0)
#define BT_BLE_EN BIT(1)
#define BT_NOMALE_POWER_CFG 0 //模拟正常配置
#define BT_LOW_POWER_CFG 1 //模拟低功耗配置
#define BT_ANALOG_CFG BT_NOMALE_POWER_CFG //模拟配置
enum {
BT_UPDATA_POWER_ON,
BT_UPDATA_JUMP_APP,
};
enum {
REQUES_CHECK_DATA = 0,
REQUES_READ_DATA = 1,
REQUES_STOP_DATA = 2,
};
#ifdef BLE_UPDATA_SUPPORT_CONNECT
// huayue add 2017/1/12
#define BT_POWER_MODE_ENABLE 0
#define BLE_ENCRYPT_ENABLE 0
#define BLE_PRIVACY_ENABLE 0
#define BLE_MASTER_ENABLE 0
#define THREAD_DEBUG_EN 1
#define BQB_RF_SET_DEBUG_EN 1
#define BQB_SYS_TIMER_DEBYG_EN 1
#define BLE_ATT_ENCRYPT_EN 0
#else
#define BT_POWER_MODE_ENABLE 0
#define BLE_ENCRYPT_ENABLE 0
#define BLE_PRIVACY_ENABLE 0
#define BLE_MASTER_ENABLE 0
#define THREAD_DEBUG_EN 0
#define BQB_RF_SET_DEBUG_EN 0
#define BQB_SYS_TIMER_DEBYG_EN 0
#define BLE_ATT_ENCRYPT_EN 0
#endif
//配置是否支持uboot升级
#if defined(CONFIG_CPU_BR22) || defined(CONFIG_CPU_BR21) || defined(CONFIG_CPU_BR18)
#define ALL_FLASH_INCLUDE_UBOOT_UPDATE_EN 0
#else //BR23/BR25/BR26/BR30/BD29
#define ALL_FLASH_INCLUDE_UBOOT_UPDATE_EN 1
#endif
//br18 & br22 origin version
#define FLASH_FRAMEWORK_VERSION_V1_EN 0
//br22 new flash framwork
#define FLASH_FRAMEWORK_VERSION_V2_EN 1
//配置单独配置升级采用什么格式
#define FORMAT_BR22_NEW 0
#define FORMAT_BR18_V2 1
#ifdef CONFIG_CPU_BR22
#define CFG_TOOL_BIN_FORMAT_SEL FORMAT_BR22_NEW
#else //BR18/BR26/BR23/BD29/BR21/BR25/BR30
#define CFG_TOOL_BIN_FORMAT_SEL FORMAT_BR18_V2
#endif
//配置是否支持外部用户接口
#if defined(CONFIG_CPU_BR23) || defined(CONFIG_CPU_BR28) || defined(CONFIG_CPU_BR35)
#define USER_API_CODE_SUPPORT_EN 1
#else
#define USER_API_CODE_SUPPORT_EN 0
#endif
//是否SPI0只采用TEAM A;
#define SPI0_PORT_TEAM_A_ONLY_EN 1
/*是否开启电量检测*/
#define LOW_POWER_DET_EN 0
//是否支持升级外部DSP
#if defined(CONFIG_CPU_BR22) && (EDR_UPDATA_SUPPORT_CONNECT)
#define EX_DSP_UPDATE_SUPPORT_EN 0
#else
#define EX_DSP_UPDATE_SUPPORT_EN 0
#endif
// #if defined(CONFIG_CPU_BR23)
// #define EX_FLASH_UPDATE_SUPPORT_EN 1
// #else
// #define EX_FLASH_UPDATE_SUPPORT_EN 0
// #endif
#if defined(CONFIG_CPU_BR23) && (EDR_UPDATA_SUPPORT_CONNECT)
//配置:经典蓝牙升级速度优化方案
//1.utilized the time waiting for rsp to program flash;
#define OTA_UPDATE_SPEED_OPTIMIZE_METHOD_1 1
//2.utilized the time waiting for programming to receive rsp data;
#define OTA_UPDATE_SPEED_OPTIMIZE_METHOD_2 1
#else
//配置:经典蓝牙升级速度优化方案
//1.utilized the time waiting for rsp to program flash;
#define OTA_UPDATE_SPEED_OPTIMIZE_METHOD_1 0
//2.utilized the time waiting for programming to receive rsp data;
#define OTA_UPDATE_SPEED_OPTIMIZE_METHOD_2 0
#endif
//支持ANC配置和系数升级使能
#if (defined(CONFIG_CPU_BR30) \
|| defined(CONFIG_CPU_BR34) \
|| defined(CONFIG_CPU_BR36) \
|| defined(CONFIG_CPU_BR28) \
|| defined(CONFIG_CPU_WL80)) \
|| defined(CONFIG_CPU_BR50) \
|| defined(CONFIG_CPU_BR35) \
|| defined(CONFIG_CPU_BR52) \
&& defined(EDR_UPDATA_SUPPORT_CONNECT) || defined(UART_UPDATA_MODULE_CONTROL)
#define ANC_CFG_AND_COEF_UPDATE_EN 1
#else
#define ANC_CFG_AND_COEF_UPDATE_EN 0
#endif
#if defined(CONFIG_CPU_BR42) || defined(CONFIG_CPU_BR46)
#define UPDATE_EFUSE 1
#else
#define UPDATE_EFUSE 0
#endif
//配置:是否升级保留区域文件(anc param .ect)
#if (CONFIG_CPU_BR30) || (CONFIG_CPU_BR34) || (CONFIG_CPU_BR36) || (CONFIG_CPU_BR28) || (CONFIG_CPU_BR50) || defined(CONFIG_CPU_BR35) || defined(CONFIG_CPU_BR52) || defined(CONFIG_CPU_BR56)
#define RESERVED_FILE_UPDATE_EN 1
#else
#define RESERVED_FILE_UPDATE_EN 0
#endif
//支持免晶振方案
#if (SD_MODULE_CONTROL || USB_HOST_MODULE_CONTROL || UART_UPDATA_USER_MODULE_CONTROL) && (defined(CONFIG_CPU_BR23) || defined(CONFIG_CPU_BR25))
#define CRYSTAL_FREE_EN 1
#else
#define CRYSTAL_FREE_EN 0
#endif
//仅支持串口测试模式
#define UART_UPDATE_ONLY_TEST_MODE 0
//蓝牙升级仅测试模式
#define BT_UPDATE_ONLY_TEST_MODE 0
//蓝牙测试模式是否不需要回连
#define BT_UPDATE_ONLY_TEST_WITHOUT_RECONNECT 0
#if FLASH_FRAMEWORK_VERSION_V1_EN && FLASH_FRAMEWORK_VERSION_V2_EN
#error "FLASH_FRAMEWORK_VERSION_1&2 NOT OPEN IN SAME TIME!!!\n"
#endif
#endif
loader/ble_app_ota_update/include_lib/liba/br35/JL_rcsp_uboot.a
BIN
View File
Binary file not shown.
loader/ble_app_ota_update/include_lib/liba/br35/bt_protocol.a
BIN
View File
Binary file not shown.
loader/ble_app_ota_update/include_lib/liba/br35/btctrler_v2.a
BIN
View File
Binary file not shown.
loader/ble_app_ota_update/include_lib/liba/br35/ota_loader_driver.a
BIN
View File
Binary file not shown.
loader/ble_app_ota_update/include_lib/liba/br35/system.a
BIN
View File
Binary file not shown.
loader/ble_app_ota_update/include_lib/liba/br35/update.a
BIN
View File
Binary file not shown.
loader/ble_app_ota_update/include_lib/system/cpu/br35/asm/cpu.h
+383
View File
@@ -0,0 +1,383 @@
#ifndef ASM_CPU_H
#define ASM_CPU_H
#include "sfr.h"
#include "csfr.h"
#ifndef __ASSEMBLY__
typedef unsigned char u8, bool, BOOL;
typedef char s8;
typedef unsigned short u16;
typedef signed short s16;
typedef unsigned int u32;
typedef signed int s32;
typedef unsigned long long u64;
typedef u32 FOURCC;
typedef long long s64;
typedef unsigned long long u64;
#endif
#define ___trig __asm__ volatile ("trigger")
#ifndef BIG_ENDIAN
#define BIG_ENDIAN 0x3021
#endif
#ifndef LITTLE_ENDIAN
#define LITTLE_ENDIAN 0x4576
#endif
#define CPU_ENDIAN LITTLE_ENDIAN
#ifdef BT_DUT_INTERFERE
#define CPU_CORE_NUM 1 //dut interfere
#else
#define CPU_CORE_NUM 1 //sdk
#endif
#define OS_CORE_AFFINITY_ENABLE 1
#define CPU_TASK_CLR(a)
#define CPU_TASK_SW(a) \
do { \
q32DSP(a)->ILAT_SET |= BIT(3-a); \
} while (0)
#define CPU_INT_NESTING 2
#ifndef __ASSEMBLY__
#if CPU_CORE_NUM > 1
__attribute__((always_inline))
static int current_cpu_id()
{
unsigned id;
asm volatile("%0 = cnum" : "=r"(id) ::);
return id ;
}
__attribute__((always_inline))
static int core_num(void)
{
u32 num;
asm volatile("%0 = cnum" : "=r"(num) :);
return num;
}
#else
static inline int current_cpu_id()
{
return 0;
}
static inline int core_num(void)
{
return 0;
}
#endif
static inline int cpu_in_irq()
{
int flag;
__asm__ volatile("%0 = icfg" : "=r"(flag));
return flag & 0xff;
}
static inline int cpu_irq_disabled()
{
int flag;
__asm__ volatile("%0 = icfg" : "=r"(flag));
return (flag & 0x300) != 0x300;
}
#if 0
static inline int data_sat_s16(int ind)
{
if (ind > 32767) {
ind = 32767;
} else if (ind < -32768) {
ind = -32768;
}
return ind;
}
#else
static inline int data_sat_s16(int ind)
{
__asm__ volatile(
" %0 = sat16(%0)(s) \t\n"
: "=&r"(ind)
: "0"(ind)
:);
return ind;
}
#endif
static inline u32 reverse_u32(u32 data32)
{
#if 0
u8 *dataptr = (u8 *)(&data32);
data32 = (((u32)dataptr[0] << 24) | ((u32)dataptr[1] << 16) | ((u32)dataptr[2] << 8) | (u32)dataptr[3]);
#else
__asm__ volatile("%0 = rev8(%0) \t\n" : "=&r"(data32) : "0"(data32) :);
#endif
return data32;
}
static inline u32 reverse_u16(u16 data16)
{
u32 retv;
#if 0
u8 *dataptr = (u8 *)(&data16);
retv = (((u32)dataptr[0] << 8) | ((u32)dataptr[1]));
#else
retv = ((u32)data16) << 16;
__asm__ volatile("%0 = rev8(%0) \t\n" : "=&r"(retv) : "0"(retv) :);
#endif
return retv;
}
static inline u32 rand32()
{
return JL_RAND->R64L;
}
#define __asm_sine(s64, precision) \
({ \
u64 ret; \
u8 sel = 0; \
__asm__ volatile ("%0 = copex(%1) (%2)" : "=r"(ret) : "r"(s64), "i"(sel)); \
ret = ret>>32; \
ret;\
})
void p33_soft_reset(void);
static inline void cpu_reset(void)
{
// JL_CLOCK->PWR_CON |= (1 << 4);
p33_soft_reset();
}
#define __asm_csync() \
do { \
asm volatile("csync;"); \
} while (0)
#include "irq.h"
#include "printf.h"
#include "log.h"
#define arch_atomic_read(v) \
({ \
__asm_csync(); \
(*(volatile int *)&(v)->counter); \
})
#if 0
extern volatile int cpu_lock_cnt[];
extern volatile int irq_lock_cnt[];
static inline void local_irq_disable()
{
__builtin_pi32v2_cli();
irq_lock_cnt[current_cpu_id()]++;
}
static inline void local_irq_enable()
{
if (--irq_lock_cnt[current_cpu_id()] == 0) {
__builtin_pi32v2_sti();
}
}
#else
extern void __local_irq_disable() ;
extern void __local_irq_enable() ;
extern void local_irq_disable();
extern void local_irq_enable();
#endif
#if(0 )
#define arch_spin_trylock(lock) \
do { \
__asm_csync(); \
while ((lock)->rwlock); \
(lock)->rwlock = 1; \
}while(0)
#define arch_spin_lock(lock) \
do { \
int ret = false; \
__asm_csync(); \
if (!(lock)->rwlock) { \
ret = true; \
(lock)->rwlock = 1; \
} \
if (ret) \
break; \
}while(1)
#define arch_spin_unlock(lock) \
do { \
(lock)->rwlock = 0; \
}while(0)
#else
static inline void q32DSP_testset(u32 volatile *ptr)
{
asm volatile(
" 1: \n\t "
" testset b[%0] \n\t "
" ifeq goto 1b \n\t "
:
: "p"(ptr)
: "memory"
);
}
static inline void q32DSP_testclr(u32 volatile *ptr)
{
asm volatile(
" b[%0] = %1 \n\t "
:
: "p"(ptr), "r"(0)
: "memory"
);
}
#define arch_spin_trylock(lock) \
do { \
q32DSP_testset(&lock->rwlock);\
}while(0)
#define arch_spin_lock(lock) arch_spin_trylock(lock)
#define arch_spin_unlock(lock) \
do{ \
q32DSP_testclr(&lock->rwlock) ;\
}while(0)
#endif
#if 1 // CPU_CORE_NUM >1
extern volatile int cpu_lock_cnt[];
extern volatile int irq_lock_cnt[];
#if 0
#define CPU_SR_ALLOC() \
// int flags
#define CPU_CRITICAL_ENTER() \
do { extern u8 volatile cpulock;\
local_irq_disable(); \
if(cpu_lock_cnt[current_cpu_id()]++ == 0) \
q32DSP_testset(&cpulock);\
__asm_csync(); \
}while(0)
// asm volatile("lockset;");
#define CPU_CRITICAL_EXIT() \
do {extern u8 volatile cpulock; \
if (--cpu_lock_cnt[current_cpu_id()] == 0) \
q32DSP_testclr(&cpulock);\
local_irq_enable();\
}while(0)
#endif
static inline int get_random()
{
return JL_RAND->R64L;
}
#define OS_SR_ALLOC()
#define OS_ENTER_CRITICAL() \
CPU_CRITICAL_ENTER(); \
#define OS_EXIT_CRITICAL() \
CPU_CRITICAL_EXIT()
#define CPU_SR_ALLOC() \
// int flags
#define CPU_CRITICAL_ENTER() \
do { \
local_irq_disable(); \
}while(0)
#define CPU_CRITICAL_EXIT() \
do { \
local_irq_enable(); \
}while(0)
// asm volatile("lockclr;");
#else
#define CPU_SR_ALLOC() \
// int flags
#define CPU_CRITICAL_ENTER() \
do { \
local_irq_disable(); \
__asm_csync(); \
}while(0)
#define CPU_CRITICAL_EXIT() \
do { \
local_irq_enable(); \
}while(0)
#endif
extern void cpu_assert_debug();
extern const int config_asser;
#define ASSERT(a,...) \
do { \
if(1 /* config_asser */){\
if(!(a)){ \
printf("cpu %d file:%s, line:%d",current_cpu_id(), __FILE__, __LINE__); \
printf("ASSERT-FAILD: "#a" "__VA_ARGS__); \
cpu_assert_debug(); \
} \
}else {\
if(!(a)){ \
cpu_reset(); \
}\
}\
}while(0);
#endif //__ASSEMBLY__
#endif
loader/ble_app_ota_update/include_lib/system/cpu/br35/asm/exception.h
+71
View File
@@ -0,0 +1,71 @@
#ifndef __DEBUG_H__
#define __DEBUG_H__
#define CDBG_IDx(n, id) ((1<<(n+4)) | (id<<(n*8+8)))
#define CDBG_INV (1<<7)
#define CDBG_PEN (1<<3)
#define CDBG_XEN (1<<2)
#define CDBG_WEN (1<<1)
#define CDBG_REN (1<<0)
void debug_init();
void exception_analyze();
/********************************** DUBUG SFR *****************************************/
u32 get_dev_id(char *name);
/* ---------------------------------------------------------------------------- */
/**
* @brief Memory权限保护设置
*
* @param idx: 保护框索引, 范围: 0 ~ 3, 目前系统默认使用0和3, 用户可用1和2
* @param begin: Memory开始地址
* @param end: Memory结束地址
* @param inv: 0: 保护框内, 1: 保护框外
* @param format: "Cxwr0rw1rw2rw3rw", CPU:外设0:外设1:外设2:外设3,
* @param ...: 外设ID号索引, 如: DBG_EQ, 见debug.h
*/
/* ---------------------------------------------------------------------------- */
void mpu_set(int idx, u32 begin, u32 end, u32 inv, const char *format, ...);
/* ---------------------------------------------------------------------------- */
/**
* @brief 取消指定框的mpu保护
*
* @param idx: 保护框索引号
*/
/* ---------------------------------------------------------------------------- */
void mpu_disable_by_index(u8 idx);
/* ---------------------------------------------------------------------------- */
/**
* @brief :取消所有保护框mpu保护
*/
/* ---------------------------------------------------------------------------- */
void mpu_diasble(void);
/* ---------------------------------------------------------------------------- */
/**
* @brief flash PC范围设置为Flash外区域, 调用该接口后调用flash里的函数将触发异常
*/
/* ---------------------------------------------------------------------------- */
void flash_pc_limit_disable();
/* ---------------------------------------------------------------------------- */
/**
* @brief flash PC范围限制恢复为flash代码区域, 调用该接口后可调用flash里的函数
*/
/* ---------------------------------------------------------------------------- */
void flash_pc_limit_enable();
#endif
loader/ble_app_ota_update/include_lib/system/fs/lite_file_sys/diskio.h
+70
View File
@@ -0,0 +1,70 @@
/*-----------------------------------------------------------------------
/ Low level disk interface modlue include file R0.06 (C)ChaN, 2007
/-----------------------------------------------------------------------*/
#ifndef _DISKIO
// #include "logic_include.h"
//#ifdef __ICC8051__
/* Status of Disk Functions */
typedef u8 DSTATUS;
/* Results of Disk Functions */
typedef enum {
RES_OK = 0, /* 0: Successful */
RES_ERROR, /* 1: R/W Error */
RES_WRPRT, /* 2: Write Protected */
RES_NOTRDY, /* 3: Not Ready */
RES_PARERR /* 4: Invalid Parameter */
} DRESULT;
///#endif
/*---------------------------------------*/
/* Prototypes for disk control functions */
//DSTATUS disk_initialize (BYTE);
//DSTATUS disk_status (BYTE);
//DRESULT disk_read (BYTE, BYTE*, DWORD, BYTE);
//#if _READONLY == 0
//DRESULT disk_write (BYTE, const BYTE*, DWORD, BYTE);
//#endif
//DRESULT disk_ioctl (BYTE, BYTE, void*);
//void disk_timerproc (void);
#define _READONLY 0 /* 1: Read-only mode */
#define _USE_IOCTL 1
/* Disk Status Bits (DSTATUS) */
#define STA_NOINIT 0x01 /* Drive not initialized */
#define STA_NODISK 0x02 /* No medium in the drive */
#define STA_PROTECT 0x04 /* Write protected */
/* Command code for disk_ioctrl() */
/* Generic command */
#define CTRL_SYNC 0 /* Mandatory for read/write configuration */
#define GET_SECTOR_COUNT 1 /* Mandatory for only f_mkfs() */
#define GET_SECTOR_SIZE 2
#define GET_BLOCK_SIZE 3 /* Mandatory for only f_mkfs() */
#define CTRL_POWER 4
#define CTRL_LOCK 5
#define CTRL_EJECT 6
/* MMC/SDC command */
#define MMC_GET_TYPE 10
#define MMC_GET_CSD 11
#define MMC_GET_CID 12
#define MMC_GET_OCR 13
#define MMC_GET_SDSTAT 14
/* ATA/CF command */
#define ATA_GET_REV 20
#define ATA_GET_MODEL 21
#define ATA_GET_SN 22
#define _DISKIO
#endif
loader/ble_app_ota_update/include_lib/system/fs/lite_file_sys/tff.h
+448
View File
@@ -0,0 +1,448 @@
#ifndef _FATFS_H
#define _FATFS_H
#include "common.h"
#include "diskio.h"
// #include "logic_include.h"
#define MAX_DEEPTH 2 /* 0~9 deepth of system */
#define LFN_MAX_SIZE 512 //不能超过512
/*******************************************************/
/********************驱动调试信息***********************/
/*******************************************************/
//#define FS_DEBUG
#ifdef FS_DEBUG
#define fs_deg printf
#define fs_deg_puts printf
#define fs_deg_buf printf_buf
#define fs_deg_data printf_data
#else
#define fs_deg(...)
#define fs_deg_puts(...)
#define fs_deg_buf(...)
#define fs_deg_data(...)
#endif
#define FS_LD_WORD(p) ld_word_func(p)//(u16)(*(u16*)(u8*)(ptr))
#define FS_LD_DWORD(p) ld_dword_func(p)//(u32)(*(u32*)(u8*)(ptr))
#define FS_ST_WORD(ptr,val) st_word_func((u8 *)(ptr),(u16)(val)) //(u16)(*(u16*)(u8*)(ptr))
#define FS_ST_DWORD(ptr,val) st_dword_func((u8 *)(ptr),(u32)(val)) //(u32)(*(u32*)(u8*)(ptr))
typedef u32 CLUST;
#define FS_WRITE_EN /* 是否允许写文件 */
#ifdef FS_WRITE_EN
#define FAT12_WRITE_EN
//#define EXFAT_WRITE_EN
#endif
#define WIN_DATA_DIRTY 0x08
/* File system API info */
typedef struct _FSAPIMSG {
u16 musicdir_counter; // 包含指定文件的文件夹序号
u16 dir_counter; // 文件夹序号
u16 file_total_indir; // 当前目录的根下有效文件的个数
u16 file_total_outdir; // 当前目录前的文件总数，目录循环模式下，需要用它来计算文件序号
u16 file_number; // 当前文件序号
u16 file_counter; //用于搜索文件计数
u8 deepth; // dir deepth for search
} FSAPIMSG;
typedef struct _SWIN_BUF {
u8 start[512];
u32 sector;
struct _FATFS *fs;
u8 flag;
} SWIN_BUF;
/*
#define FS_WIN_START fs->win->start
#define FS_WIN_SECTOR fs->win->sector
#define FS_WIN_FLAG fs->win->flag
*/
#define FS_WIN_START fs->win.start
#define FS_WIN_SECTOR fs->win.sector
#define FS_WIN_FLAG fs->win.flag
/* File system object structure */
struct _FATFS {
//SWIN_BUF *win; /* Disk access window for Directory/FAT/File */
u32 fatbase; /* FAT start sector */
u32 dirbase; /* Root directory start sector */
u32 database; /* Data start sector */
u32 n_fatent; /* Maximum cluster# + 1 */
#ifdef FS_WRITE_EN
u8 write_en; //文件系统是否允许写操作：只允许FAT16，FAT32并且sector size只能是512bytes
u8 fsi_flag; /* fsinfo dirty flag (1:must be written back) */
u32 last_clust; /* Last allocated cluster */
u32 fsi_sector; /* fsinfo sector (FAT32) */
#endif
u32 boot_sect;
u16 n_rootdir; /* Number of root directory entries */
u16 total_file; /* 当前设备的匹配文件总数*/
u8 s_size; /* sector size, 2 power n*/
u8 csize; /* Number of sectors per cluster,2 power n */
u8 fs_type; /* FAT sub type */
u8 secotr_512size; /* size of per sector */
u32(*disk_read)(u8 *buf, u32 lba); /* device read function */
u32(*disk_write)(u8 *buf, u32 lba); /* device write function */
u32 fat_time;
// u8 *lfn; //长文件名buffer
// u16 lfn_cnt;
// char *tpath; //路径名称buffer
void *hdev;
SWIN_BUF win; /* Disk access window for Directory/FAT/File */
u8 drive_cnt;
//FSAPIMSG *fs_msg;
};
typedef struct _FATFS FATFS;
struct _FS_NAME {
char tpath[128]; //路径名称buffer
char *lfn; //长文件名buffer
u16 lfn_cnt;
};
typedef struct _FS_NAME FS_NAME;
typedef u32(*disk_read)(u8 *buf, u32 lba);
typedef u32(*disk_write)(u8 *buf, u32 lba);
/* Directory object structure */
typedef struct _DIR {
u32 clust; /* Current cluster */
u32 csect; /* Current sector */
u32 sclust; /* Start cluster */
u16 cindex; /* Current index */
//u16 lfn_index; /* 长文件名index号 */
} DIR;
/* DIR status structure */
typedef struct _DIRINFO {
DIR dj;
u32 sclust; /* File start cluster */
u32 fsize; /* Size */
u8 fattrib; /* Attribute */
char fname[12]; /* */
} DIRINFO;
/* File object structure */
/*
typedef struct _FIL
{
u32 fptr; // File R/W pointer
//u32 fsize; // File size
u8 flag;
SWIN_BUF *data_win;
u32 csect; // Current sector
u32 clust; // Current cluster
//u32 sclust; // File start cluster
#ifdef FS_WRITE_EN
SWIN_BUF *dir_win;
u8 dir_duty;
#endif
u32 start_clust;
u32 end_clust;
FATFS *fs;
DIRINFO dir_info; //文件的目录项信息
FSAPIMSG fs_msg;
} FIL;
*/
typedef struct _FIL0 {
u32 fptr; // File R/W pointer
//u32 fsize; // File size
u8 flag;
SWIN_BUF data_win;
u32 csect; // Current sector
u32 clust; // Current cluster
//u32 sclust; // File start cluster
#ifdef FS_WRITE_EN
SWIN_BUF dir_win;
u8 dir_duty;
#endif
u32 start_clust;
u32 end_clust;
FATFS *fs;
} FIL0;
typedef struct _FIL {
FIL0 fil;
DIRINFO dir_info; //文件的目录项信息
FSAPIMSG fs_msg;
//u8 filename[512];///<[1][512];
//u8 path_name[128];///<128
DIR f_dj[MAX_DEEPTH];
FS_NAME fs_n;
} FIL;
typedef struct _LDIR_INFO {
u8 ldir_ord;
u8 ldir_name1[10]; //文件的目录项信息
u8 ldir_attr0;
u8 ldir_type0;
u8 ldir_chksum0;
u8 ldir_name2[12];
u16 ldir_fst_clus_lo;
u8 ldir_name3[4];
} LDIR_INFO;
/* File access control and file status flags (FIL.flag) */
#define FA_OPEN_EXISTING 0x00
#ifdef FS_WRITE_EN
#define FA_CREATE_HIDDEN 0x02
#define FA_WRITE 0x04 //是否允许写文件
#define FA_CREATE_NEW 0x08 //文件不存在时创建
#define FA_CREATE_ALWAYS 0x10 //无论文件中否存在，均创建
#endif
#define FA__ERROR 0x80 //文件错误
#define FDISK__ERROR 0x40 //设备错误
#define DDE 0xE5 /* Deleted directory entry mark in DIR_Name[0] */
#define NDDE 0x05 /* Replacement of the character collides with DDE */
#define SZ_DIR 32
//#ifdef __SMART_CPU__
//#endif
/* File function return code (FRESULT) */
#define _DF1S 1
/* Character code support macros */
#define IsUpper(c) (((c)>='A')&&((c)<='Z'))
#define IsLower(c) (((c)>='a')&&((c)<='z'))
#if _DF1S /* DBCS configuration */
#ifdef _DF2S /* Two 1st byte areas */
#define IsDBCS1(c) (((u8)(c) >= _DF1S && (u8)(c) <= _DF1E) || ((u8)(c) >= _DF2S && (u8)(c) <= _DF2E))
#else /* One 1st byte area */
//#define IsDBCS1(c) ((u8)(c) >= _DF1S && (u8)(c) <= _DF1E)
#define IsDBCS1(c) ((u8)(c) < ' ' && (u8)(c) > '~')
#endif
#ifdef _DS3S /* Three 2nd byte areas */
#define IsDBCS2(c) (((u8)(c) >= _DS1S && (u8)(c) <= _DS1E) || ((u8)(c) >= _DS2S && (u8)(c) <= _DS2E) || ((u8)(c) >= _DS3S && (u8)(c) <= _DS3E))
#else /* Two 2nd byte areas */
#define IsDBCS2(c) (((u8)(c) >= _DS1S && (u8)(c) <= _DS1E) || ((u8)(c) >= _DS2S && (u8)(c) <= _DS2E))
#endif
#else /* SBCS configuration */
#define IsDBCS1(c) 0
#define IsDBCS2(c) 0
#endif /* _DF1S */
/* FAT sub-type boundaries */
/* Note that the FAT spec by Microsoft says 4085 but Windows works with 4087! */
#define MIN_FAT16 4086 /* Minimum number of clusters for FAT16 */
#define MIN_FAT32 65526 /* Minimum number of clusters for FAT32 */
#define ROOT_DIR 0
/* FAT sub type */
#define FS_FAT12 1
#define FS_FAT16 2
#define FS_FAT32 3
#define FS_EXFAT 4
/* File attribute bits for directory entry */
#define AM_RDO 0x01 /* Read only */
#define AM_HID 0x02 /* Hidden */
#define AM_SYS 0x04 /* System */
#define AM_VOL 0x08 /* Volume label */
#define AM_LFN 0x0F /* LFN entry */
#define AM_DIR 0x10 /* Directory */
#define AM_ARC 0x20 /* Archive */
#define AM_FCH 0x80 /* exFAT下,文件簇连续标志 */
/* Offset of FAT structure members */
#define BS_jmpBoot 0
#define BS_OEMName 3
#define BPB_BytsPerSec_l 11
#define BPB_BytsPerSec_h 12
#define BPB_SecPerClus 13
#define BPB_RsvdSecCnt 14
#define BPB_NumFATs 16
#define BPB_RootEntCnt 17
#define BPB_TotSec16 19
#define BPB_Media 21
#define BPB_FATSz16 22
#define BPB_SecPerTrk 24
#define BPB_NumHeads 26
#define BPB_HiddSec 28
#define BPB_TotSec32 32
#define BS_55AA 510
#define BS_DrvNum 36
#define BS_BootSig 38
#define BS_VolID 39
#define BS_VolLab 43
#define BS_FilSysType 54
#define BPB_FATSz32 36
#define BPB_ExtFlags 40
#define BPB_FSVer 42
#define BPB_RootClus 44
#define BPB_FSInfo 48
#define BPB_BkBootSec 50
#define BS_DrvNum32 64
#define BS_BootSig32 66
#define BS_VolID32 67
#define BS_VolLab32 71
#define BS_FilSysType32 82
#define BS_FileSysTypeexFAT 5
#define BPB_FatOffset 80
#define BPB_FatLength 84
#define BPB_ClusterHeapOffset 88
#define BPB_ClusterCount 92
#define BPB_FirstClusterOfRootDirectory 96
#define BPB_VolumeFlags 106
#define BPB_BytesPerSectorShift 108
#define BPB_SectorsPerClusterShift 109
#define BPB_NumberOfFats 110
#define MBR_Table 446
#define FSI_LeadSig 0 /* FSI: Leading signature (4) */
#define FSI_StrucSig 484 /* FSI: Structure signature (4) */
#define FSI_Free_Count 488 /* FSI: Number of free clusters (4) */
#define FSI_Nxt_Free 492 /* FSI: Last allocated cluster (4) */
///for FAT12/FAT16/FAT32
#define DIR_Name 0 /* Short file name (11) */
#define DIR_Attr 11 /* Attribute (1) */
#define DIR_NTres 12 /* NT flag (1) */
#define DIR_CrtTimeTenth 13 /* Created time sub-second (1) */
#define DIR_CrtTime 14 /* Created time (2) */
#define DIR_CrtDate 16 /* Created date (2) */
#define DIR_LstAccDate 18 /* Last accessed date (2) */
#define DIR_FstClusHI 20 /* Higher 16-bit of first cluster (2) */
#define DIR_WrtTime 22 /* Modified time (2) */
#define DIR_WrtDate 24 /* Modified date (2) */
#define DIR_FstClusLO 26
#define DIR_FileSize 28
#define LDIR_Attr 11 /* LFN attribute (1) */
#define LDIR_Type 12 /* LFN type (1) */
#define LDIR_Chksum 13 /* Sum of corresponding SFN entry */
////for exFAT
#define DIR_FileChainFlags 1
#define DIR_NameLen 3
#define DIR_AttrexFAT 4
#define DIR_FileSizeexFAT 8
#define DIR_FstClustexFAT 20
enum {
SEEK_SET = 0x01,
SEEK_CUR = 0x02,
SEEK_END = 0x03
};
typedef enum {
FR_OK = 0,
FR_FIND_DIR = 0x80,
FR_FIND_FILE,
FR_DIR_END, //前面几个位置不能变
FR_NO_FILE,
FR_NO_PATH,
FR_EXIST,
FR_INVALID_NAME,
FR_INVALID_DRIVE,
FR_DENIED,
FR_RW_ERROR,
FR_WRITE_PROTECTED,
FR_NO_FILESYSTEM,
FR_DEEP_LIMIT,
FR_END_PATH,
FR_FILE_LIMIT,
FR_END_FILE,
FR_LFN_ERR,
FR_MKFS_ABORTED,
FR_DIR_DELETE,
FR_DISK_ERROR,
FR_FILE_END,
FR_FILE_ERR,
FR_NO_WINBUF,
FR_INT_ERR, /* (2) Assertion failed */
FR_NO_SEL_DRIVE,
} FRESULT;
/*-----------------------------------------------------*/
/* Tiny-FatFs module application interface */
FRESULT f_seek(FIL *fp, u8 type, u32 offsize);
u16 f_read(FIL *fp, u8 *buff, u16 btr);
u32 f_read_bt_updata(FIL *fp, u8 *buff, u32 btr, u8 read_type, u8 type, u32 offsize);
FRESULT f_readnextdir(FATFS *fs, DIR *dj, DIRINFO *dinfo, FS_NAME *fs_n);
void f_opendir(FATFS *fs, DIR *dj) ;
FRESULT f_mount(FATFS *fs, u32 bootsect, char drive_sel) ;
FRESULT f_mount_api(FATFS *fs, u32 bootsect, char drive_sel);
FRESULT f_open(FATFS *fs, FIL *fp, char *path, char *lfn_buf, u8 mode);
u8 f_tell_status(FIL *fp);
u16 f_write(FIL *fp, u8 *buff, u16 btw);
FRESULT f_mkdir(FATFS *fs, char *path, u8 mode);
FRESULT f_sync_fs(FIL *fp);
FRESULT f_sync_file(FIL *fp);
FRESULT f_unlink(FIL *fp);
bool path_mem_cmp(char *src, char *dst, u8 len);
bool my_mem_cmp(char *src, char *dst, u8 len);
u8 get_powerof2(u8 n);
u32 clust2sect(FATFS *fs, u32 clust);
void st_clust(u8 *dir, u32 cl);
FRESULT sync_window(SWIN_BUF *win_buf);
FRESULT move_window(u32 sector, SWIN_BUF *win_buf);
u32 get_fat(FATFS *fs, u32 clust, SWIN_BUF *win_buf);
u32 get_cluster(FIL *fp, u32 clust, SWIN_BUF *win_buf);
FRESULT put_fat(FATFS *fs, u32 clst, u32 val, SWIN_BUF *win_buf);
u32 ld_clust(FATFS *fs, u8 *dir);
bool dir_sdi(FATFS *fs, DIR *dj, u16 idx);
FRESULT dir_alloc(FATFS *fs, DIR *dj, u8 nent);
FRESULT dir_register(FATFS *fs, DIR *dj, char *fn);
FRESULT sync_fs(FATFS *fs);
u8 create_name(char *sfn, const char *path);
FRESULT dir_find(FATFS *fs, DIR *dj, DIRINFO *dir_info, char *sfn, FS_NAME *lfn);
FRESULT follow_path(FATFS *fs, DIR *dj, char *sfn, DIRINFO *dinfo, char *path, FS_NAME *lfn);
FRESULT remove_chain(FATFS *fs, u32 clst);
u32 create_chain(FATFS *fs, u32 clst, SWIN_BUF *win);
FRESULT check_fs(FATFS *fs, u32 sec);
void get_dir_info(const u8 *dir, DIRINFO *dinfo);
bool dir_next(FATFS *fs, DIR *dj, bool stretch);
u16 ld_word_func(u8 *p);
u32 ld_dword_func(u8 *p);
void st_word_func(u8 *ptr, u16 val);
void st_dword_func(u8 *ptr, u32 val);
bool decode_lfn(char *p, char *sou_p, u16 max_copy);
#endif /* _FATFS */
loader/ble_app_ota_update/include_lib/system/generic/circular_buf.h
+53
View File
@@ -0,0 +1,53 @@
#ifndef CIRCULAR_BUF_INTERFACE_H
#define CIRCULAR_BUF_INTERFACE_H
#include "typedef.h"
typedef struct _cbuffer {
u8 *begin;
u8 *end;
u8 *read_ptr;
u8 *write_ptr;
u8 *tmp_ptr ;
u32 tmp_len;
u32 data_len;
u32 total_len;
} cbuffer_t;
extern void cbuf_init(cbuffer_t *cbuffer, void *buf, u32 size);
extern u32 cbuf_read(cbuffer_t *cbuffer, void *buf, u32 len);
extern u32 cbuf_write(cbuffer_t *cbuffer, void *buf, u32 len);
extern u32 cbuf_is_write_able(cbuffer_t *cbuffer, u32 len);
extern void *cbuf_write_alloc(cbuffer_t *cbuffer, u32 *len);
extern void cbuf_write_updata(cbuffer_t *cbuffer, u32 len);
void *cbuf_read_alloc(cbuffer_t *cbuffer, u32 *len);
void cbuf_read_updata(cbuffer_t *cbuffer, u32 len);
void cbuf_clear(cbuffer_t *cbuffer);
u32 cbuf_rewrite(cbuffer_t *cbuffer, void *begin, void *buf, u32 len);
void cbuf_discard_prewrite(cbuffer_t *cbuffer);
void cbuf_updata_prewrite(cbuffer_t *cbuffer);
u32 cbuf_prewrite(cbuffer_t *cbuffer, void *buf, u32 len);
u32 cbuf_get_data_size(cbuffer_t *cbuffer);
void cbuf_read_alloc_len_updata(cbuffer_t *cbuffer, u32 len);
u32 cbuf_read_alloc_len(cbuffer_t *cbuffer, void *buf, u32 len);
#define cbuf_get_writeptr(a) (a)->write_ptr
#define cbuf_get_readptr(a ) (a)->read_ptr
#endif
loader/ble_app_ota_update/include_lib/system/generic/common.h
+42
View File
@@ -0,0 +1,42 @@
#ifndef __COMMON_H__
#define __COMMON_H__
#include "asm/cpu.h"
#include "csfr.h"
#include "typedef.h"
#include "device_errno.h"
#include "wdt.h"
//#include "printf.h"
#define SFR(sfr, start, len, dat) (sfr = (sfr & ~((~(0xffffffff << (len))) << (start))) | (((dat) & (~(0xffffffff << (len)))) << (start)))
#ifndef MIN
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#endif
#ifndef MAX
#define MAX(a, b) ((a) > (b) ? (a) : (b))
#endif
#ifdef __DEBUG
#define APP_DEBUG 1
#else
#define APP_DEBUG 0
#endif
// #if APP_DEBUG
// #define log_info printf
// #define log_error(...)
// #define log_info_hexdump printf_buf
// #else
// #define log_info(...)
// #define log_info_hexdump(a,b)
// #endif
// void wdt_clear();
#endif
loader/ble_app_ota_update/include_lib/system/generic/debug.h
+109
View File
@@ -0,0 +1,109 @@
#ifndef _DEBUG_H_
#define _DEBUG_H_
#include "printf.h"
#include "asm/cpu.h"
#include "generic/typedef.h"
#define RedBold "\033[31;1m" // 红色加粗
#define RedBoldBlink "\033[31;1;5m" // 红色加粗、闪烁
#define GreenBold "\033[32;1m" // 红色加粗
#define GreenBoldBlink "\033[32;1;5m" // 红色加粗、闪烁
#define YellowBold "\033[33;1m" // 红色加粗
#define YellowBoldBlink "\033[33;1;5m" // 红色加粗、闪烁
#define BlueBold "\033[34;1m" // 蓝色加粗
#define BlueBoldBlink "\033[34;1;5m" // 蓝色加粗、闪烁
#define PurpleBold "\033[35;1m" // 紫色加粗
#define PurpleBoldBlink "\033[35;1;5m" // 紫色加粗、闪烁
#define DGreenBold "\033[36;1m" // 红色加粗
#define DGreenBoldBlink "\033[36;1;5m" // 红色加粗、闪烁
#define WhiteBold "\033[37;1m" // 红色加粗
#define WhiteBoldBlink "\033[37;1;5m" // 红色加粗、闪烁
#define Reset "\033[0;25m" // 颜色复位
#define LOG_VERBOSE v
#define LOG_INFO i
#define LOG_DEBUG d
#define LOG_WARN w
#define LOG_ERROR e
#define LOG_CHAR c
#define _STR(x) #x
#define STR(x) "["_STR(x)"]"
#define _LOG_TAG_CONST_DECLARE(level, name) extern const char log_tag_const_##level##_##name
#define LOG_TAG_CONST_DECLARE(level, name) _LOG_TAG_CONST_DECLARE(level, name)
#define ___LOG_IS_ENABLE(level, name) (log_tag_const_##level##_##name)
#define __LOG_IS_ENABLE(level, name) ___LOG_IS_ENABLE(level, name)
#define _LOG_IS_ENABLE(level) __LOG_IS_ENABLE(level, LOG_TAG_CONST)
#ifdef LOG_TAG_CONST
LOG_TAG_CONST_DECLARE(LOG_VERBOSE, LOG_TAG_CONST);
LOG_TAG_CONST_DECLARE(LOG_INFO, LOG_TAG_CONST);
LOG_TAG_CONST_DECLARE(LOG_DEBUG, LOG_TAG_CONST);
LOG_TAG_CONST_DECLARE(LOG_WARN, LOG_TAG_CONST);
LOG_TAG_CONST_DECLARE(LOG_ERROR, LOG_TAG_CONST);
LOG_TAG_CONST_DECLARE(LOG_CHAR, LOG_TAG_CONST);
#define _LOG_TAG LOG_TAG
#define LOG_IS_ENABLE(level) _LOG_IS_ENABLE(level)
#else
#define _LOG_TAG "[NULL]"
#define LOG_IS_ENABLE(x) 0
#endif
#ifdef __DEBUG
#define log_print printf
#define log_info(format, ...) \
if (LOG_IS_ENABLE(LOG_INFO)) \
log_print("[Info] " _LOG_TAG format "\r\n", ## __VA_ARGS__)
#define log_info_hexdump(x, y) \
if (LOG_IS_ENABLE(LOG_INFO)) \
printf_buf(x, y)
#define log_debug(format, ...) \
if (LOG_IS_ENABLE(LOG_DEBUG)) \
log_print("[Debug] " _LOG_TAG format "\r\n", ## __VA_ARGS__)
#define log_debug_hexdump(x, y) \
if (LOG_IS_ENABLE(LOG_DEBUG)) \
printf_buf(x, y)
#define log_error(format, ...) \
if (LOG_IS_ENABLE(LOG_ERROR)) \
log_print("<Error> " _LOG_TAG format "\r\n", ## __VA_ARGS__)
#define log_error_hexdump(x, y) \
if (LOG_IS_ENABLE(LOG_ERROR)) \
printf_buf(x, y)
#define log_char(x) \
if (LOG_IS_ENABLE(LOG_CHAR)) \
putchar(x)
#else
#define log_info(format, ...)
#define log_info_hexdump(x, y)
#define log_debug(format, ...)
#define log_debug_hexdump(x, y)
#define log_error(format, ...)
#define log_error_hexdump(x, y)
#define log_char(x)
#endif
int printf_lite(const char *format, ...);
void log_putbyte(char c);
void put_buf_lite(void *_buf, u32 len);
#endif//__DEBUG_H_
loader/ble_app_ota_update/include_lib/system/generic/errno-base.h
+41
View File
@@ -0,0 +1,41 @@
#ifndef _ASM_GENERIC_ERRNO_BASE_H
#define _ASM_GENERIC_ERRNO_BASE_H
#define EPERM 1 /* Operation not permitted */
#define ENOENT 2 /* No such file or directory */
#define ESRCH 3 /* No such process */
#define EINTR 4 /* Interrupted system call */
#define EIO 5 /* I/O error */
#define ENXIO 6 /* No such device or address */
#define E2BIG 7 /* Argument list too long */
#define ENOEXEC 8 /* Exec format error */
#define EBADF 9 /* Bad file number */
#define ECHILD 10 /* No child processes */
#define EAGAIN 11 /* Try again */
#define ENOMEM 12 /* Out of memory */
#define EACCES 13 /* Permission denied */
#define EFAULT 14 /* Bad address */
#define ENOTBLK 15 /* Block device required */
#define EBUSY 16 /* Device or resource busy */
#define EEXIST 17 /* File exists */
#define EXDEV 18 /* Cross-device link */
#define ENODEV 19 /* No such device */
#define ENOTDIR 20 /* Not a directory */
#define EISDIR 21 /* Is a directory */
#define EINVAL 22 /* Invalid argument */
#define ENFILE 23 /* File table overflow */
#define EMFILE 24 /* Too many open files */
#define ENOTTY 25 /* Not a typewriter */
#define ETXTBSY 26 /* Text file busy */
#define EFBIG 27 /* File too large */
#define ENOSPC 28 /* No space left on device */
#define ESPIPE 29 /* Illegal seek */
#define EROFS 30 /* Read-only file system */
#define EMLINK 31 /* Too many links */
#define EPIPE 32 /* Broken pipe */
#define EDOM 33 /* Math argument out of domain of func */
#define ERANGE 34 /* Math result not representable */
#define ETIMEDOUT 35 /* Connection timed out */
#endif
loader/ble_app_ota_update/include_lib/system/generic/jiffies.h
+35
View File
@@ -0,0 +1,35 @@
#ifndef JIFFIES_H
#define JIFFIES_H
#define HZ 100L
#define MSEC_PER_SEC 1000L
#define USEC_PER_MSEC 1000L
#define NSEC_PER_USEC 1000L
#define NSEC_PER_MSEC 1000000L
#define USEC_PER_SEC 1000000L
#define NSEC_PER_SEC 1000000000L
#define FSEC_PER_SEC 1000000000000000LL
#ifndef __ASSEMBLY__
extern volatile unsigned long jiffies;
extern unsigned long jiffies_msec();
extern unsigned long jiffies_half_msec();
#endif
#define maskrom_get_jiffies() jiffies
#define maskrom_set_jiffies(n) jiffies = n
#define JIFFIES_CIRCLE 0x7FFFFFF
#define msecs_to_jiffies_10(msec) ((msec)/10)
#define jiffies_to_msecs(jiff) ((jiff)*10)
#define msecs_to_jiffies(msec) ((msec)/10)
#define time_after(a,b) ((long)(b) - (long)(a) <= 0)
#define time_before(a,b) time_after(b, a)
int jiffies_msec2offset(unsigned long begin_msec, unsigned long end_msec);
#endif
loader/ble_app_ota_update/include_lib/system/generic/lbuf.h
+225
View File
@@ -0,0 +1,225 @@
#ifndef LBUF_H
#define LBUF_H
#include "typedef.h"
#include "list.h"
#include "spinlock.h"
#define LBUF_DEBUG 0
struct lbuff_head {
#if LBUF_DEBUG
int magic_a; /*!< 测试验证变量*/
#endif
struct list_head head; /*!< 指向hentry链表*/
struct list_head free; /*!< 指向hfree链表*/
spinlock_t lock; /*!< 混合自旋锁,单核是为开关临界区,多核是自旋锁.*/
u8 align; /*!< 数据包字节对齐*/
u16 priv_len; /*!< 数据包结构体的最小长度*/
u32 total_size; /*!< 总大小*/
u32 last_addr; /*!< 指向free链表中找到的足够长度的hfree结构体地址*/
void *priv;
#if LBUF_DEBUG
int magic_b; /*!< 测试验证变量*/
#endif
};
struct lbuff_state {
u32 avaliable; /*!< 剩余空间的字节长度*/
u32 fragment; /*!< lbuf内存碎片块数量*/
u32 max_continue_len; /*!< 最大的剩余内存块的字节长度*/
int num; /*!< 剩余内存块数量*/
};
/* --------------------------------------------------------------------------*/
/**
* @brief 链表buf初始化
*
* @param [in] buf 需要lbuf进行管理的内存
* @param [in] len 内存长度
* @param [in] align 输入对管理的内存进行对齐的参数,避免后续使用因地址不对齐产生碎片
* @param [in] priv_head_len 要管理的一个数据包结构体的最小的长度
*
* @return lbuf操作句柄
*/
/* --------------------------------------------------------------------------*/
struct lbuff_head *lbuf_init(void *buf, u32 len, int align, int priv_head_len);
/* --------------------------------------------------------------------------*/
/**
* @brief 分配内存空间进行存储数据包
*
* @param [in] head lbuf操作句柄
* @param [in] len 需要存入的数据包的长度
*
* @return 成功则返回进行存储数据包的地址,调用时候需要用户把该块内存的类型初始化为数据包结构体的类型。失败则返回NULL。
*/
/* --------------------------------------------------------------------------*/
void *lbuf_alloc(struct lbuff_head *head, u32 len);
/* --------------------------------------------------------------------------*/
/**
* @brief 重新分配lbuf_alloc()返回用于存储数据包的lbuf空间
*
* @param [in] lbuf lbuf_alloc()返回用于存储数据包的地址
* @param [in] size 需重新分配的空间的字节长度.注:size的大小只能比lbuf_alloc()中的len小,即只能重新分配更小的lbuf空间,不能扩大空间.
*
* @return 重新分配后用于存储数据包的地址。失败则返回空指针。注:重新分配最好使用lbuf_real_size()获取lbuf空间的长度确认是否分配成功
*/
/* --------------------------------------------------------------------------*/
void *lbuf_realloc(void *lbuf, int size);
/* --------------------------------------------------------------------------*/
/**
* @brief 判断lbuf空间内的内容是否为空
*
* @param [in] head lbuf操作句柄
*
* @return 返回1则为空,0则不为空
*/
/* --------------------------------------------------------------------------*/
int lbuf_empty(struct lbuff_head *head);
/* --------------------------------------------------------------------------*/
/**
* @brief 清空lbuf空间内进行已经分配给数据包的空间
*
* @param [in] head lbuf操作句柄
*/
/* --------------------------------------------------------------------------*/
void lbuf_clear(struct lbuff_head *head);
/* --------------------------------------------------------------------------*/
/**
* @brief 把数据包写入分配好的lbuf区域
*
* @param [in] lbuf lbuf_alloc()返回用于存储数据包的地址
* @param [in] channel_map 选择映射到哪个通道,最多8个通道,使用位映射的方式进行通道对应.
*/
/* --------------------------------------------------------------------------*/
void lbuf_push(void *lbuf, u8 channel_map);
/* --------------------------------------------------------------------------*/
/**
* @brief 读取对应的通道映射的lbuf区域存储的内容
*
* @param [in] head lbuf操作句柄
* @param [in] channel 需要读取的通道值,一般使用BIT(n),n为需要读取的通道
*
* @return 成功则返回存储对应的通道映射的数据包的地址
*/
/* --------------------------------------------------------------------------*/
void *lbuf_pop(struct lbuff_head *head, u8 channel);
/* --------------------------------------------------------------------------*/
/**
* @brief 释放存储数据包的lbuf空间
*
* @param [in] lbuf lbuf_alloc()返回用于存储数据包的地址
*
* @return 0则释放失败，存在地址越界操作或者通道还没有被读完，ref-1,读完后才能完全释放。1则释放成功。
*/
/* --------------------------------------------------------------------------*/
int lbuf_free(void *lbuf);
/* --------------------------------------------------------------------------*/
/**
* @brief 用于调试,检查是否可以释放存储数据包的lbuf空间
*
* @param [in] lbuf lbuf_alloc()返回用于存储数据包的地址
* @param [in] rets 调用lbuf_free_check()函数的返回地址rets,取值可参考lbuf_free()
*/
/* --------------------------------------------------------------------------*/
void lbuf_free_check(void *lbuf, u32 rets);
/* --------------------------------------------------------------------------*/
/**
* @brief 返回可分配的用来存储数据包的最大lbuf内存空间
*
* @param [in] head lbuf操作句柄
*
* @return 可分配的最大lbuf内存空间的字节长度
*/
/* --------------------------------------------------------------------------*/
u32 lbuf_free_space(struct lbuff_head *head);
/* --------------------------------------------------------------------------*/
/**
* @brief 获取lbuf空间的状态
*
* @param [in] head lbuf操作句柄
* @param [out] state lbuff_state结构体
*/
/* --------------------------------------------------------------------------*/
void lbuf_state(struct lbuff_head *head, struct lbuff_state *state);
/* --------------------------------------------------------------------------*/
/**
* @brief lbuf信息打印
*
* @param [in] head lbuf操作句柄
*/
/* --------------------------------------------------------------------------*/
void lbuf_dump(struct lbuff_head *head);
/* --------------------------------------------------------------------------*/
/**
* @brief 获取已经存入lbuf空间的数据包的数量
*
* @param [in] head lbuf操作句柄
*
* @return lbuf存储的数据包的数量
*/
/* --------------------------------------------------------------------------*/
int lbuf_traversal(struct lbuff_head *head);
/* --------------------------------------------------------------------------*/
/**
* @brief 返回lbuf空间还可以被写入size大小数据包的数量
*
* @param [in] head lbuf操作句柄
* @param [in] size 欲检测写入数据包的大小
*
* @return 可以写入的数量
*/
/* --------------------------------------------------------------------------*/
int lbuf_avaliable(struct lbuff_head *head, int size);
/* --------------------------------------------------------------------------*/
/**
* @brief 返回给数据包分配的内存空间的大小
*
* @param [in] lbuf lbuf_alloc()返回用于存储数据包的地址
*
* @return 实际占用空间的字节长度
*/
/* --------------------------------------------------------------------------*/
int lbuf_real_size(void *lbuf);
/* --------------------------------------------------------------------------*/
/**
* @brief 计算lbuf空间剩下多少剩余空间
*
* @param [in] head lbuf操作句柄
*
* @return 剩余空间的字节长度
*/
/* --------------------------------------------------------------------------*/
int lbuf_remain_space(struct lbuff_head *head);
/* --------------------------------------------------------------------------*/
/**
* @brief 需要被重复释放的次数+1
*
* @param [in] lbuf lbuf_alloc()返回用于存储数据包的地址
*/
/* --------------------------------------------------------------------------*/
void lbuf_inc_ref(void *lbuf);
#endif
loader/ble_app_ota_update/include_lib/system/generic/list.h
+284
View File
@@ -0,0 +1,284 @@
#ifndef LIST_H
#define LIST_H
/**
* container_of - cast a member of a structure out to the containing structure
* @ptr: the pointer to the member.
* @type: the type of the container struct this is embedded in.
* @member: the name of the member within the struct.
*
*/
#ifdef offsetof
#undef offsetof
#endif
#ifdef container_of
#undef container_of
#endif
#define list_offsetof(type, memb) \
((unsigned long)(&((type *)0)->memb))
#define container_of(ptr, type, memb) \
((type *)((char *)ptr - list_offsetof(type, memb)))
struct list_head {
struct list_head *next, *prev;
};
#define LIST_HEAD_INIT(name) { &(name), &(name) }
#define LIST_HEAD(name) \
struct list_head name = LIST_HEAD_INIT(name)
/**
* list_entry - get the struct for this entry
* @ptr: the &struct list_head pointer.
* @type: the type of the struct this is embedded in.
* @member: the name of the list_struct within the struct.
*/
#define list_entry(ptr, type, member) \
container_of(ptr, type, member)
/**
* list_first_entry - get the first element from a list
* @ptr: the list head to take the element from.
* @type: the type of the struct this is embedded in.
* @member: the name of the list_struct within the struct.
*
* Note, that list is expected to be not empty.
*/
/* REF_LIST: spi.c */
#define list_first_entry(ptr, type, member) \
list_entry((ptr)->next, type, member)
/**
* list_for_each - iterate over a list
* @pos: the &struct list_head to use as a loop cursor.
* @head: the head for your list.
*/
#define list_for_each(pos, head) \
for (pos = (head)->next; pos != (head); \
pos = pos->next)
/**
* list_for_each_safe - iterate over a list safe against removal of list entry
* @pos: the &struct list_head to use as a loop counter.
* @n: another &struct list_head to use as temporary storage
* @head: the head for your list.
*/
#define list_for_each_safe(pos, n, head) \
for (pos = (head)->next, n = pos->next; pos != (head); \
pos = n, n = pos->next)
/**
* list_for_each_entry - iterate over list of given type
* @pos: the type * to use as a loop cursor.
* @head: the head for your list.
* @member: the name of the list_struct within the struct.
*/
#define list_for_each_entry(pos, head, member) \
for (pos = list_entry((head)->next, typeof(*pos), member); \
&pos->member != (head); \
pos = list_entry(pos->member.next, typeof(*pos), member))
/**
* list_for_each_entry_reverse - iterate backwards over list of given type.
* @pos: the type * to use as a loop cursor.
* @head: the head for your list.
* @member: the name of the list_struct within the struct.
*/
#define list_for_each_entry_reverse(pos, head, member) \
for (pos = list_entry((head)->prev, typeof(*pos), member); \
&pos->member != (head); \
pos = list_entry(pos->member.prev, typeof(*pos), member))
/**
* list_for_each_entry_safe - iterate over list of given type safe against removal of list entry
* @pos: the type * to use as a loop cursor.
* @n: another type * to use as temporary storage
* @head: the head for your list.
* @member: the name of the list_struct within the struct.
*/
#define list_for_each_entry_safe(pos, n, head, member) \
for (pos = list_entry((head)->next, typeof(*pos), member), \
n = list_entry(pos->member.next, typeof(*pos), member); \
&pos->member != (head); \
pos = n, n = list_entry(n->member.next, typeof(*n), member))
/**
* list_empty - tests whether a list is empty
* @head: the list to test.
*/
/* REF_LIST: spi.c */
static inline int list_empty(const struct list_head *head)
{
return head->next == head;
}
/*
* Insert a new entry between two known consecutive entries.
*
* This is only for internal list manipulation where we know
* the prev/next entries already!
*/
static inline void __list_add(struct list_head *_new,
struct list_head *prev,
struct list_head *next)
{
next->prev = _new;
_new->next = next;
_new->prev = prev;
prev->next = _new;
}
/**
* list_add_tail - add a new entry
* @new: new entry to be added
* @head: list head to add it before
*
* Insert a new entry before the specified head.
* This is useful for implementing queues.
*/
/* REF_LIST: spi.c */
static inline void list_add_tail(struct list_head *_new, struct list_head *head)
{
__list_add(_new, head->prev, head);
}
static inline void __list_del(struct list_head *prev, struct list_head *next)
{
if (prev == 0 || next == 0) {
return;
}
//ASSERT(prev!=NULL || next!=NULL)
next->prev = prev;
prev->next = next;
}
static inline void __list_del_entry(struct list_head *entry)
{
__list_del(entry->prev, entry->next);
}
/* REF_LIST: spi.c */
static inline void list_del(struct list_head *entry) //修改过的list_del，这里与list_del_init一样
{
__list_del(entry->prev, entry->next);
entry->next = entry;
entry->prev = entry;
}
/*
* Simple doubly linked list implementation.
*
* Some of the internal functions ("__xxx") are useful when
* manipulating whole lists rather than single entries, as
* sometimes we already know the next/prev entries and we can
* generate better code by using them directly rather than
* using the generic single-entry routines.
*/
static inline void INIT_LIST_HEAD(struct list_head *list)
{
list->next = list;
list->prev = list;
}
static inline void list_del_init(struct list_head *entry)
{
__list_del_entry(entry);
INIT_LIST_HEAD(entry);
}
/**
* list_move_tail - delete from one list and add as another's tail
* @list: the entry to move
* @head: the head that will follow our entry
*/
static inline void list_move_tail(struct list_head *list,
struct list_head *head)
{
__list_del(list->prev, list->next);
list_add_tail(list, head);
}
/**
* list_add - add a new entry
* @new: new entry to be added
* @head: list head to add it after
*
* Insert a new entry after the specified head.
* This is good for implementing stacks.
*/
static inline void list_add(struct list_head *new, struct list_head *head)
{
__list_add(new, head, head->next);
}
static inline int list_is_head(struct list_head *head, struct list_head *member)
{
return head->next == member;
}
#if 0
static inline void __list_splice(const struct list_head *list,
struct list_head *prev,
struct list_head *next)
{
struct list_head *first = list->next;
struct list_head *last = list->prev;
first->prev = prev;
prev->next = first;
last->next = next;
next->prev = last;
}
/**
* list_splice_tail_init - join two lists and reinitialise the emptied list
* @list: the new list to add.
* @head: the place to add it in the first list.
*
* Each of the lists is a queue.
* The list at @list is reinitialised
*/
static inline void list_splice_tail_init(struct list_head *list,
struct list_head *head)
{
if (!list_empty(list)) {
__list_splice(list, head->prev, head);
INIT_LIST_HEAD(list);
}
}
/**
* list_is_singular - tests whether a list has just one entry.
* @head: the list to test.
*/
static inline int list_is_singular(const struct list_head *head)
{
return !list_empty(head) && (head->next == head->prev);
}
/**
* list_splice_tail - join two lists, each list being a queue
* @list: the new list to add.
* @head: the place to add it in the first list.
*/
static inline void list_splice_tail(struct list_head *list,
struct list_head *head)
{
if (!list_empty(list)) {
__list_splice(list, head->prev, head);
}
}
#endif
#endif
loader/ble_app_ota_update/include_lib/system/generic/log.h
+125
View File
@@ -0,0 +1,125 @@
#ifndef __LOG_H
#define __LOG_H
#include "printf.h"
#define __LOG_VERB 0
#define __LOG_DEBUG 1
#define __LOG_INFO 2
#define __LOG_WARN 3
#define __LOG_ERROR 4
#define __LOG_CHAR 5
#define __LOG_ENABLE
#ifndef __LOG_LEVEL
#define __LOG_LEVEL 0
#endif
#ifdef __DEBUG
#else
#define CONFIG_RELEASE_ENABLE
#endif
#ifdef CONFIG_RELEASE_ENABLE
#undef __LOG_LEVEL
#define __LOG_LEVEL 0xff
#endif
#if __LOG_LEVEL > __LOG_VERB
#define log_v(...) do {} while (0)
#else
#define log_v(...) printf(__VA_ARGS__)
#endif
#if __LOG_LEVEL > __LOG_DEBUG
#define log_d(...) do {} while (0)
#else
#define log_d(...) printf(__VA_ARGS__)
#endif
#if __LOG_LEVEL > __LOG_INFO
#define log_i(...) do {} while (0)
#else
#define log_i(...) printf(__VA_ARGS__)
#endif
#if __LOG_LEVEL > __LOG_WARN
#define log_w(...) do {} while (0)
#else
#define log_w(...) printf(__VA_ARGS__)
#endif
#if __LOG_LEVEL > __LOG_ERROR
#define log_e(...) do {} while (0)
#else
#define log_e(...) printf(__VA_ARGS__)
#endif
#if __LOG_LEVEL > __LOG_CHAR
#define log_c(x) do {} while (0)
#elif defined __LOG_ENABLE
#define log_c(x) putchar(x)
#else
#define log_c(x)
#endif
#define r_printf(x, ...) log_i("\e[31m\e[1m" x "\e[0m", ## __VA_ARGS__)
#define g_printf(x, ...) log_i("\e[32m\e[1m" x "\e[0m", ## __VA_ARGS__)
#define y_printf(x, ...) log_i("\e[33m\e[1m" x "\e[0m", ## __VA_ARGS__)
#define r_f_printf(x, ...) log_i("\e[31m\e[5m\e[1m" x "\e[0m", ## __VA_ARGS__)
#define g_f_printf(x, ...) log_i("\e[32m\e[5m\e[1m" x "\e[0m", ## __VA_ARGS__)
#define y_f_printf(x, ...) log_i("\e[33m\e[5m\e[1m" x "\e[0m", ## __VA_ARGS__)
#ifndef __LOG_ENABLE
#define log_dump(a, b) do {} while(0)
#define log_putchar() do {} while(0)
#define log_early_init(a) do {} while(0)
#define log_level(a) do {} while(0)
#else
struct logbuf {
u16 len;
u16 buf_len;
char buf[0];
};
int log_output_lock();
void log_output_unlock();
void log_print_time();
void log_early_init(int buf_size);
void log_level(int level);
// void log_print(int level, const char *tag, const char *format, ...);
void log_dump(const u8 *buf, int len);
struct logbuf *log_output_start(int len);
void log_output_end(struct logbuf *);
void log_putchar(struct logbuf *lb, char c);
void log_put_u8hex(struct logbuf *lb, unsigned char dat);
void log_putbyte(char);
void log_set_time_offset(int offset);
int log_get_time_offset();
#endif
void log_flush();
#endif
loader/ble_app_ota_update/include_lib/system/generic/msg.h
+63
View File
@@ -0,0 +1,63 @@
#ifndef _MSG_H_
#define _MSG_H_
#include "typedef.h"
#if (defined(CONFIG_CPU_BD47) || defined(CONFIG_CPU_BR29)) && defined(BLE_APP_LOW_RAM_USED) // bd47 内存紧缺
#define MAX_POOL 100
#else
#define MAX_POOL 128
#endif
enum {
MSG_NO_ERROR = 0,
MSG_EVENT_EXIST = -1,
MSG_NOT_EVENT = -2,
MSG_EVENT_PARAM_ERROR = -3,
MSG_BUF_NOT_ENOUGH = -4,
};
#define Q_USER 0x400000
enum {
LMP_EVENT = Q_USER + 1,
LMP_HCI_CMD,
LMP_HCI_CMD_TO_CONN,
HCI_COMMON_CMD,
LL_EVENT,
HCI_CMD_TO_LL,
HCI_CMD_TO_LL_CONN,
TWS_LMP_EVENT,
BTSTACK_HCI_EVENT,
BTSTACK_HCI_ACL,
//MSG_BT_UPDATA_START = 0x80,
//MSG_BT_UPDATE_LOADER_DOWNLOAD_START,
MSG_JL_SPEECH_START_PREPARE = 0xB00,
MSG_JL_SPEECH_START,
MSG_JL_SPEECH_STOP,
MSG_JL_GET_DEV_INFO,
MSG_JL_GET_DEV_UPDATE_FILE_INFO_OFFSET,
MSG_JL_INQUIRE_DEVEICE_IF_CAN_UPDATE,
MSG_JL_ENTER_UPDATE_MODE,
MSG_JL_EXIT_UPDATE_MODE,
MSG_JL_UPDATE_DISCONNECT,
MSG_JL_UPDATE_REVICE_REBOOT,
MSG_JL_SWITCH_CH_SPP,
MSG_JL_SUCCESS_STATUS_HANDLE,
MSG_JL_ERR_STATUS_HANDLE,
MSG_JL_GET_PRIVATE_INFO,
MSG_UBOOT_SOFT_POWEROFF,
};
void task_message_init(void);
int task_post_msg(char *name, int argc, ...);
int task_post_msg_base(const char *name, int argc, int cmd, int *argv);
int task_get_msg(u16 timeout, int len, int *msg);
#endif
loader/ble_app_ota_update/include_lib/system/generic/sys_timer.h
+76
View File
@@ -0,0 +1,76 @@
#define SYS_TIMER_H
#include "generic/typedef.h"
#include "list.h"
typedef int sys_timer;
struct sys_timer {
struct list_head entry;
void (*func)(void *priv);
void *priv;
u32 jiffies;
u32 msec: 24;
u32 del: 1;
u32 timeout: 1;
u16 id;
u8 used;
};
void sys_timer_init();
bool __timer_find(struct sys_timer *timer);
u16 sys_timer_add(void *priv, void (*func)(void *priv), u32 msec);
void sys_timer_schedule(void);
void sys_timer_delay_schedule(void);
void sys_timer_set_user(struct sys_timer *timer, u32 user);
u32 sys_timer_get_user(struct sys_timer *timer);
void sys_timer_del_schedule(void);
void loop_timer_schedule(void);
void sys_timer_re_run(u16 id);
void sys_timer_del(u16 t);
int sys_timer_modify(u16 id, u32 msec);
u16 sys_timeout_add(void *priv, void (*func)(void *priv), u32 msec);
void sys_timeout_del(u16 t);
/*
* For Compatible
*/
#define sys_hi_timer_schedule()\
usr_timer_schedule()
#define sys_hi_timer_add(a, b, c)\
sys_timer_add(a, b, c)
#define sys_hi_timeout_add(a, b, c)\
sys_timeout_add(a, b, c)
// usr_timeout_add(a, b, c, 1)
#define sys_hi_timer_modify(a, b)\
sys_timer_modify(a, b)
#define sys_hi_timeout_modify(a, b)\
sys_timer_modify(a, b)
#define sys_hi_timer_del(a)\
sys_timer_del(a)
#define sys_hi_timeout_del(a)\
sys_timer_del(a)
#define sys_s_hi_timer_add(a, b, c)\
sys_timer_add(a, b, c, 0)
#define sys_s_hi_timerout_add(a, b, c)\
sys_timeout_add(a, b, c, 0)
#define sys_s_hi_timer_modify(a, b)\
sys_timer_modify(a, b)
#define sys_s_hi_timeout_modify(a, b)\
sys_timer_modify(a, b)
#define sys_s_hi_timer_del(a)\
sys_timer_del(a)
#define sys_s_hi_timeout_del(a)\
sys_timeout_del(a)
loader/ble_app_ota_update/include_lib/system/generic/typedef.h
+219
View File
@@ -0,0 +1,219 @@
/*************************************************************
File: typedef.h
Author:Juntham
Discriptor:
数据类型重定义
Version:
Date：
*************************************************************/
#ifndef _typedef_h_
#define _typedef_h_
#include "asm/cpu.h"
typedef signed char int8_t;
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
typedef unsigned int uint32_t;
typedef unsigned long long int uint64_t;
typedef unsigned char u8, bool, BOOL;
typedef char s8;
typedef signed short s16;
typedef unsigned short u16;
typedef unsigned int u32;
typedef signed int s32;
typedef unsigned long long u64;
typedef u32 FOURCC;
typedef long long s64;
typedef unsigned long long u64;
#ifdef READ_BT_8
#undef READ_BT_8
#endif
#ifdef READ_BT_16
#undef READ_BT_16
#endif
#ifdef READ_BT_24
#undef READ_BT_24
#endif
#ifdef READ_BT_32
#undef READ_BT_32
#endif
#define READ_BT_8( buffer, pos) ( ((u8) buffer[pos]))
#define READ_BT_16( buffer, pos) ( ((u16) buffer[pos]) | (((u16)buffer[pos+1]) << 8))
#define READ_BT_24( buffer, pos) ( ((u32) buffer[pos]) | (((u32)buffer[pos+1]) << 8) | (((u32)buffer[pos+2]) << 16))
#define READ_BT_32( buffer, pos) ( ((u32) buffer[pos]) | (((u32)buffer[pos+1]) << 8) | (((u32)buffer[pos+2]) << 16) | (((u32) buffer[pos+3])) << 24)
#if defined(__GNUC__)
///<locate code to x segment ever exist
#define SEC_USED(x) __attribute__((section(#x),used))
///<locate code to x segment optimized by dependency
#define SEC(x) __attribute__((section(#x)))
#define sec(x) __attribute__((section(#x),used))
///<locate data to x segment
#define AT(x) __attribute__((section(#x)))
#define SET(x) __attribute__((x))
#define ALIGNED(x) __attribute__((aligned(x)))
#define _GNU_PACKED_ __attribute__((packed))
#define _NOINLINE_ __attribute__((noinline))
#define _INLINE_ __attribute__((always_inline))
#define _WEAK_ __attribute__((weak))
#define _WEAKREF_ __attribute__((weakref))
#define _NORETURN_ __attribute__((noreturn))
#define _NAKED_ __attribute__((naked))
#define SET_INTERRUPT __attribute__((interrupt("")))
#define ___interrupt __attribute__((interrupt("")))
#else
#define SEC_USED(x)
#define SEC(x)
#define AT(x)
#define SET(x)
#define ALIGNED(x)
#define _GNU_PACKED_
#define _NOINLINE_
#define _INLINE_
#define _WEAK_
#define _WEAKREF_
#define _NORETURN_
#define _NAKED_
#endif
#if CPU_ENDIAN == LITTLE_ENDIAN
//#define ntohl(x) (u32)((x>>24)|((x>>8)&0xff00)|(x<<24)|((x&0xff00)<<8))
//#define ntoh(x) (u16)((x>>8&0x00ff)|x<<8&0xff00)
//#define ntohl(x) (u32)((((u32)(x))>>24) | ((((u32)(x))>>8)&0xff00) | (((u32)(x))<<24) | ((((u32)(x))&0xff00)<<8))
//#define ntoh(x) (u16)((((u32)(x))>>8&0x00ff) | (((u32)(x))<<8&0xff00))
//#define NTOH(x) (x) = ntoh(x)
//#define NTOHL(x) (x) = ntohl(x)
#define LD_WORD(ptr) (u16)(*(u16*)(u8*)(ptr))
#define LD_DWORD(ptr) (u32)(*(u32*)(u8*)(ptr))
#define ST_WORD(ptr,val) *(u16*)(u8*)(ptr)=(u16)(val)
#define ST_DWORD(ptr,val) *(u32*)(u8*)(ptr)=(u32)(val)
#else
#define ntohl(x) (x)
#define ntoh(x) (x)
#define NTOH(x) (x) = ntoh(x)
#define NTOHL(x) (x) = ntohl(x)
#endif
#if defined(__UPDATE_NEED_SFC) && defined(__APP_IS_OTA) && !defined(__UPDATE_RUN_RAM)
#define SFC_MODE_EN
#endif
#if defined(SFC_MODE_EN)
#define AT_SPI_CODE AT(.vm_sfc.text.cache)
#else
#define AT_SPI_CODE
#endif
#undef FALSE
#define FALSE 0
#undef TRUE
#define TRUE 1
#define false 0
#define true 1
#ifndef NULL
#define NULL (void *)0
#endif
#define BIT(n) (1UL << (n))
#define BitSET(REG,POS) ((REG) |= (1L << (POS)))
#define BitCLR(REG,POS) ((REG) &= (~(1L<< (POS))))
#define BitXOR(REG,POS) ((REG) ^= (~(1L << (POS))))
#define BitCHK_1(REG,POS) (((REG) & (1L << (POS))) == (1L << (POS)))
#define BitCHK_0(REG,POS) (((REG) & (1L << (POS))) == 0x00)
#define testBit(REG,POS) ((REG) & (1L << (POS)))
#define clrBit(x,y) (x) &= ~(1L << (y))
#define setBit(x,y) (x) |= (1L << (y))
#define readb(addr) *((volatile unsigned char*)(addr))
#define readw(addr) *((volatile unsigned short *)(addr))
#define readl(addr) *((volatile unsigned long*)(addr))
#define writeb(addr, val) *((volatile unsigned char*)(addr)) = (u8)(val)
#define writew(addr, val) *((volatile unsigned short *)(addr)) = (u16)(val)
#define writel(addr, val) *((volatile unsigned long*)(addr)) = (u32)(val)
#define ALIGN_4BYTE(size) ((size+3)&0xfffffffc)
#if CPU_ENDIAN == BIG_ENDIAN
#define __cpu_u16(lo, hi) ((lo)|((hi)<<8))
#elif CPU_ENDIAN == LITTLE_ENDIAN
#define __cpu_u16(lo, hi) ((hi)|((lo)<<8))
#else
#error "undefine cpu eadin"
#endif
#ifndef MIN
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#endif
#ifndef MAX
#define MAX(a, b) ((a) > (b) ? (a) : (b))
#endif
#define ARRAY_SIZE(array) (sizeof(array)/sizeof(array[0]))
#define likely(x) __builtin_expect(!!(x), 1)
#define unlikely(x) __builtin_expect(!!(x), 0)
#define SFR(sfr, start, len, dat) \
(sfr = (sfr & ~((~(0xffffffff << (len))) << (start))) | \
(((dat) & (~(0xffffffff << (len)))) << (start)))
#include "errno-base.h"
#include "string.h"
#include "strings.h"
#include "malloc.h"
#include "jiffies.h"
#ifdef offsetof
#undef offsetof
#endif
#ifdef container_of
#undef container_of
#endif
#define offsetof(type, memb) \
((unsigned long)(&((type *)0)->memb))
#define container_of(ptr, type, memb) \
((type *)((char *)(ptr) - offsetof(type, memb)))
void delay(unsigned int);
void delay_us(unsigned int);
// 只适用32位以内数据比较
#define LOOP_OVERTAKE(a, b, n) \
((((a) - (b)) & ((1ULL << (n)) - 1)) < ((1UL << ((n) - 1))))
#endif
loader/ble_app_ota_update/include_lib/system/malloc.h
+30
View File
@@ -0,0 +1,30 @@
#ifndef _MEM_HEAP_H_
#define _MEM_HEAP_H_
#ifdef __cplusplus
extern "C" {
#endif
extern void *malloc(unsigned long size);
extern void *zalloc(unsigned long size);
extern void *calloc(unsigned long count, unsigned long size);
extern void *realloc(void *rmem, unsigned long newsize);
extern void free(void *mem);
extern void *kmalloc(unsigned long size, int flags);
extern void *vmalloc(unsigned long size);
extern void vfree(void *addr);
extern void *kzalloc(unsigned int len, int a);
extern void kfree(void *p);
extern void malloc_stats(void);
extern void malloc_dump();
#ifdef __cplusplus
}
#endif
#endif /* _MEM_HEAP_H_ */
loader/ble_app_ota_update/include_lib/system/os/os_cpu.h
+87
View File
@@ -0,0 +1,87 @@
/***********************************Jieli tech************************************************
File : os_cpu.h
By : Juntham
date : 2014-07-03 09:06
********************************************************************************************/
#ifndef _OS_CPU_H
#define _OS_CPU_H
#include "asm/cpu.h"
#include "jiffies.h"
#ifndef __ASSEMBLY__
typedef unsigned short QS;
typedef unsigned int OS_STK; /* Each stack entry is 32-bit wide*/
typedef unsigned int OS_CPU_SR; /* Unsigned 32 bit quantity */
typedef unsigned int OS_CPU_DATA; /* Unsigned 32 bit quantity */
#endif
#define OS_CPU_EXT extern
#define OS_CPU_CORE CPU_CORE_NUM
#define OS_CPU_ID current_cpu_id()
#define OS_STK_GROWTH 1 /* Stack grows from HIGH to LOW memory*/
#define OS_CPU_MMU 0
#define OS_CPU_VIRTUAL_MEM 1 //临时定义：区别于OS_CPU_MMU
#define OS_TASK_CLR(a) CPU_TASK_CLR(a)
#define OS_TASK_SW(a) CPU_TASK_SW(a) /* 任务级任务切换函数*/
#define OS_INT_NESTING CPU_INT_NESTING
#define CPU_SR_ALLOC()
#define OS_SR_ALLOC()
#define OS_ENTER_CRITICAL() \
CPU_CRITICAL_ENTER(); \
#define OS_EXIT_CRITICAL() \
CPU_CRITICAL_EXIT()
#ifndef __ASSEMBLY__
/*#include "system/spinlock.h"
extern spinlock_t os_lock;
#define OS_ENTER_CRITICAL() \
spin_lock(&os_lock)
#define OS_EXIT_CRITICAL() \
spin_unlock(&os_lock)*/
void OSCtxSw(void);
extern void EnableOtherCpu(void) ;
#define os_ctx_sw OSCtxSw
void OSInitTick(u32 hz);
void InstallOSISR(void);
void os_task_dead(const char *task_name);
#endif
/*
*********************************************************************************************************
* DATA TYPES
* (Compiler Specific)
*********************************************************************************************************
*/
#define OS_CRITICAL_METHOD 3
#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */
//#define CPU_SR_ALLOC() OS_CPU_SR cpu_sr
#endif
#endif /*_OS_CPU_H */
loader/ble_app_ota_update/include_lib/system/spinlock.h
+76
View File
@@ -0,0 +1,76 @@
#ifndef SYS_SPINLOCK_H
#define SYS_SPINLOCK_H
#include "typedef.h"
//#include "cpu.h"
//#include "irq.h"
struct __spinlock {
volatile u32 rwlock;
};
typedef struct __spinlock spinlock_t;
extern void local_irq_disable(void);
extern void local_irq_enable(void);
#define preempt_disable() \
local_irq_disable()
#define preempt_enable() \
local_irq_enable()
#if CPU_CORE_NUM > 1
#define spin_acquire(lock) \
do { \
arch_spin_lock(lock); \
}while(0)
#define spin_release(lock) \
do { \
arch_spin_unlock(lock); \
}while(0)
#else
#define spin_acquire(lock) \
do { \
}while(0)
#define spin_release(lock) \
do { \
}while(0)
#endif
#define DEFINE_SPINLOCK(x) \
spinlock_t x = { .rwlock = 0 }
static inline void spin_lock_init(spinlock_t *lock)
{
lock->rwlock = 0;
}
static inline void spin_lock(spinlock_t *lock)
{
preempt_disable();
spin_acquire(lock);
}
static inline void spin_unlock(spinlock_t *lock)
{
spin_release(lock);
preempt_enable();
}
#endif
loader/ble_app_ota_update/include_lib/update/update_main.h
+216
View File
@@ -0,0 +1,216 @@
#ifndef __UPDATE_MAIN_H__
#define __UPDATE_MAIN_H__
#include "typedef.h"
#include "tff.h"
extern u32 UPDATE_BEG;
extern u32 UPDATA_SIZE;
#define UART_UPDATE_FLAG_ADDR (u32)(&UPDATE_BEG)
#define UPDATE_FLAG_ADDR ((u32)(&UPDATE_BEG) + 0x8)
#define UPDATE_PRIV_PARAM_LEN 32
#define UPDATA_MAGIC (0x5A00) //防止CRC == 0 的情况
// #define SEEK_SET 0 #<{(| Seek from beginning of file. |)}>#
// #define SEEK_CUR 1 #<{(| Seek from current position. |)}>#
// #define SEEK_END 2 #<{(| Seek from end of file. |)}>#
//给SDK的升级结果
typedef enum {
UPDATA_NON = UPDATA_MAGIC,
UPDATA_READY,
UPDATA_SUCCESSFULLY,
UPDATA_PARM_ERR,
UPDATA_DEV_ERR,
UPDATA_KEY_ERR,
} UPDATA_RESULT_TO_SDK;
//区分是否跳转还是断电重新上电进入loader
typedef enum {
UPDATE_JUMP = 0,
UPDATE_POWERON,
} UPDATE_MODE;
typedef enum {
UPDATE_PARM,
UPDATE_START,
UPDATE_END,
} UPDATE_STEP;
typedef enum {
UPDATE_READ_TOUT_PARM = UPDATE_END + 1, // 根据远端ini文件的配合更新读超时时间
UPDATE_SDK_BEGIN_PARM, // 开始升级
} UPDATE_INI;
typedef enum {
USB_UPDATA = UPDATA_MAGIC, //0x5A00
SD0_UPDATA, //0x5A01
SD1_UPDATA,
PC_UPDATA,
UART_UPDATA,
BT_UPDATA,
BLE_APP_UPDATA,
SPP_APP_UPDATA,
DUAL_BANK_UPDATA,
BLE_TEST_UPDATA,
NORFLASH_UPDATA,
// BLE_UPDATA,
USER_NORFLASH_UFW_UPDATA,
USER_LC_FLASH_UFW_UPDATA,
USB_HID_UPDATA,
DEV_NORFLASH_UFW_UPDATA,
NET_UFW_UPDATA,
USER_NANDFLASH_UFW_UPDATA,
TESTBOX_UART_UPDATA,
UPDIFF_FLASH_UPDATA,
COMBAK_FLASH_UPDATA,
DEV_UPDATA_MAX,
DEV_UPDATE = 0xFFFE,
NON_DEV_UPDATA = 0xFFFF,
} UPDATA_TYPE;
enum EXT_ARG_TYPE {
EXT_LDO_TRIM_RES = 0,
EXT_JUMP_FLAG,
EXT_BT_MAC_ADDR,
EXT_RF_PA_INFO,
EXT_RESERVED_UPDATE, // 用于sdk传入参数控制是否升级预留区域
EXT_RESET_TIME_WITHOUT_CONN, // 用于sdk传入未连接状态保持多久就重启的超时时间
EXT_SD_IO_INFO,
EXT_BT_WLA_INFO,
EXT_MUTIL_UPDATE_NAME = 0x8,
EXT_USER_API_BIN_INFO,
EXT_NEW_SDK_UPD_AGAIN,
EXT_NEW_FILENAME,
EXT_KEEP_ROMIO_INFO = 0x10,
EXT_NAND_PARAM = 0x11,
EXT_SYS_CLK_PARAM = 0x12,
EXT_TYPE_MAX = 0xff,
};
typedef enum _UPDATA_RESULT {
UPDATA_RESULT_SUCC = 1,
UPDATA_RESULT_FAIL,
UPDATA_RESULT_KEY_ERR,
} UPDATA_RESULT;
//回报给测试盒的？
enum {
BT_UPDATE_OVER = 0,
BT_UPDATE_KEY_ERR,
BT_UPDATE_CONNECT_ERR,
};
enum {
UPDATE_ERR_NONE = 0,
UPDATE_ERR_UFW_HEAD_CRC_ERR,
UPDATE_ERR_NOT_FIND_LOADER_FILE,
UPDATE_ERR_NOT_FIND_TARGET_LOADER,
UPDATE_ERR_LOADER_HEAD_CRC_ERR = 4,
UPDATE_ERR_MALLOC_ERR,
UPDATE_ERR_LOADER_WRITE_ERR,
UPDATE_ERR_FILE_HANDLE_ERR,
UPDATE_ERR_LOADER_VERIFY_ERR = 8,
UPDATE_ERR_NOT_FIND_FLASH_BIN,
UPDATE_ERR_FLASH_HEAD_CRC_ERR,
UPDATE_ERR_NOT_FIND_TARGET_FILE,
UPDATE_ERR_KEY_ERR = 12,
UPDATE_ERR_UBOOT_NOT_MATCH,
UPDATE_ERR_READ_REMOTE_FILE_ERR,
UPDATE_ERR_REMOTE_RES_FILE_CRC_ERR,
UPDATE_ERR_CODE_VERIFY_ERR = 16,
UPDATE_ERR_RES0_VERIFY_ERR,
UPDATE_ERR_NOT_FIND_RESERVE_DIR_FILE,
UPDATE_ERR_LOCAL_FILE_HEAD_CRC_ERR,
UPDATE_ERR_LOCAL_FILE_DATA_CRC_ERR = 20,
UPDATE_ERR_PARAM_ERR,
UPDATE_ERR_BT_CFG_UPDATE_ERR,
UPDATE_ERR_TONE_UPDATE_ERR,
UPDATE_ERR_RESERVED_CONFIG_UPDATE_ERR = 24,
UPDATE_ERR_PRODUCT_ID_NOT_MATCH,
UPDATE_ERR_EX_DSP_UPDATE_ERR,
UPDATE_ERR_CONN_ERR,
UPDATE_ERR_ERASE_FAIL = 28,
UPDATE_ERR_UPDATE_FILE_SIZE_ERR,
UPDATE_ERR_ANC_CFG_UPDATE_ERR,
UPDATE_ERR_ANC_COEF_UPDATE_ERR,
UPDATE_ERR_RESERVED_ZONE_UPDATE_ERR = 32,
// 可以把错误更加具体化
UPDATE_ERR_FLASH_ID_ERR,
UPDATE_ERR_CHIP_ID_ERR,
UPDATE_ERR_EFUSE_OVERWRITE_ERR,
UPDATE_ERR_EFUSE_BT_NAME_ERR,
UPDATE_ERR_EFUSE_CHANNEL_ERR,
UPDATE_ERR_ISD_CONFIG_ERR,
UPDATE_ERR_LOCAL_EFUSE_CRC_ERR,
UPDATE_ERR_LOCAL_EFUSE_WRITE_ERR,
UPDATE_ERR_WRITE_P11_CODE_ERR,
UPDATE_ERR_EFUSE_MASKROM_USE2_WRITE_ERR,
};
//for rcsp update
enum {
DEV_CONN_STATE_DISCONNECTED = 0,
DEV_CONN_STATE_CONNECTED,
DEV_CONN_STATE_READY_UPDATE,
DEV_CONN_STATE_START_UPDATE,
};
typedef struct _UPDATA_PARM {
u16 parm_crc;
u16 parm_type; //UPDATA_TYPE:sdk pass parm to uboot
u16 parm_result; //UPDATA_TYPE:uboot return result to sdk
u16 magic;
u8 file_patch[32];
u8 parm_priv[32];
u32 ota_addr;
u16 ext_arg_len;
u16 ext_arg_crc;
} UPDATA_PARM;
typedef struct _update_op_api_t {
int (*ch_init)(void (*resume_hdl)(void *priv), int (*sleep_hdl)(void *priv));
u16(*f_open)(void);
u16(*f_read)(void *fp, u8 *buff, u32 len);
int (*f_seek)(void *fp, u8 type, u32 offset);
u16(*f_stop)(u8 err);
int (*notify_update_content_size)(u32 size);
void (*ch_exit)(void *priv);
void *priv;
} update_op_api_t;
typedef struct _update_mode_info_t {
s32 type;
void (*state_cbk)(u32 status, void *priv);
const update_op_api_t *file_op;
u8 task_en;
} update_mode_info_t;
void update_main();
void set_updata_result(u16 type, u16 result);
u8 fs_update_result_transition(u8 err);
extern u32 fs_dev_mount(u16 dev_type);
void update_reset(void);
u8 *update_param_ext_get(UPDATA_PARM *p, u8 ext_type);
void *dev_update_handle_get(void);
void mutil_cpu_set_offset(u32 offset);
#endif