初版
This commit is contained in:
huxi
@@ -0,0 +1,45 @@
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#ifndef __CLOCK_H__
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#define __CLOCK_H__
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#include "typedef.h"
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#define MHz (1000000L)
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#define OSC_FREQ 24000000
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#define SYS_CLK 48000000
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enum {
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UART_CLOCK_IN_DISABLE = 0,
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UART_CLOCK_IN_STD48M,
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UART_CLOCK_IN_STD24M,
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UART_CLOCK_IN_EXT,
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UART_CLOCK_IN_LSB,
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};
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#define UART_CLOCK_IN(x) SFR(JL_LSBCLK->PRP_CON0, 12, 3, x)
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#define BT_CLOCK_IN(x) //SFR(JL_CLOCK->CLK_CON1, 14, 2, x)
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//for MACRO - BT_CLOCK_IN
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enum {
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BT_CLOCK_IN_PLL48M = 0,
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BT_CLOCK_IN_HSB,
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BT_CLOCK_IN_LSB,
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BT_CLOCK_IN_DISABLE,
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};
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void lrc_init(void);
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void sys_clk_init(u32 osc_freq, u32 sys_clk);
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void btosc_upgrade_cfg(void *cfg);
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void sys_clk_reinit(void *clk_argv);
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u32 clk_get(const char *clk);
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#define CLR_DVDD_POR_PND() JL_HSBCLK->PWR_CON |= BIT(11)
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#endif
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@@ -0,0 +1,21 @@
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#ifndef __CRC_H__
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#define __CRC_H__
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#include "typedef.h"
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u16 chip_crc16(void *ptr, u32 len);
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u16 chip_crc16_with_init(void *ptr, u32 len, u16 init);
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void CrcDecode(void *buf, u16 len);
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void crc_encode(void *buf, u32 len, const u8 *crckey, u32 offset);
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#define CRC16(x,y) chip_crc16(x,y)
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#endif
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@@ -0,0 +1,412 @@
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//*********************************************************************************//
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// Module name : csfr.h //
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// Description : q32DSP core sfr define //
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// By Designer : zequan_liu //
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// Dat changed : //
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//*********************************************************************************//
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#ifndef __Q32DSP_CSFR__
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#define __Q32DSP_CSFR__
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#define __RW volatile // read write
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#define __RO volatile const // only read
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#define __WO volatile // only write
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#define __u8 unsigned int // u8 to u32 special for struct
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#define __u16 unsigned int // u16 to u32 special for struct
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#define __u32 unsigned int
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#define csfr_base 0xff0000
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//*********************************************************************************
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//
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// hcore_sfr
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//
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//*********************************************************************************
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//............. 0x0000 - 0x00ff............
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typedef struct {
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__RW __u32 CON0;
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__RW __u32 FTMAX;
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} JL_CMNG_TypeDef;
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#define JL_CMNG_BASE (csfr_base + map_adr(0x00, 0x00))
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#define JL_CMNG ((JL_CMNG_TypeDef *)JL_CMNG_BASE)
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//............. 0x0100 - 0x01ff............
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//typedef struct {
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// __RW __u32 CON;
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// __RW __u32 KEY;
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//} JL_SDTAP_TypeDef;
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//#define JL_SDTAP_BASE (csfr_base + map_adr(0x01, 0x00))
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//#define JL_SDTAP ((JL_SDTAP_TypeDef *)JL_SDTAP_BASE)
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//............. 0x0200 - 0x02ff............
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typedef struct {
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__RW __u32 WREN;
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__RW __u32 CON0;
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__RW __u32 CON1;
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__RW __u32 CON2;
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__RW __u32 CON3;
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__RW __u32 MSG0;
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__RW __u32 MSG1;
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__RW __u32 MSG2;
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__RW __u32 MSG3;
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__RO __u32 ID;
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} JL_CEMU_TypeDef;
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#define JL_CEMU_BASE (csfr_base + map_adr(0x02, 0x00))
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#define JL_CEMU ((JL_CEMU_TypeDef *)JL_CEMU_BASE)
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//............. 0x0300 - 0x03ff............
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#define MPU_INV (1<<31)
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#define MPU_PWEN (1<<16)
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#define MPU_PREN (1<<8)
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#define MPU_PEN (MPU_PWEN | MPU_PREN)
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#define MPU_XEN (1<<2)
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#define MPU_WEN (1<<1)
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#define MPU_REN (1<<0)
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#define MPU_IDx_cfg(n, id) (id<<(n*8))
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#define MPU_IDx_pen(n, pr, pw) ((pr<<(9+n)) | (pw<<(17+n)))
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typedef struct {
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__RW __u32 CON[15]; // 0-1 used in br35
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__RO __u32 REV0;
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__RW __u32 CID[15]; // 0-1 used in br35
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__RO __u32 REV1;
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__RW __u32 BEG[15]; // 0-1 used in br35
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__RO __u32 REV2;
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__RW __u32 END[15]; // 0-1 used in br35
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__RW __u32 WREN;
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} JL_MPU_TypeDef;
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#define JL_MPU_BASE (csfr_base + map_adr(0x03, 0x00))
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#define JL_MPU ((JL_MPU_TypeDef *)JL_MPU_BASE)
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//............. 0x0400 - 0x04ff............
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typedef struct {
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__RW __u32 CON;
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__RW __u32 TLB1_BEG;
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__RW __u32 TLB1_END;
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} JL_MMU_TypeDef;
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#define JL_MMU_BASE (csfr_base + map_adr(0x04, 0x00))
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#define JL_MMU ((JL_MMU_TypeDef *)JL_MMU_BASE)
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typedef struct {
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short page: 14;
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short vld: 1;
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} JL_MMU_TLB1_TypeDef;
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#define JL_MMU_TLB1 ((JL_MMU_TLB1_TypeDef *)(JL_MMU->TLB1_BEG))
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//............. 0x0500 - 0x05ff............
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//#define JL_TypeDef_L1P JL_TypeDef_q32DSP_ICU
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#define JL_TypeDef_L1P JL_TypeDef_q32DSP_DCU
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#define JL_L1P_BASE (csfr_base + map_adr(0x05, 0x00))
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#define JL_L1P ((JL_TypeDef_L1P *)JL_L1P_BASE)
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//............. 0x0600 - 0x06ff............
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#define JL_TypeDef_L2I JL_TypeDef_q32DSP_ICU
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#define JL_L2I_BASE (csfr_base + map_adr(0x06, 0x00))
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#define JL_L2I ((JL_TypeDef_L2I *)JL_L2I_BASE)
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//............. 0x0700 - 0x07ff............
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#define JL_TypeDef_L2D JL_TypeDef_q32DSP_DCU
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#define JL_L2D_BASE (csfr_base + map_adr(0x07, 0x00))
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#define JL_L2D ((JL_TypeDef_L2D *)JL_L2D_BASE)
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//............. 0x0800 - 0x08ff............
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typedef struct {
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__RO __u32 CHIP_ID;
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__RO __u32 CHIP_VER;
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} JL_SYSTEM_TypeDef;
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#define JL_SYSTEM_BASE (csfr_base + map_adr(0x08, 0x00))
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#define JL_SYSTEM ((JL_SYSTEM_TypeDef *)JL_SYSTEM_BASE)
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//............. 0x0900 - 0x09ff............
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typedef struct {
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__RW __u32 CON;
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__RW __u32 BEG;
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__RW __u32 END;
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__RW __u32 DAT_VLD0;
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__RW __u32 DAT_VLD1;
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__RW __u32 DAT_VLD2;
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__RW __u32 DAT_VLD3;
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__RO __u32 ROM_CRC;
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__RW __u32 MCFG0_SEL;
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__RW __u32 MCFG1_SEL;
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__RW __u32 MCFG0_RF1P;
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__RW __u32 MCFG0_RF2P;
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__RW __u32 MCFG0_RM1P;
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__RW __u32 MCFG0_RM2P;
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__RW __u32 MCFG0_VROM;
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__RW __u32 MCFG1_RM1P;
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__RW __u32 MCFG0_CON[2];
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__RW __u32 MCFG1_CON[2];
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} JL_MBIST_TypeDef;
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#define JL_MBIST_BASE (csfr_base + map_adr(0x09, 0x00))
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#define JL_MBIST ((JL_MBIST_TypeDef *)JL_MBIST_BASE)
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//............. 0x0a00 - 0x0aff............
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//typedef struct {
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// __RW __u32 CON;
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// __RW __u32 CADR;
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// __RW __u32 ACC0L;
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// __RW __u32 ACC0H;
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// __RW __u32 ACC1L;
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// __RW __u32 ACC1H;
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// __RW __u32 CONST;
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// __RW __u32 TEST1;
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//} JL_FFT_TypeDef;
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//
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//#define JL_FFT_BASE (csfr_base + map_adr(0x0a, 0x00))
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//#define JL_FFT ((JL_FFT_TypeDef *)JL_FFT_BASE)
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//............. 0x0b00 - 0x0bff............
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//typedef struct {
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///* 00 */ __RW __u32 CON0;
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///* 01 */ __RW __u32 LPEN_CON;
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///* 02 */ __RW __u32 LSEN_CON;
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///* 03 */ __RO __u32 LS_PND;
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///* 04 */ __RO __u32 CE_PND;
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///* 05 */ __RW __u32 LS_PRD_32K;
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///* 06 */ __RW __u32 CE_PRD_32K;
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///* 07 */ __RW __u32 LS_PRD_64K;
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///* 08 */ __RW __u32 CE_PRD_64K;
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///* 09 */ __RW __u32 LS_PRD_ROM;
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///* 0a */ __RW __u32 CE_PRD_ROM;
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//} JL_ATOLP_TypeDef;
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//#define JL_ATOLP_BASE (csfr_base + map_adr(0x0b, 0x00))
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//#define JL_ATOLP ((JL_ATOLP_TypeDef *)JL_ATOLP_BASE)
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//*********************************************************************************
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//
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// q32DSP_sfr
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//
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//*********************************************************************************
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//---------------------------------------------//
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// q32DSP define
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//---------------------------------------------//
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#define q32DSP_sfr_offset 0x000800
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#define q32DSP_sfr_base (csfr_base + 0xe000)
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#define q32DSP_cpu_base (q32DSP_sfr_base + 0x0000)
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#define q32DSP_icu_base (q32DSP_sfr_base + 0x0400)
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#define q32DSP(n) ((JL_TypeDef_q32DSP *)(q32DSP_sfr_base + q32DSP_sfr_offset*n))
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#define q32DSP_icu(n) ((JL_TypeDef_q32DSP_ICU *)(q32DSP_icu_base + q32DSP_sfr_offset*n))
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//---------------------------------------------//
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// q32DSP core sfr
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//---------------------------------------------//
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typedef struct {
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/* 00 */ __RO __u32 DR00;
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/* 01 */ __RO __u32 DR01;
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/* 02 */ __RO __u32 DR02;
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/* 03 */ __RO __u32 DR03;
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/* 04 */ __RO __u32 DR04;
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/* 05 */ __RO __u32 DR05;
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/* 06 */ __RO __u32 DR06;
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/* 07 */ __RO __u32 DR07;
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/* 08 */ __RO __u32 DR08;
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/* 09 */ __RO __u32 DR09;
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/* 0a */ __RO __u32 DR10;
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/* 0b */ __RO __u32 DR11;
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/* 0c */ __RO __u32 DR12;
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/* 0d */ __RO __u32 DR13;
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/* 0e */ __RO __u32 DR14;
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/* 0f */ __RO __u32 DR15;
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/* 10 */ __RO __u32 RETI;
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/* 11 */ __RO __u32 RETE;
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/* 12 */ __RO __u32 RETX;
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/* 13 */ __RO __u32 RETS;
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/* 14 */ __RO __u32 SR04;
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/* 15 */ __RO __u32 PSR;
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/* 16 */ __RO __u32 CNUM;
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/* 17 */ __RO __u32 SR07;
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/* 18 */ __RO __u32 SR08;
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/* 19 */ __RO __u32 SR09;
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/* 1a */ __RO __u32 SR10;
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/* 1b */ __RO __u32 ICFG;
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/* 1c */ __RO __u32 USP;
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/* 1d */ __RO __u32 SSP;
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/* 1e */ __RO __u32 SP;
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/* 1f */ __RO __u32 PCRS;
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/* 20 */ __RW __u32 BPCON;
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/* 21 */ __RW __u32 BSP;
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/* 22 */ __RW __u32 BP0;
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/* 23 */ __RW __u32 BP1;
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/* 24 */ __RW __u32 BP2;
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/* 25 */ __RW __u32 BP3;
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/* 26 */ __WO __u32 CMD_PAUSE;
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/* 27 */ __RW __u32 BP4;
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/* 28 */ __RW __u32 BP5;
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/* 29 */ __RW __u32 BP6;
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/* 2a */ __RW __u32 BP7;
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/* */ __RO __u32 REV2a[0x30 - 0x2a - 1];
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/* 30 */ __RW __u32 PMU_CON0;
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/* 31 */ __RW __u32 PMU_CON1;
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/* 32 */ __RO __u32 RST_ADDR;
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/* */ __RO __u32 REV32[0x3b - 0x32 - 1];
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/* 3b */ __RW __u8 TTMR_CON;
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/* 3c */ __RW __u32 TTMR_CNT;
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/* 3d */ __RW __u32 TTMR_PRD;
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/* */ __RO __u32 REV3d[0x40 - 0x3d - 1];
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/* 40 */ __RW __u32 ICFG00;
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/* 41 */ __RW __u32 ICFG01;
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/* 42 */ __RW __u32 ICFG02;
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/* 43 */ __RW __u32 ICFG03;
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/* 44 */ __RW __u32 ICFG04;
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/* 45 */ __RW __u32 ICFG05;
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/* 46 */ __RW __u32 ICFG06;
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/* 47 */ __RW __u32 ICFG07;
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/* 48 */ __RW __u32 ICFG08;
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/* 49 */ __RW __u32 ICFG09;
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/* 4a */ __RW __u32 ICFG10;
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/* 4b */ __RW __u32 ICFG11;
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/* 4c */ __RW __u32 ICFG12;
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/* 4d */ __RW __u32 ICFG13;
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/* 4e */ __RW __u32 ICFG14;
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/* 4f */ __RW __u32 ICFG15;
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/* 50 */ __RW __u32 ICFG16;
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/* 51 */ __RW __u32 ICFG17;
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/* 52 */ __RW __u32 ICFG18;
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/* 53 */ __RW __u32 ICFG19;
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/* 54 */ __RW __u32 ICFG20;
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/* 55 */ __RW __u32 ICFG21;
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/* 56 */ __RW __u32 ICFG22;
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/* 57 */ __RW __u32 ICFG23;
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/* 58 */ __RW __u32 ICFG24;
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/* 59 */ __RW __u32 ICFG25;
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/* 5a */ __RW __u32 ICFG26;
|
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/* 5b */ __RW __u32 ICFG27;
|
||||
/* 5c */ __RW __u32 ICFG28;
|
||||
/* 5d */ __RW __u32 ICFG29;
|
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/* 5e */ __RW __u32 ICFG30;
|
||||
/* 5f */ __RW __u32 ICFG31;
|
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|
||||
/* 60 */ __RO __u32 IPND0;
|
||||
/* 61 */ __RO __u32 IPND1;
|
||||
/* 62 */ __RO __u32 IPND2;
|
||||
/* 63 */ __RO __u32 IPND3;
|
||||
/* 64 */ __RO __u32 IPND4;
|
||||
/* 65 */ __RO __u32 IPND5;
|
||||
/* 66 */ __RO __u32 IPND6;
|
||||
/* 67 */ __RO __u32 IPND7;
|
||||
/* 68 */ __WO __u32 ILAT_SET;
|
||||
/* 69 */ __WO __u32 ILAT_CLR;
|
||||
/* 6a */ __RW __u32 IPMASK;
|
||||
/* 6b */ __RW __u32 GIEMASK;
|
||||
/* 6c */ __RW __u32 IWKUP_NUM;
|
||||
/* */ __RO __u32 REV6c[0x70 - 0x6c - 1];
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||||
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/* 70 */ __RW __u32 ETM_CON;
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/* 71 */ __RO __u32 ETM_PC0;
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/* 72 */ __RO __u32 ETM_PC1;
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||||
/* 73 */ __RO __u32 ETM_PC2;
|
||||
/* 74 */ __RO __u32 ETM_PC3;
|
||||
/* 75 */ __RW __u32 WP0_ADRH;
|
||||
/* 76 */ __RW __u32 WP0_ADRL;
|
||||
/* 77 */ __RW __u32 WP0_DATH;
|
||||
/* 78 */ __RW __u32 WP0_DATL;
|
||||
/* 79 */ __RO __u32 WP0_PC;
|
||||
/* 7a */ __RO __u32 WP0_AMSG;
|
||||
/* */ __RO __u32 REV7b[0x80 - 0x7a - 1];
|
||||
|
||||
/* 80 */ __RW __u32 EMU_CON;
|
||||
/* 81 */ __RW __u32 EMU_MSG;
|
||||
/* 82 */ __RW __u32 EMU_SSP_H;
|
||||
/* 83 */ __RW __u32 EMU_SSP_L;
|
||||
/* 84 */ __RW __u32 EMU_USP_H;
|
||||
/* 85 */ __RW __u32 EMU_USP_L;
|
||||
/* 86 */ __RW __u32 LIM_PC0_H;
|
||||
/* 87 */ __RW __u32 LIM_PC0_L;
|
||||
/* 88 */ __RW __u32 LIM_PC1_H;
|
||||
/* 89 */ __RW __u32 LIM_PC1_L;
|
||||
/* 8a */ __RW __u32 LIM_PC2_H;
|
||||
/* 8b */ __RW __u32 LIM_PC2_L;
|
||||
/* */ __RO __u32 REV8b[0x90 - 0x8b - 1];
|
||||
|
||||
/* 90 */ __RW __u32 ESU_CON;
|
||||
/* 91 */ __RO __u32 CNT_CHIT;
|
||||
/* 92 */ __RO __u32 CNT_CMIS;
|
||||
/* 93 */ __RO __u32 CNT_FILL;
|
||||
/* 94 */ __RO __u32 CNT_IHIT;
|
||||
/* 95 */ __RO __u32 CNT_IMIS;
|
||||
/* 96 */ __RO __u32 CNT_RHIT;
|
||||
/* 97 */ __RO __u32 CNT_RMIS;
|
||||
/* 98 */ __RO __u32 CNT_WHIT;
|
||||
/* 99 */ __RO __u32 CNT_WMIS;
|
||||
} JL_TypeDef_q32DSP;
|
||||
|
||||
//---------------------------------------------//
|
||||
// q32DSP icache sfr
|
||||
//---------------------------------------------//
|
||||
|
||||
typedef struct {
|
||||
__RW __u32 CON;
|
||||
__RW __u32 EMU_CON;
|
||||
__RW __u32 EMU_MSG;
|
||||
__RW __u32 EMU_ID;
|
||||
__RW __u32 CMD_CON;
|
||||
__RW __u32 CMD_BEG;
|
||||
__RW __u32 CMD_END;
|
||||
__RW __u32 CNT_RACK;
|
||||
__RW __u32 CNT_RNAK;
|
||||
__RW __u32 MBIST_SEL;
|
||||
__RW __u32 MCFG0_CON[2];
|
||||
} JL_TypeDef_q32DSP_ICU;
|
||||
|
||||
//---------------------------------------------//
|
||||
// q32DSP dcache sfr
|
||||
//---------------------------------------------//
|
||||
|
||||
typedef struct {
|
||||
__RW __u32 CON;
|
||||
__RW __u32 EMU_CON;
|
||||
__RW __u32 EMU_MSG;
|
||||
__RW __u32 EMU_ID;
|
||||
__RW __u32 CNT_WACK;
|
||||
__RW __u32 CNT_WNAK;
|
||||
__RW __u32 CNT_RACK;
|
||||
__RW __u32 CNT_RNAK;
|
||||
__RW __u32 CMD_CON[4];
|
||||
__RW __u32 CMD_BEG[4];
|
||||
__RW __u32 CMD_END[4];
|
||||
__RW __u32 MBIST_SEL;
|
||||
__RW __u32 MCFG0_CON[2];
|
||||
__RO __u32 REV1[0x20 - 0x16 - 1];
|
||||
__WO __u32 CMO[32];
|
||||
} JL_TypeDef_q32DSP_DCU;
|
||||
|
||||
#undef __RW
|
||||
#undef __RO
|
||||
#undef __WO
|
||||
|
||||
#undef __u8
|
||||
#undef __u16
|
||||
#undef __u32
|
||||
|
||||
//*********************************************************************************//
|
||||
// //
|
||||
// end of this module //
|
||||
// //
|
||||
//*********************************************************************************//
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,17 @@
|
||||
#ifndef __DELAY_H__
|
||||
#define __DELAY_H__
|
||||
|
||||
#include "typedef.h"
|
||||
|
||||
void udelay(u32 usec);
|
||||
|
||||
void mdelay(u32 msec);
|
||||
|
||||
void delay(volatile u32 t);
|
||||
|
||||
void rc_udelay(u32 usec);
|
||||
|
||||
void rc_mdelay(u32 msec);
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,788 @@
|
||||
/**
|
||||
* @file gpio.h
|
||||
* @brief
|
||||
* @author @zh-jieli.com
|
||||
* @version 1.0.0
|
||||
* @date 2018-10-11
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __GPIO_H__
|
||||
#define __GPIO_H__
|
||||
|
||||
#include "typedef.h"
|
||||
|
||||
#define IO_GROUP_NUM 16
|
||||
|
||||
|
||||
#define IO_PORTA_00 (IO_GROUP_NUM * 0 + 0)
|
||||
#define IO_PORTA_01 (IO_GROUP_NUM * 0 + 1)
|
||||
#define IO_PORTA_02 (IO_GROUP_NUM * 0 + 2)
|
||||
#define IO_PORTA_03 (IO_GROUP_NUM * 0 + 3)
|
||||
#define IO_PORTA_04 (IO_GROUP_NUM * 0 + 4)
|
||||
#define IO_PORTA_05 (IO_GROUP_NUM * 0 + 5)
|
||||
#define IO_PORTA_06 (IO_GROUP_NUM * 0 + 6)
|
||||
#define IO_PORTA_07 (IO_GROUP_NUM * 0 + 7)
|
||||
#define IO_PORTA_08 (IO_GROUP_NUM * 0 + 8)
|
||||
#define IO_PORTA_09 (IO_GROUP_NUM * 0 + 9)
|
||||
#define IO_PORTA_10 (IO_GROUP_NUM * 0 + 10)
|
||||
#define IO_PORTA_11 (IO_GROUP_NUM * 0 + 11)
|
||||
#define IO_PORTA_12 (IO_GROUP_NUM * 0 + 12)
|
||||
#define IO_PORTA_13 (IO_GROUP_NUM * 0 + 13)
|
||||
#define IO_PORT_PA_MASK 0x3fff
|
||||
|
||||
#define IO_PORTB_00 (IO_GROUP_NUM * 1 + 0)
|
||||
#define IO_PORTB_01 (IO_GROUP_NUM * 1 + 1)
|
||||
#define IO_PORTB_02 (IO_GROUP_NUM * 1 + 2)
|
||||
#define IO_PORTB_03 (IO_GROUP_NUM * 1 + 3)
|
||||
#define IO_PORTB_04 (IO_GROUP_NUM * 1 + 4)
|
||||
#define IO_PORTB_05 (IO_GROUP_NUM * 1 + 5)
|
||||
#define IO_PORTB_06 (IO_GROUP_NUM * 1 + 6)
|
||||
#define IO_PORTB_07 (IO_GROUP_NUM * 1 + 7)
|
||||
#define IO_PORTB_08 (IO_GROUP_NUM * 1 + 8)
|
||||
#define IO_PORT_PB_MASK 0x01ff
|
||||
|
||||
#define IO_PORTC_00 (IO_GROUP_NUM * 2 + 0)
|
||||
#define IO_PORTC_01 (IO_GROUP_NUM * 2 + 1)
|
||||
#define IO_PORTC_02 (IO_GROUP_NUM * 2 + 2)
|
||||
#define IO_PORTC_03 (IO_GROUP_NUM * 2 + 3)
|
||||
#define IO_PORTC_04 (IO_GROUP_NUM * 2 + 4)
|
||||
#define IO_PORTC_05 (IO_GROUP_NUM * 2 + 5)
|
||||
#define IO_PORTC_06 (IO_GROUP_NUM * 2 + 6)
|
||||
#define IO_PORTC_07 (IO_GROUP_NUM * 2 + 7)
|
||||
#define IO_PORTC_08 (IO_GROUP_NUM * 2 + 8)
|
||||
#define IO_PORTC_09 (IO_GROUP_NUM * 2 + 9)
|
||||
#define IO_PORTC_10 (IO_GROUP_NUM * 2 + 10)
|
||||
#define IO_PORTC_11 (IO_GROUP_NUM * 2 + 11)
|
||||
#define IO_PORT_PC_MASK 0x0fff
|
||||
|
||||
#define IO_PORTF_00 (IO_GROUP_NUM * 3 + 0)
|
||||
#define IO_PORTF_01 (IO_GROUP_NUM * 3 + 1)
|
||||
#define IO_PORTF_02 (IO_GROUP_NUM * 3 + 2)
|
||||
#define IO_PORTF_03 (IO_GROUP_NUM * 3 + 3)
|
||||
#define IO_PORTF_04 (IO_GROUP_NUM * 3 + 4)
|
||||
#define IO_PORTF_05 (IO_GROUP_NUM * 3 + 5)
|
||||
#define IO_PORT_PF_MASK 0x003f
|
||||
|
||||
#define IO_PORTP_00 (IO_GROUP_NUM * 4 + 0)
|
||||
#define IO_PORT_PP_MASK 0x0001
|
||||
|
||||
#define IO_PORT_LDOIN IO_PORTP_00
|
||||
|
||||
#define IO_MAX_NUM (IO_PORTP_00 + 1)
|
||||
|
||||
#define IO_PORT_DP (IO_GROUP_NUM * 5 + 0)
|
||||
#define IO_PORT_DM (IO_GROUP_NUM * 5 + 1)
|
||||
#define IO_PORT_USB_MASK 0x03
|
||||
#define IS_PORT_USB(x) (x <= IO_PORT_DM)//无usb赋0
|
||||
|
||||
//br50无pr
|
||||
// #define IO_PORT_PR_00 (IO_GROUP_NUM * 15 + 0)//pr固定15
|
||||
// #define IO_PORT_PR_01 (IO_GROUP_NUM * 15 + 1)
|
||||
// #define IO_PORT_PR_MASK 0x03
|
||||
|
||||
#define IO_PORT_MAX (IO_PORT_DM + 1)
|
||||
|
||||
#define P33_IO_OFFSET 0
|
||||
#define IO_CHGFL_DET (IO_PORT_MAX + P33_IO_OFFSET + 0)
|
||||
#define IO_VBGOK_DET (IO_PORT_MAX + P33_IO_OFFSET + 1)
|
||||
#define IO_VBTCH_DET (IO_PORT_MAX + P33_IO_OFFSET + 2)
|
||||
#define IO_LDOIN_DET (IO_PORT_MAX + P33_IO_OFFSET + 3)
|
||||
#define IO_VBATDT_DET (IO_PORT_MAX + P33_IO_OFFSET + 4)
|
||||
|
||||
#define PG_IO_OFFSET 5
|
||||
#define IO_LCD_PG (IO_PORT_MAX + PG_IO_OFFSET + 0)
|
||||
#define IO_MT_PG (IO_PORT_MAX + PG_IO_OFFSET + 1)
|
||||
#define IO_FS_PG2 (IO_PORT_MAX + PG_IO_OFFSET + 2)
|
||||
|
||||
|
||||
#define GPIOA (IO_GROUP_NUM * 0)
|
||||
#define GPIOB (IO_GROUP_NUM * 1)
|
||||
#define GPIOC (IO_GROUP_NUM * 2)
|
||||
#define GPIOF (IO_GROUP_NUM * 3)
|
||||
#define GPIOP (IO_GROUP_NUM * 4)
|
||||
#define GPIOUSB (IO_GROUP_NUM * 5)
|
||||
// #define GPIOR (IO_GROUP_NUM * 15) //br50 no pr
|
||||
#define GPIOP33 (IO_PORT_MAX + P33_IO_OFFSET)
|
||||
|
||||
|
||||
|
||||
|
||||
enum {
|
||||
INPUT_CH0,
|
||||
INPUT_CH1,
|
||||
INPUT_CH2,
|
||||
INPUT_CH3,
|
||||
};
|
||||
|
||||
enum {
|
||||
LOW_POWER_FREE = 0,
|
||||
LOW_POWER_KEEP = 1,
|
||||
};
|
||||
enum gpio_op_mode {
|
||||
GPIO_SET = 1,
|
||||
GPIO_AND,
|
||||
GPIO_OR,
|
||||
GPIO_XOR,
|
||||
};
|
||||
enum gpio_direction {
|
||||
GPIO_OUT = 0,
|
||||
GPIO_IN = 1,
|
||||
};
|
||||
struct gpio_reg {
|
||||
volatile unsigned int in;
|
||||
volatile unsigned int out;
|
||||
volatile unsigned int dir;
|
||||
volatile unsigned int die;
|
||||
volatile unsigned int dieh;
|
||||
volatile unsigned int pu0;
|
||||
volatile unsigned int pu1;
|
||||
volatile unsigned int pd0;
|
||||
volatile unsigned int pd1;
|
||||
volatile unsigned int hd0;
|
||||
volatile unsigned int hd1;
|
||||
volatile unsigned int spl;
|
||||
volatile unsigned int con;
|
||||
};
|
||||
|
||||
struct gpio_platform_data {
|
||||
unsigned int gpio;
|
||||
};
|
||||
|
||||
#define GPIO_PLATFORM_DATA_BEGIN(data) \
|
||||
static const struct gpio_platform_data data = { \
|
||||
|
||||
|
||||
#define GPIO_PLATFORM_DATA_END() \
|
||||
};
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief usb_iomode
|
||||
*
|
||||
* @param enable 1，使能；0，关闭
|
||||
*/
|
||||
void usb_iomode(u32 enable);
|
||||
/**
|
||||
* @brief gpio_direction_input
|
||||
*
|
||||
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
|
||||
* @param dir 1，输入；0，输出
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
int gpio_set_direction(u32 gpio, u32 dir);
|
||||
|
||||
|
||||
/**
|
||||
* @brief gpio_direction_input
|
||||
*
|
||||
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
|
||||
* @param value 1，输出1, 0，输出0
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
int gpio_set_output_value(u32 gpio, u32 dir);
|
||||
|
||||
/**
|
||||
* @brief gpio_dir
|
||||
*
|
||||
* @param gpio [GPIOA GPIOB GPIOC GPIOD GPIOR GPIOUSB]
|
||||
* @param start [0-15]，GPIOR[0-3]，GPIOUSB[0-1]
|
||||
* @param len [0-15]，GPIOR[0-3]，GPIOUSB[0-1]
|
||||
* @param dat 1，输入；0，输出
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_dir(u32 gpio, u32 start, u32 len, u32 dat, enum gpio_op_mode op);
|
||||
|
||||
/**
|
||||
* @brief gpio_direction_output
|
||||
*
|
||||
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
|
||||
* @param value 1，输出1；0，输出0
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
int gpio_direction_output(u32 gpio, int value);
|
||||
|
||||
/**
|
||||
* @brief gpio_out
|
||||
*
|
||||
* @param gpio [GPIOA GPIOB GPIOC GPIOD GPIOR GPIOUSB]
|
||||
* @param start [0-15]，GPIOR[0-3]，GPIOUSB[0-1]
|
||||
* @param len [0-15]，GPIOR[0-3]，GPIOUSB[0-1]
|
||||
* @param dat 1，输入；0，输出
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_out(u32 gpio, u32 start, u32 len, u32 dat);
|
||||
|
||||
/**
|
||||
* @brief gpio_set_pull_up
|
||||
*
|
||||
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
|
||||
* @param value 1，上拉；0，不上拉
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
int gpio_set_pull_up(u32 gpio, int value);
|
||||
|
||||
|
||||
/**
|
||||
* @brief gpio_set_pu
|
||||
*
|
||||
* @param gpio [GPIOA GPIOB GPIOC GPIOD GPIOR GPIOUSB]
|
||||
* @param start [0-15]，GPIOR[0-3]，GPIOUSB[0-1]
|
||||
* @param len [0-15]，GPIOR[0-3]，GPIOUSB[0-1]
|
||||
* @param dat 1，上拉；0，不上拉
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_set_pu0(u32 gpio, u32 start, u32 len, u32 dat, enum gpio_op_mode op);
|
||||
u32 gpio_set_pu1(u32 gpio, u32 start, u32 len, u32 dat, enum gpio_op_mode op);
|
||||
|
||||
/**
|
||||
* @brief gpio_set_pull_down
|
||||
*
|
||||
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
|
||||
* @param value 1，下拉；0，不下拉
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
int gpio_set_pull_down(u32 gpio, int value);
|
||||
|
||||
/**
|
||||
* @brief gpio_set_pd
|
||||
*
|
||||
* @param gpio [GPIOA GPIOB GPIOC GPIOD GPIOR GPIOUSB]
|
||||
* @param start [0-15]，GPIOR[0-3]，GPIOUSB[0-1]
|
||||
* @param len [0-15]，GPIOR[0-3]，GPIOUSB[0-1]
|
||||
* @param dat 1，下拉；0，不下拉
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_set_pd0(u32 gpio, u32 start, u32 len, u32 dat, enum gpio_op_mode op);
|
||||
u32 gpio_set_pd1(u32 gpio, u32 start, u32 len, u32 dat, enum gpio_op_mode op);
|
||||
|
||||
enum GPIO_HDRIVE {
|
||||
GPIO_HDRIVE_2_4_MA = 0, //2.4mA
|
||||
GPIO_HDRIVE_8_MA, //8mA
|
||||
GPIO_HDRIVE_26_4_MA, //26.4mA
|
||||
GPIO_HDRIVE_40_MA, //40mA
|
||||
};
|
||||
/**
|
||||
* @brief gpio_set_hd
|
||||
*
|
||||
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
|
||||
* @param value see enum GPIO_HDRIVE
|
||||
*
|
||||
* @return 0:ok, <0:fail
|
||||
*/
|
||||
int gpio_set_hd(u32 gpio, int value);
|
||||
|
||||
/**
|
||||
* @brief gpio_set_die
|
||||
*
|
||||
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
|
||||
* @param value 1，IO普通输入；0，IO模拟输入
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
int gpio_set_die(u32 gpio, int value);
|
||||
|
||||
/**
|
||||
* @brief gpio_set_dieh
|
||||
*
|
||||
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
|
||||
* @param value 1，IO普通输入；0，IO模拟输入
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_set_dieh(u32 gpio, u32 value);
|
||||
|
||||
/**
|
||||
* @brief gpio_die
|
||||
*
|
||||
* @param gpio [GPIOA GPIOB GPIOC GPIOD GPIOR GPIOUSB]
|
||||
* @param start [0-15]，GPIOR[0-3]，GPIOUSB[0-1]
|
||||
* @param len [0-15]，GPIOR[0-3]，GPIOUSB[0-1]
|
||||
* @param dat 1，IO普通输入；0，IO模拟输入
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_die(u32 gpio, u32 start, u32 len, u32 dat, enum gpio_op_mode op);
|
||||
|
||||
/**
|
||||
* @brief gpio_dieh
|
||||
*
|
||||
* @param gpio [GPIOA GPIOB GPIOC GPIOD GPIOR GPIOUSB]
|
||||
* @param start [0-15]，GPIOR[0-3]，GPIOUSB[0-1]
|
||||
* @param len [0-15]，GPIOR[0-3]，GPIOUSB[0-1]
|
||||
* @param dat 1，IO普通输入；0，IO模拟输入
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_dieh(u32 gpio, u32 start, u32 len, u32 dat, enum gpio_op_mode op);
|
||||
|
||||
/**
|
||||
* @brief gpio_set_output_channle
|
||||
*
|
||||
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
|
||||
* @param clk 参考枚举CHx_UTx_TX，如CH0_UT0_TX
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_output_channle(u32 gpio, u32 clk);
|
||||
|
||||
/**
|
||||
* @brief gpio_read
|
||||
*
|
||||
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
int gpio_read(u32 gpio);
|
||||
|
||||
/**
|
||||
* @brief gpio_in
|
||||
*
|
||||
* @param gpio [GPIOA GPIOB GPIOC GPIOD GPIOR GPIOUSB]
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_in(u32 gpio);
|
||||
/**
|
||||
* @brief gpio_write
|
||||
*
|
||||
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
|
||||
* @param value 1，输出1；0，输出0
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_write(u32 gpio, u32 value);
|
||||
|
||||
/**
|
||||
* @brief gpio_wakeup0 use IN_CHNL0_SEL
|
||||
*
|
||||
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_wakeup0(u32 gpio);
|
||||
|
||||
/**
|
||||
* @brief gpio_irflt_in use IN_CHNL1_SEL
|
||||
*
|
||||
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_irflt_in(u32 gpio);
|
||||
|
||||
/**
|
||||
* @brief gpio_cap_mux use IN_CHNL2_SEL
|
||||
*
|
||||
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_cap_mux(u32 gpio);
|
||||
|
||||
|
||||
/**
|
||||
* @brief gpio_uart_rx_input
|
||||
*
|
||||
* @param gpio
|
||||
* @param ut
|
||||
* @param ch
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_uart_rx_input(u32 gpio, u32 ut, u32 ch);
|
||||
|
||||
/**
|
||||
* @brief
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_close_uart0(void);
|
||||
|
||||
/**
|
||||
* @brief
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_close_uart1(void);
|
||||
|
||||
/**
|
||||
* @brief
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_close_uart2(void);
|
||||
|
||||
/**
|
||||
* @brief gpio_set_uart0
|
||||
*
|
||||
* @param ch 0:3 选择对应IO br22
|
||||
* |ch|tx|rx|
|
||||
* |- |- |- |
|
||||
* |0|PA5_TX|PA6_RX|
|
||||
* |1|PB7_TX|PB8_RX|
|
||||
* |2|PA7_TX|PA8_RX|
|
||||
* |3|预留|预留|
|
||||
* |-1|关闭对应的IO口串口功能|no|
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_set_uart0(u32 ch);
|
||||
/**
|
||||
* @brief gpio_set_uart1
|
||||
*
|
||||
* @param ch 0:3 选择对应IO br22
|
||||
* |ch|tx|rx|
|
||||
* |- |- |- |
|
||||
* |0|PB5_TX|PB6_RX|
|
||||
* |1|预留|预留|
|
||||
* |2|PA1_TX|PA2_RX|
|
||||
* |3|USBDP |USBDM |
|
||||
* |-1|关闭对应的IO口串口功能|no|
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_set_uart1(u32 ch);
|
||||
/**
|
||||
* @brief gpio_set_uart2
|
||||
*
|
||||
* @param ch 0:3 选择对应IO br22
|
||||
* |ch|tx|rx|
|
||||
* |- |- |- |
|
||||
* |0|PA3_TX|PA4_RX|
|
||||
* |1|预留|预留|
|
||||
* |2|预留|预留|
|
||||
* |3|PA9_TX|PA10_RX|
|
||||
* |-1|关闭对应的IO口串口功能|no|
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_set_uart2(u32 ch);
|
||||
|
||||
enum {
|
||||
IRFLT_LSB,
|
||||
// IRFLT_LSB,
|
||||
IRFLT_STD12M = 2,
|
||||
IRFLT_STD24M,
|
||||
};
|
||||
enum {
|
||||
IRFLT_DIV1,
|
||||
IRFLT_DIV2,
|
||||
IRFLT_DIV4,
|
||||
IRFLT_DIV8,
|
||||
IRFLT_DIV16,
|
||||
IRFLT_DIV32,
|
||||
IRFLT_DIV64,
|
||||
IRFLT_DIV128,
|
||||
IRFLT_DIV256,
|
||||
IRFLT_DIV512,
|
||||
IRFLT_DIV1024,
|
||||
IRFLT_DIV2048,
|
||||
IRFLT_DIV4096,
|
||||
IRFLT_DIV8192,
|
||||
IRFLT_DIV16384,
|
||||
IRFLT_DIV32768,
|
||||
};
|
||||
/* u32 irflt_config(u32 osc, u32 div); */
|
||||
|
||||
/**
|
||||
* @brief gpio_irflt_to_timer
|
||||
*
|
||||
* @param t: [0-3]
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_irflt_to_timer(u32 t);
|
||||
|
||||
|
||||
u32 get_gpio(const char *p);
|
||||
const char *gpio_get_name(u32 gpio);
|
||||
|
||||
//===================================================//
|
||||
// BR50 Crossbar API
|
||||
//===================================================//
|
||||
enum PFI_TABLE {
|
||||
PFI_GP_ICH0 = ((u32)(&(JL_IMAP->FI_GP_ICH0))),
|
||||
PFI_GP_ICH1 = ((u32)(&(JL_IMAP->FI_GP_ICH1))),
|
||||
PFI_GP_ICH2 = ((u32)(&(JL_IMAP->FI_GP_ICH2))),
|
||||
PFI_GP_ICH3 = ((u32)(&(JL_IMAP->FI_GP_ICH3))),
|
||||
PFI_GP_ICH4 = ((u32)(&(JL_IMAP->FI_GP_ICH4))),
|
||||
PFI_GP_ICH5 = ((u32)(&(JL_IMAP->FI_GP_ICH5))),
|
||||
PFI_SD0_CMD = ((u32)(&(JL_IMAP->FI_SD0_CMD))),
|
||||
PFI_SD0_DA0 = ((u32)(&(JL_IMAP->FI_SD0_DA0))),
|
||||
PFI_SD0_DA1 = ((u32)(&(JL_IMAP->FI_SD0_DA1))),
|
||||
PFI_SD0_DA2 = ((u32)(&(JL_IMAP->FI_SD0_DA2))),
|
||||
PFI_SD0_DA3 = ((u32)(&(JL_IMAP->FI_SD0_DA3))),
|
||||
|
||||
// PFI_SPI0_CLK = ((u32)(&(JL_IMAP->FI_SPI0_CLK))),
|
||||
// PFI_SPI0_DA0 = ((u32)(&(JL_IMAP->FI_SPI0_DA0))),
|
||||
// PFI_SPI0_DA1 = ((u32)(&(JL_IMAP->FI_SPI0_DA1))),
|
||||
// PFI_SPI0_DA2 = ((u32)(&(JL_IMAP->FI_SPI0_DA2))),
|
||||
// PFI_SPI0_DA3 = ((u32)(&(JL_IMAP->FI_SPI0_DA3))),
|
||||
PFI_SPI1_CLK = ((u32)(&(JL_IMAP->FI_SPI1_CLK))),
|
||||
PFI_SPI1_DA0 = ((u32)(&(JL_IMAP->FI_SPI1_DA0))),
|
||||
PFI_SPI1_DA1 = ((u32)(&(JL_IMAP->FI_SPI1_DA1))),
|
||||
PFI_SPI1_DA2 = ((u32)(&(JL_IMAP->FI_SPI1_DA2))),
|
||||
PFI_SPI1_DA3 = ((u32)(&(JL_IMAP->FI_SPI1_DA3))),
|
||||
PFI_SPI2_CLK = ((u32)(&(JL_IMAP->FI_SPI2_CLK))),
|
||||
PFI_SPI2_DA0 = ((u32)(&(JL_IMAP->FI_SPI2_DA0))),
|
||||
PFI_SPI2_DA1 = ((u32)(&(JL_IMAP->FI_SPI2_DA1))),
|
||||
|
||||
// PFI_SD0_DA1 = ((u32)(&(JL_IMAP->FI_SD0_DA1))),
|
||||
// PFI_SD0_DA2 = ((u32)(&(JL_IMAP->FI_SD0_DA2))),
|
||||
// PFI_SD0_DA3 = ((u32)(&(JL_IMAP->FI_SD0_DA3))),
|
||||
PFI_IIC0_SCL = ((u32)(&(JL_IMAP->FI_IIC0_SCL))),
|
||||
PFI_IIC0_SDA = ((u32)(&(JL_IMAP->FI_IIC0_SDA))),
|
||||
PFI_UART0_RX = ((u32)(&(JL_IMAP->FI_UART0_RX))),
|
||||
|
||||
PFI_UART1_RX = ((u32)(&(JL_IMAP->FI_UART1_RX))),
|
||||
|
||||
// PFI_UART1_CTS = ((u32)(&(JL_IMAP->FI_UART1_CTS))),
|
||||
PFI_UART2_RX = ((u32)(&(JL_IMAP->FI_UART2_RX))),
|
||||
// PFI_TDM_S_WCK = ((u32)(&(JL_IMAP->FI_TDM_S_WCK))),
|
||||
// PFI_TDM_S_BCK = ((u32)(&(JL_IMAP->FI_TDM_S_BCK))),
|
||||
// PFI_TDM_M_DA = ((u32)(&(JL_IMAP->FI_TDM_M_DA))),
|
||||
// PFI_RDEC0_DAT0 = ((u32)(&(JL_IMAP->FI_RDEC0_DAT0))),
|
||||
// PFI_RDEC0_DAT1 = ((u32)(&(JL_IMAP->FI_RDEC0_DAT1))),
|
||||
// PFI_RDEC1_DAT0 = ((u32)(&(JL_IMAP->FI_RDEC1_DAT0))),
|
||||
// PFI_RDEC1_DAT1 = ((u32)(&(JL_IMAP->FI_RDEC1_DAT1))),
|
||||
// PFI_RDEC2_DAT0 = ((u32)(&(JL_IMAP->FI_RDEC2_DAT0))),
|
||||
// PFI_RDEC2_DAT1 = ((u32)(&(JL_IMAP->FI_RDEC2_DAT1))),
|
||||
//PFI_ALNK0_MCLK = ((u32)(&(JL_IMAP->FI_ALNK0_MCLK))),
|
||||
//PFI_ALNK0_LRCK = ((u32)(&(JL_IMAP->FI_ALNK0_LRCK))),
|
||||
//PFI_ALNK0_SCLK = ((u32)(&(JL_IMAP->FI_ALNK0_SCLK))),
|
||||
//PFI_ALNK0_DAT0 = ((u32)(&(JL_IMAP->FI_ALNK0_DAT0))),
|
||||
//PFI_ALNK0_DAT1 = ((u32)(&(JL_IMAP->FI_ALNK0_DAT1))),
|
||||
//PFI_ALNK0_DAT2 = ((u32)(&(JL_IMAP->FI_ALNK0_DAT2))),
|
||||
//PFI_ALNK0_DAT3 = ((u32)(&(JL_IMAP->FI_ALNK0_DAT3))),
|
||||
//PFI_SPDIF_DIA = ((u32)(&(JL_IMAP->FI_SPDIF_DIA))),
|
||||
//PFI_SPDIF_DIB = ((u32)(&(JL_IMAP->FI_SPDIF_DIB))),
|
||||
//PFI_SPDIF_DIC = ((u32)(&(JL_IMAP->FI_SPDIF_DIC))),
|
||||
//PFI_SPDIF_DID = ((u32)(&(JL_IMAP->FI_SPDIF_DID))),
|
||||
//PFI_PLNK_DAT0 = ((u32)(&(JL_IMAP->FI_PLNK_DAT0))),
|
||||
//PFI_PLNK_DAT1 = ((u32)(&(JL_IMAP->FI_PLNK_DAT1))),
|
||||
//PFI_CAN_RX = ((u32)(&(JL_IMAP->FI_CAN_RX))),
|
||||
PFI_QDEC0_A = ((u32)(&(JL_IMAP->FI_QDEC0_A))),
|
||||
PFI_QDEC0_B = ((u32)(&(JL_IMAP->FI_QDEC0_B))),
|
||||
PFI_CHAIN_IN0 = ((u32)(&(JL_IMAP->FI_CHAIN_IN0))),
|
||||
PFI_CHAIN_IN1 = ((u32)(&(JL_IMAP->FI_CHAIN_IN1))),
|
||||
PFI_CHAIN_IN2 = ((u32)(&(JL_IMAP->FI_CHAIN_IN2))),
|
||||
PFI_CHAIN_IN3 = ((u32)(&(JL_IMAP->FI_CHAIN_IN3))),
|
||||
PFI_CHAIN_RST = ((u32)(&(JL_IMAP->FI_CHAIN_RST))),
|
||||
PFI_TOTAl = ((u32)(&(JL_IMAP->FI_TOTAL))),
|
||||
};
|
||||
|
||||
enum OUTPUT_CH_SIGNAL {
|
||||
OUTPUT_CH_SIGNAL_TIMER0_PWM,//8
|
||||
OUTPUT_CH_SIGNAL_TIMER1_PWM,
|
||||
OUTPUT_CH_SIGNAL_TIMER2_PWM,
|
||||
OUTPUT_CH_SIGNAL_TIMER3_PWM,
|
||||
OUTPUT_CH_SIGNAL_TIMER4_PWM,
|
||||
OUTPUT_CH_SIGNAL_TIMER5_PWM,
|
||||
OUTPUT_CH_SIGNAL_MCPWM0_H,
|
||||
OUTPUT_CH_SIGNAL_MCPWM0_L,
|
||||
OUTPUT_CH_SIGNAL_MCPWM1_H,
|
||||
OUTPUT_CH_SIGNAL_MCPWM1_L,
|
||||
OUTPUT_CH_SIGNAL_UART1_RTS,
|
||||
OUTPUT_CH_SIGNAL_CLOCK_OUT0,
|
||||
OUTPUT_CH_SIGNAL_CLOCK_OUT1,//br50无clk out1
|
||||
OUTPUT_CH_SIGNAL_CLOCK_OUT2,
|
||||
OUTPUT_CH_SIGNAL_GP_ICH0,
|
||||
OUTPUT_CH_SIGNAL_GP_ICH1,
|
||||
|
||||
OUTPUT_CH_SIGNAL_LEDC0_OUT = 32,
|
||||
OUTPUT_CH_SIGNAL_LEDC1_OUT = 33,
|
||||
};
|
||||
|
||||
enum INPUT_CH_TYPE {
|
||||
INPUT_CH_TYPE_GP_ICH = 0,
|
||||
INPUT_CH_TYPE_TIME2_PWM = 6,
|
||||
INPUT_CH_TYPE_TIME3_PWM,
|
||||
INPUT_CH_TYPE_MAX = 8,
|
||||
};
|
||||
|
||||
enum INPUT_CH_SIGNAL {
|
||||
//ICH_CON0
|
||||
INPUT_CH_SIGNAL_TIMER0_CIN = 0,//5
|
||||
INPUT_CH_SIGNAL_TIMER1_CIN,
|
||||
INPUT_CH_SIGNAL_TIMER2_CIN,
|
||||
INPUT_CH_SIGNAL_TIMER3_CIN,
|
||||
INPUT_CH_SIGNAL_TIMER4_CIN,
|
||||
INPUT_CH_SIGNAL_TIMER5_CIN,
|
||||
//ICH_CON1
|
||||
INPUT_CH_SIGNAL_TIMER0_CAPTURE,
|
||||
INPUT_CH_SIGNAL_TIMER1_CAPTURE,
|
||||
INPUT_CH_SIGNAL_TIMER2_CAPTURE,
|
||||
INPUT_CH_SIGNAL_TIMER3_CAPTURE,
|
||||
INPUT_CH_SIGNAL_TIMER4_CAPTURE,
|
||||
INPUT_CH_SIGNAL_TIMER5_CAPTURE,
|
||||
//ICH_CON2
|
||||
INPUT_CH_SIGNAL_MCPWM0_CK,
|
||||
INPUT_CH_SIGNAL_MCPWM1_CK,
|
||||
INPUT_CH_SIGNAL_MCPWM0_FP,
|
||||
INPUT_CH_SIGNAL_MCPWM1_FP,
|
||||
INPUT_CH_SIGNAL_IRFLT,
|
||||
INPUT_CH_SIGNAL_UART1_CTS,
|
||||
//ICH_CON3
|
||||
INPUT_CH_SIGNAL_QDEC_SIN0,
|
||||
INPUT_CH_SIGNAL_QDEC_SIN1,
|
||||
INPUT_CH_SIGNAL_WLC_EXT_ACT,
|
||||
INPUT_CH_SIGNAL_CAP,
|
||||
INPUT_CH_SIGNAL_CLK_PIN,
|
||||
INPUT_CH_SIGNAL_EXT_CLK,
|
||||
//ICH_CON4
|
||||
INPUT_CH_SIGNAL_AUD_DBG_DATI,
|
||||
INPUT_CH_SIGNAL_RESERVE0,
|
||||
INPUT_CH_SIGNAL_RESERVE1,
|
||||
INPUT_CH_SIGNAL_RESERVE2,
|
||||
INPUT_CH_SIGNAL_RESERVE3,
|
||||
INPUT_CH_SIGNAL_RESERVE4,
|
||||
};
|
||||
|
||||
|
||||
//=================================================================================//
|
||||
//@brief: CrossBar 获取某IO的输出映射寄存器
|
||||
//@input:
|
||||
// gpio: 需要输出外设信号的IO口; 如IO_PORTA_00
|
||||
//@return:
|
||||
// 输出映射寄存器地址; 如&(JL_OMAP->PA0_OUT)
|
||||
//=================================================================================//
|
||||
u32 *gpio2crossbar_outreg(u32 gpio);
|
||||
|
||||
//=================================================================================//
|
||||
//@brief: CrossBar 获取某IO的输入映射序号
|
||||
//@input:
|
||||
// gpio: 需要输出外设信号的IO口; 如IO_PORTA_00
|
||||
//@return:
|
||||
// 输出映射序号; 如PA0_IN
|
||||
//=================================================================================//
|
||||
u32 gpio2crossbar_inport(u32 gpio);
|
||||
|
||||
//=================================================================================//
|
||||
//@brief: CrossBar 输出设置 API, 将指定IO口设置为某个外设的输出
|
||||
//@input:
|
||||
// gpio: 需要输出外设信号的IO口;
|
||||
// fun_index: 需要输出到指定IO口的外设信号, 可以输出外设信号列表请查看io_omap.h文件;
|
||||
// dir_ctl: IO口方向由外设控制使能, 常设为1;
|
||||
// data_ctl: IO口电平状态由外设控制使能, 常设为1;
|
||||
// low_power_mode: 低功耗状态是否保持io功能;
|
||||
//@return:
|
||||
// 1)0: 执行正确;
|
||||
// 2)-EINVAL: 传参出错;
|
||||
//@note: 所映射的IO需要在设置IO状态为输出配置;
|
||||
//@example: 将UART0的Tx信号输出到IO_PORTA_05口:
|
||||
// gpio_direction_output(IO_PORTA_05, 1); //设置IO为输出状态
|
||||
// gpio_set_fun_output_port(IO_PORTA_05, FO_UART0_TX, 1, 1); //将UART0的Tx信号输出到IO_PORTA_05口
|
||||
//=================================================================================//
|
||||
int gpio_set_fun_output_port(u32 gpio, u32 fun_index, u8 dir_ctl, u8 data_ctl, u8 low_power_mode);
|
||||
|
||||
u32 gpio_get_ompap_low_power_mode(u32 offset);
|
||||
//=================================================================================//
|
||||
//@brief: CrossBar 输出设置 API, 将指定IO释放外设控制, 变为普通IO;
|
||||
//@input:
|
||||
// gpio: 需要释放外设控制IO口, 释放后变为普通IO模式;
|
||||
//@return:
|
||||
// 1)0: 执行正确;
|
||||
// 2)-EINVAL: 传参出错;
|
||||
//@note:
|
||||
//@example: 将IO_PORTA_05口被某一外设控制状态释放:
|
||||
// gpio_disable_fun_output_port(IO_PORTA_05);
|
||||
//=================================================================================//
|
||||
int gpio_disable_fun_output_port(u32 gpio);
|
||||
|
||||
//=================================================================================//
|
||||
//@brief: CrossBar 输入设置 API, 将某个外设的输入设置为从某个IO输入
|
||||
//@input:
|
||||
// gpio: 需要输入外设信号的IO口;
|
||||
// pfun: 需要从指定IO输入的外设信号, 可以输入的外设信号列表请查看gpio.h文件enum PFI_TABLE枚举项;
|
||||
// low_power_mode: 低功耗状态是否保持io功能;
|
||||
//@return:
|
||||
// 1)0: 执行正确;
|
||||
// 2)-EINVAL: 传参出错;
|
||||
//@note: 所映射的IO需要在设置IO状态为输入配置;
|
||||
//@example: 将UART0的Rx信号设置为IO_PORTA_05口输入:
|
||||
// gpio_set_die(IO_PORTA_05, 1); //数字输入使能
|
||||
// gpio_set_pull_up(IO_PORTA_05, 1); //上拉输入使能
|
||||
// gpio_direction_input(IO_PORTA_05); //设置IO为输入状态
|
||||
// gpio_set_fun_input_port(IO_PORTA_05, PFI_UART0_RX); //将UART0的Rx信号设置为IO_PORTA_05口输入
|
||||
//=================================================================================//
|
||||
int gpio_set_fun_input_port(u32 gpio, enum PFI_TABLE pfun, u32 low_power_mode);
|
||||
u32 gpio_get_impap_low_power_mode(u32 offset);
|
||||
|
||||
//=================================================================================//
|
||||
//@brief: CrossBar 输入设置 API, 将某个外设信号释放IO口控制, 变为普通IO;
|
||||
//@input:
|
||||
// pfun: 需要释放由某个IO口输入的外设信号, 外设信号列表请查看gpio.h文件enum PFI_TABLE枚举项;
|
||||
//@return: 默认为0, 无出错处理;
|
||||
//@note:
|
||||
//@example: 将外设信号PFI_UART0_RX释放由某个IO输入:
|
||||
// gpio_disable_fun_input_port(PFI_UART0_RX);
|
||||
//=================================================================================//
|
||||
int gpio_disable_fun_input_port(enum PFI_TABLE pfun);
|
||||
|
||||
//=================================================================================//
|
||||
//@brief: Output Channel输出设置 API, 将指定IO口设置为某个外设的输出
|
||||
//@input:
|
||||
// gpio: 需要输出外设信号的IO口;
|
||||
// signal: 将enum OUTPUT_CH_SIGNAL列表中需要输出到指定IO口的外设信号, 可以输出的外设信号列表请查看gpio.h文件的enum OUTPUT_CH_SIGNAL枚举项;
|
||||
//@return: 默认为0, 出错内部触发ASSERT;
|
||||
//@note: 所映射的IO需要在设置IO状态为输出配置;
|
||||
//@example: 将OUTPUT_CH_SIGNAL_MC_PWM0_H的Tx信号输出到IO_PORTA_05口:
|
||||
// gpio_direction_output(IO_PORTA_05, 1); //设置IO为输出状态
|
||||
// gpio_och_sel_output_signal(IO_PORTA_05, OUTPUT_CH_SIGNAL_MC_PWM0_H); //将OUTPUT_CH_SIGNAL_MC_PWM0_H信号输出到IO_PORTA_05口
|
||||
//=================================================================================//
|
||||
int gpio_och_sel_output_signal(u32 gpio, enum OUTPUT_CH_SIGNAL signal);
|
||||
|
||||
//=================================================================================//
|
||||
//@brief: Output Channel 输出设置 API, 将指定IO释放外设控制, 变为普通IO;
|
||||
//@input:
|
||||
// gpio: 需要释放外设控制IO口, 释放后变为普通IO模式;
|
||||
// signal: 将enum OUTPUT_CH_SIGNAL列表中需要取消输出的外设信号, 外设信号列表请查看gpio.h文件的enum OUTPUT_CH_SIGNAL枚举项;;
|
||||
//@return: 默认为0, 无出错处理;
|
||||
//@note:
|
||||
//@example: 将OUTPUT_CH_SIGNAL_MC_PWM0_H取消输出IO_PORTA_05:
|
||||
// gpio_och_disable_output_signal(IO_PORTA_05, OUTPUT_CH_SIGNAL_MC_PWM0_H);
|
||||
//=================================================================================//
|
||||
int gpio_och_disable_output_signal(u32 gpio, enum OUTPUT_CH_SIGNAL signal);
|
||||
|
||||
//=================================================================================//
|
||||
//@brief: Input Channel 输入设置 API, 将某个外设的输入设置为从某个IO输入
|
||||
//@input:
|
||||
// gpio: 需要输入外设信号的IO口;
|
||||
// signal: 需要从指定IO输入的外设信号, 可以输入的外设信号列表请查看gpio.h文件enum INPUT_CH_SIGNAL枚举项;
|
||||
// type: INPUT_CH 类型, 常设为INPUT_CH_TYPE_GP_ICH;
|
||||
//@return: 默认为0, 出错内部触发ASSERT;
|
||||
//@note: 所映射的IO需要在设置IO状态为输入配置;
|
||||
//@example: 将INPUT_CH_SIGNAL_TIMER0_CIN信号设置为IO_PORTA_05口输入:
|
||||
// gpio_set_die(IO_PORTA_05, 1); //数字输入使能
|
||||
// gpio_set_pull_up(IO_PORTA_05, 1); //上拉输入使能
|
||||
// gpio_direction_input(IO_PORTA_05); //设置IO为输入状态
|
||||
// gpio_ich_sel_input_signal(IO_PORTA_05, INPUT_CH_SIGNAL_TIMER0_CIN, INPUT_CH_TYPE_GP_ICH); //将INPUT_CH_SIGNAL_TIMER0_CIN信号设置为IO_PORTA_05口输入
|
||||
//=================================================================================//
|
||||
int gpio_ich_sel_input_signal(u32 gpio, enum INPUT_CH_SIGNAL signal, enum INPUT_CH_TYPE type);
|
||||
|
||||
//=================================================================================//
|
||||
//@brief: Input Channel 输入设置 API, 将某个外设信号释放IO口控制, 变为普通IO;
|
||||
//@input:
|
||||
// gpio: 需要取消输入外设信号的IO口;
|
||||
// signal: 需要取消输入的外设信号, 外设信号列表请查看gpio.h文件enum INPUT_CH_SIGNAL枚举项;
|
||||
// type: INPUT_CH 类型, 常设为INPUT_CH_TYPE_GP_ICH;
|
||||
//@return: 默认为0, 无出错处理;
|
||||
//@note:
|
||||
//@example: 将外设信号INPUT_CH_SIGNAL_TIMER0_CIN释放由某个IO输入:
|
||||
// gpio_ich_disable_input_signal(IO_PORTA_05, INPUT_CH_SIGNAL_TIMER0_CIN, INPUT_CH_TYPE_GP_ICH);
|
||||
//=================================================================================//
|
||||
int gpio_ich_disable_input_signal(u32 gpio, enum INPUT_CH_SIGNAL signal, enum INPUT_CH_TYPE type);
|
||||
|
||||
#endif /*GPIO_H*/
|
||||
|
||||
@@ -0,0 +1,91 @@
|
||||
|
||||
//===============================================================================//
|
||||
//
|
||||
// input IO define
|
||||
//
|
||||
//===============================================================================//
|
||||
#define PA0_IN 1
|
||||
#define PA1_IN 2
|
||||
#define PA2_IN 3
|
||||
#define PA3_IN 4
|
||||
#define PA4_IN 5
|
||||
#define PA5_IN 6
|
||||
#define PA6_IN 7
|
||||
#define PA7_IN 8
|
||||
#define PA8_IN 9
|
||||
#define PA9_IN 10
|
||||
#define PA10_IN 11
|
||||
#define PA11_IN 12
|
||||
#define PA12_IN 13
|
||||
#define PA13_IN 14
|
||||
#define PB0_IN 15
|
||||
#define PB1_IN 16
|
||||
#define PB2_IN 17
|
||||
#define PB3_IN 18
|
||||
#define PB4_IN 19
|
||||
#define PB5_IN 20
|
||||
#define PB6_IN 21
|
||||
#define PB7_IN 22
|
||||
#define PB8_IN 23
|
||||
#define PC0_IN 24
|
||||
#define PC1_IN 25
|
||||
#define PC2_IN 26
|
||||
#define PC3_IN 27
|
||||
#define PC4_IN 28
|
||||
#define PC5_IN 29
|
||||
#define PC6_IN 30
|
||||
#define PC7_IN 31
|
||||
#define PC8_IN 32
|
||||
#define PC9_IN 33
|
||||
#define PC10_IN 34
|
||||
#define PC11_IN 35
|
||||
#define USBDP_IN 36
|
||||
#define USBDM_IN 37
|
||||
#define PP0_IN 38
|
||||
|
||||
//===============================================================================//
|
||||
//
|
||||
// function input select sfr
|
||||
//
|
||||
//===============================================================================//
|
||||
typedef struct {
|
||||
__RW __u8 FI_GP_ICH0;
|
||||
__RW __u8 FI_GP_ICH1;
|
||||
__RW __u8 FI_GP_ICH2;
|
||||
__RW __u8 FI_GP_ICH3;
|
||||
__RW __u8 FI_GP_ICH4;
|
||||
__RW __u8 FI_GP_ICH5;
|
||||
__RW __u8 FI_SD0_CMD;
|
||||
__RW __u8 FI_SD0_DA0;
|
||||
__RW __u8 FI_SD0_DA1;
|
||||
__RW __u8 FI_SD0_DA2;
|
||||
__RW __u8 FI_SD0_DA3;
|
||||
__RW __u8 FI_SPI1_CLK;
|
||||
__RW __u8 FI_SPI1_DA0;
|
||||
__RW __u8 FI_SPI1_DA1;
|
||||
__RW __u8 FI_SPI1_DA2;
|
||||
__RW __u8 FI_SPI1_DA3;
|
||||
__RW __u8 FI_SPI2_CLK;
|
||||
__RW __u8 FI_SPI2_DA0;
|
||||
__RW __u8 FI_SPI2_DA1;
|
||||
__RW __u8 FI_SPI2_DA2;
|
||||
__RW __u8 FI_SPI2_DA3;
|
||||
__RW __u8 FI_IIC0_SCL;
|
||||
__RW __u8 FI_IIC0_SDA;
|
||||
__RW __u8 FI_UART0_RX;
|
||||
__RW __u8 FI_UART1_RX;
|
||||
__RW __u8 FI_UART2_RX;
|
||||
__RW __u8 FI_QDEC0_A;
|
||||
__RW __u8 FI_QDEC0_B;
|
||||
__RW __u8 FI_CHAIN_IN0;
|
||||
__RW __u8 FI_CHAIN_IN1;
|
||||
__RW __u8 FI_CHAIN_IN2;
|
||||
__RW __u8 FI_CHAIN_IN3;
|
||||
__RW __u8 FI_CHAIN_RST;
|
||||
__RW __u8 FI_TOTAL;
|
||||
} JL_IMAP_TypeDef;
|
||||
|
||||
#define JL_IMAP_BASE (ls_base + map_adr(0x3a, 0x00))
|
||||
#define JL_IMAP ((JL_IMAP_TypeDef *)JL_IMAP_BASE)
|
||||
|
||||
|
||||
@@ -0,0 +1,94 @@
|
||||
|
||||
//===============================================================================//
|
||||
//
|
||||
// output function define
|
||||
//
|
||||
//===============================================================================//
|
||||
#define FO_GP_OCH0 ((0 << 2)|BIT(1))
|
||||
#define FO_GP_OCH1 ((1 << 2)|BIT(1))
|
||||
#define FO_GP_OCH2 ((2 << 2)|BIT(1))
|
||||
#define FO_GP_OCH3 ((3 << 2)|BIT(1))
|
||||
#define FO_GP_OCH4 ((4 << 2)|BIT(1))
|
||||
#define FO_GP_OCH5 ((5 << 2)|BIT(1))
|
||||
#define FO_GP_OCH6 ((6 << 2)|BIT(1))
|
||||
#define FO_GP_OCH7 ((7 << 2)|BIT(1))
|
||||
#define FO_SD0_CLK ((8 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SD0_CMD ((9 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SD0_DA0 ((10 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SD0_DA1 ((11 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SD0_DA2 ((12 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SD0_DA3 ((13 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SPI1_CLK ((14 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SPI1_DA0 ((15 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SPI1_DA1 ((16 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SPI1_DA2 ((17 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SPI1_DA3 ((18 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SPI2_CLK ((19 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SPI2_DA0 ((20 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SPI2_DA1 ((21 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SPI2_DA2 ((22 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SPI2_DA3 ((23 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_IIC0_SCL ((24 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_IIC0_SDA ((25 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_UART0_TX ((26 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_UART1_TX ((27 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_UART2_TX ((28 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_MCPWM0_H ((29 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_MCPWM1_H ((30 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_MCPWM0_L ((31 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_MCPWM1_L ((32 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_CHAIN_OUT0 ((33 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_CHAIN_OUT1 ((34 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_CHAIN_OUT2 ((35 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_CHAIN_OUT3 ((36 << 2)|BIT(1)|BIT(0))
|
||||
|
||||
//===============================================================================//
|
||||
//
|
||||
// IO output select sfr
|
||||
//
|
||||
//===============================================================================//
|
||||
typedef struct {
|
||||
__RW __u8 PA0_OUT;
|
||||
__RW __u8 PA1_OUT;
|
||||
__RW __u8 PA2_OUT;
|
||||
__RW __u8 PA3_OUT;
|
||||
__RW __u8 PA4_OUT;
|
||||
__RW __u8 PA5_OUT;
|
||||
__RW __u8 PA6_OUT;
|
||||
__RW __u8 PA7_OUT;
|
||||
__RW __u8 PA8_OUT;
|
||||
__RW __u8 PA9_OUT;
|
||||
__RW __u8 PA10_OUT;
|
||||
__RW __u8 PA11_OUT;
|
||||
__RW __u8 PA12_OUT;
|
||||
__RW __u8 PA13_OUT;
|
||||
__RW __u8 PB0_OUT;
|
||||
__RW __u8 PB1_OUT;
|
||||
__RW __u8 PB2_OUT;
|
||||
__RW __u8 PB3_OUT;
|
||||
__RW __u8 PB4_OUT;
|
||||
__RW __u8 PB5_OUT;
|
||||
__RW __u8 PB6_OUT;
|
||||
__RW __u8 PB7_OUT;
|
||||
__RW __u8 PB8_OUT;
|
||||
__RW __u8 PC0_OUT;
|
||||
__RW __u8 PC1_OUT;
|
||||
__RW __u8 PC2_OUT;
|
||||
__RW __u8 PC3_OUT;
|
||||
__RW __u8 PC4_OUT;
|
||||
__RW __u8 PC5_OUT;
|
||||
__RW __u8 PC6_OUT;
|
||||
__RW __u8 PC7_OUT;
|
||||
__RW __u8 PC8_OUT;
|
||||
__RW __u8 PC9_OUT;
|
||||
__RW __u8 PC10_OUT;
|
||||
__RW __u8 PC11_OUT;
|
||||
__RW __u8 USBDP_OUT;
|
||||
__RW __u8 USBDM_OUT;
|
||||
__RW __u8 PP0_OUT;
|
||||
} JL_OMAP_TypeDef;
|
||||
|
||||
#define JL_OMAP_BASE (ls_base + map_adr(0x36, 0x00))
|
||||
#define JL_OMAP ((JL_OMAP_TypeDef *)JL_OMAP_BASE)
|
||||
|
||||
|
||||
@@ -0,0 +1,190 @@
|
||||
#ifndef __IRQ_H__
|
||||
#define __IRQ_H__
|
||||
|
||||
#include "typedef.h"
|
||||
|
||||
//=================================================
|
||||
#define IRQ_EMUEXCPT_IDX 0
|
||||
#define IRQ_EXCEPTION_IDX 1
|
||||
#define IRQ_SYSCALL_IDX 2
|
||||
#define IRQ_TICK_TMR_IDX 3
|
||||
#define IRQ_TIME0_IDX 4
|
||||
#define IRQ_TIME1_IDX 5
|
||||
#define IRQ_TIME2_IDX 6
|
||||
#define IRQ_UART0_IDX 7
|
||||
#define IRQ_UART1_IDX 8
|
||||
|
||||
#define IRQ_SPI1_IDX 10
|
||||
#define IRQ_IIC0_IDX 11
|
||||
#define IRQ_PORT_IDX 12
|
||||
#define IRQ_GPADC_IDX 13
|
||||
#define IRQ_UART2_IDX 14
|
||||
#define IRQ_LRCT_IDX 15
|
||||
|
||||
#define IRQ_GPCNT0_IDX 16
|
||||
#define IRQ_QDEC0_IDX 17
|
||||
#define IRQ_SD0_IDX 18
|
||||
#define IRQ_USB_SOF_IDX 19
|
||||
#define IRQ_USB_CTRL_IDX 20
|
||||
|
||||
#define IRQ_TIME3_IDX 22
|
||||
#define IRQ_LED_IDX 23
|
||||
#define IRQ_SD0_BRK_IDX 24
|
||||
#define IRQ_MCPWM_TMR_IDX 25
|
||||
#define IRQ_MCPWM_CHX_IDX 26
|
||||
#define IRQ_PMU_TMR0_IDX 27
|
||||
#define IRQ_PMU_TMR1_IDX 28
|
||||
|
||||
#define IRQ_SPI2_IDX 31
|
||||
|
||||
#define IRQ_P33_IDX 33
|
||||
#define IRQ_PINR_IDX 34
|
||||
#define IRQ_PMU_SOFT0_IDX 35
|
||||
#define IRQ_PMU_SOFT1_IDX 36
|
||||
#define IRQ_PMU_SOFT2_IDX 37
|
||||
#define IRQ_PMU_SOFT3_IDX 38
|
||||
|
||||
#define IRQ_PMU_TMR2_IDX 40
|
||||
#define IRQ_PMU_TMR3_IDX 41
|
||||
|
||||
#define IRQ_SRC0_IDX 66
|
||||
#define IRQ_SPI0_IDX 68
|
||||
|
||||
#define IRQ_DCP_IDX 70
|
||||
|
||||
#define IRQ_IMD_IDX 72
|
||||
#define IRQ_JPG_IDX 73
|
||||
#define IRQ_GPU_IDX 74
|
||||
|
||||
#define IRQ_ADC_IDX 88
|
||||
#define IRQ_AUDIO_IDX 89
|
||||
|
||||
#define IRQ_BT_TIMEBASE_IDX 100
|
||||
#define IRQ_BLE_RX_IDX 101
|
||||
#define IRQ_BLE_EVENT_IDX 102
|
||||
#define IRQ_BT_CLKN_IDX 103
|
||||
#define IRQ_BREDR_IDX 104
|
||||
#define IRQ_BT_RXMCH 105
|
||||
#define IRQ_SYNC_IDX 106
|
||||
|
||||
#define IRQ_SOFT0_IDX 120
|
||||
#define IRQ_SOFT1_IDX 121
|
||||
#define IRQ_SOFT2_IDX 122
|
||||
#define IRQ_SOFT3_IDX 123
|
||||
#define IRQ_SOFT4_IDX 124
|
||||
#define IRQ_SOFT5_IDX 125
|
||||
#define IRQ_SOFT6_IDX 126
|
||||
#define IRQ_SOFT7_IDX 127
|
||||
|
||||
#define MAX_IRQ_ENTRY_NUM 128
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
extern u32 _IRQ_MEM_ADDR[];
|
||||
#define IRQ_MEM_ADDR (_IRQ_MEM_ADDR)
|
||||
|
||||
extern int ISR_BASE;
|
||||
#define ISR_ENTRY (u32)&ISR_BASE
|
||||
|
||||
|
||||
|
||||
void interrupt_init();
|
||||
|
||||
|
||||
//---------------------------------------------//
|
||||
// interrupt cli/sti
|
||||
//---------------------------------------------//
|
||||
static inline int int_cli(void)
|
||||
{
|
||||
int msg;
|
||||
asm volatile("cli %0" : "=r"(msg) :);
|
||||
return msg;
|
||||
}
|
||||
|
||||
static inline void int_sti(int msg)
|
||||
{
|
||||
asm volatile("sti %0" :: "r"(msg));
|
||||
}
|
||||
|
||||
void irq_common_handler(u32 irq_idx);
|
||||
void irq_set_pending(u32 irq_idx);
|
||||
//---------------------------------------------//
|
||||
// low power waiting
|
||||
//---------------------------------------------//
|
||||
__attribute__((always_inline))
|
||||
static inline void lp_waiting(int *ptr, int pnd, int cpd, char inum)
|
||||
{
|
||||
#if 0
|
||||
q32DSP(core_num())->IWKUP_NUM = inum;
|
||||
while (!(*ptr & pnd)) {
|
||||
asm volatile("idle");
|
||||
}
|
||||
*ptr |= cpd;
|
||||
#else
|
||||
int con;
|
||||
q32DSP(core_num())->IWKUP_NUM = inum;
|
||||
asm volatile(
|
||||
" goto 2f \n\t"
|
||||
" 1: \n\t"
|
||||
" idle \n\t"
|
||||
" 2: \n\t"
|
||||
" %0 = [%1] \n\t"
|
||||
" rep 1 { \n\t" // disable_bpu
|
||||
" if((%0 & %2)==0) goto 1b \n\t"
|
||||
" } \n\t"
|
||||
:"=&r"(con)
|
||||
:"r"(ptr), "r"(pnd), "0"(con)
|
||||
:
|
||||
);
|
||||
*ptr = con | cpd;
|
||||
#endif
|
||||
}
|
||||
|
||||
// void irq_unmask_set(u8 index, u8 priority, u8 cpu_id);
|
||||
// bool irq_read(u32 index);
|
||||
|
||||
|
||||
|
||||
void bit_clr_ie(unsigned char index);
|
||||
void bit_set_ie(unsigned char index);
|
||||
void request_irq(u8 index, u8 priority, void (*handler)(void), u8 cpu_id);
|
||||
void unrequest_irq(u8 index);
|
||||
|
||||
void HWI_Install(unsigned int index, unsigned int isr, unsigned int priority);
|
||||
void reg_set_ip(unsigned char index, unsigned char priority, u8 cpu_id);
|
||||
void irq_init();
|
||||
void irq_set_pending(u32 irq_idx);
|
||||
void irq_common_handler(u32 irq_idx);
|
||||
|
||||
|
||||
void ENABLE_INT(void);
|
||||
#define enable_int ENABLE_INT
|
||||
|
||||
void DISABLE_INT(void);
|
||||
#define disable_int DISABLE_INT
|
||||
|
||||
void local_irq_disable();
|
||||
|
||||
void local_irq_enable();
|
||||
|
||||
|
||||
#ifdef IRQ_TIME_COUNT_EN
|
||||
|
||||
void irq_handler_enter(int irq);
|
||||
void irq_handler_exit(int irq);
|
||||
void irq_handler_times_dump();
|
||||
|
||||
#else
|
||||
|
||||
#define irq_handler_enter(irq) do { }while(0)
|
||||
#define irq_handler_exit(irq) do { }while(0)
|
||||
#define irq_handler_times_dump() do { }while(0)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,21 @@
|
||||
#ifndef __MASK_API_H__
|
||||
#define __MASK_API_H__
|
||||
|
||||
|
||||
#include "typedef.h"
|
||||
|
||||
#include "maskrom.h"
|
||||
|
||||
void exception_analyze(u32 *sp);
|
||||
|
||||
static void mask_api_init(void *pchar, void *exp_hook)
|
||||
{
|
||||
struct maskrom_argv table;
|
||||
memset((void *)&table, 0, sizeof(struct maskrom_argv));
|
||||
table.exp_hook = exp_hook;
|
||||
table.pchar = pchar;
|
||||
mask_init(&table);
|
||||
}
|
||||
|
||||
#endif /*MASK_API_H*/
|
||||
|
||||
@@ -0,0 +1,39 @@
|
||||
#ifndef __MASKROM_H__
|
||||
#define __MASKROM_H__
|
||||
|
||||
struct os_argv_table {
|
||||
void *f;
|
||||
void *m;
|
||||
void *stack_free;
|
||||
void *stack_malloc;
|
||||
void *log_e;
|
||||
void *enter_critical;
|
||||
void *exit_critical;
|
||||
void *get_ms;
|
||||
void *cpu_task_sw;
|
||||
int (*cpu_irq_disabled)(void);
|
||||
void *jiffies_addr;
|
||||
void *jiffies_unit_addr;
|
||||
void *task_info_update_runtime;
|
||||
|
||||
struct xbuf_lock_api {
|
||||
void *lock_init;
|
||||
void *lock;
|
||||
void *unlock;
|
||||
} lock;
|
||||
|
||||
};
|
||||
|
||||
struct maskrom_argv {
|
||||
void (*pchar)(char);
|
||||
void (*exp_hook)(u32 *);
|
||||
void (*local_irq_enable)();
|
||||
void (*local_irq_disable)();
|
||||
|
||||
char *(*flt)(char **str, char *end, double num, int size, int precision, char fmt, int flags);
|
||||
struct os_argv_table os_argv;
|
||||
};
|
||||
|
||||
void mask_init(const struct maskrom_argv *argv);
|
||||
|
||||
#endif /*MASKROM_H*/
|
||||
@@ -0,0 +1,209 @@
|
||||
__local_irq_enable = ABSOLUTE(0xffd5c);
|
||||
__local_irq_disable = ABSOLUTE(0xffd60);
|
||||
request_irq = ABSOLUTE(0xffd64);
|
||||
lp_signature_set = ABSOLUTE(0xffd68);
|
||||
memcpy = ABSOLUTE(0xffd6c);
|
||||
memmove = ABSOLUTE(0xffd70);
|
||||
memcmp = ABSOLUTE(0xffd74);
|
||||
memset = ABSOLUTE(0xffd78);
|
||||
memchr = ABSOLUTE(0xffd7c);
|
||||
strcmp = ABSOLUTE(0xffd80);
|
||||
strcpy = ABSOLUTE(0xffd84);
|
||||
strncpy = ABSOLUTE(0xffd88);
|
||||
strlen = ABSOLUTE(0xffd8c);
|
||||
strncmp = ABSOLUTE(0xffd90);
|
||||
strstr = ABSOLUTE(0xffd94);
|
||||
strchr = ABSOLUTE(0xffd98);
|
||||
strrchr = ABSOLUTE(0xffd9c);
|
||||
strcat = ABSOLUTE(0xffda0);
|
||||
__divdi3 = ABSOLUTE(0xffda4);
|
||||
__umoddi3 = ABSOLUTE(0xffda8);
|
||||
__muldi3 = ABSOLUTE(0xffdac);
|
||||
__udivdi3 = ABSOLUTE(0xffdb0);
|
||||
__udivmoddi4 = ABSOLUTE(0xffdb4);
|
||||
ic_pll_init = ABSOLUTE(0xffdb8);
|
||||
sfc_suspend = ABSOLUTE(0xffdbc);
|
||||
sfc_resume = ABSOLUTE(0xffdc0);
|
||||
sfc_drop_cache = ABSOLUTE(0xffdc4);
|
||||
sfc_boot = ABSOLUTE(0xffdc8);
|
||||
sfc_entry_continue_mode = ABSOLUTE(0xffdcc);
|
||||
ota_jump_mode = ABSOLUTE(0xffdd0);
|
||||
DcuInitial = ABSOLUTE(0xffdd4);
|
||||
DcuFlushinvAll = ABSOLUTE(0xffdd8);
|
||||
DcuWaitIdle = ABSOLUTE(0xffddc);
|
||||
IcuInitial = ABSOLUTE(0xffde0);
|
||||
IcuFlushinvAll = ABSOLUTE(0xffde4);
|
||||
IcuWaitIdle = ABSOLUTE(0xffde8);
|
||||
DcuEnable = ABSOLUTE(0xffdec);
|
||||
DcuFlushRegion = ABSOLUTE(0xffdf0);
|
||||
chip_crc16 = ABSOLUTE(0xffdf4);
|
||||
CrcDecode = ABSOLUTE(0xffdf8);
|
||||
mask_init = ABSOLUTE(0xffdfc);
|
||||
wdt_clear = ABSOLUTE(0xffe00);
|
||||
nvram_set_boot_state = ABSOLUTE(0xffe04);
|
||||
chip_reset = ABSOLUTE(0xffe08);
|
||||
flash_poweron = ABSOLUTE(0xffe0c);
|
||||
flash_poweron_base = ABSOLUTE(0xffe10);
|
||||
flash_poweroff = ABSOLUTE(0xffe14);
|
||||
flash_poweroff_base = ABSOLUTE(0xffe18);
|
||||
spi_io_mount = ABSOLUTE(0xffe1c);
|
||||
spi_io_unmount = ABSOLUTE(0xffe20);
|
||||
get_sfc_read_mode = ABSOLUTE(0xffe24);
|
||||
spi_port_io_init = ABSOLUTE(0xffe28);
|
||||
spi_port_io_uninit = ABSOLUTE(0xffe2c);
|
||||
usb_slave_mode = ABSOLUTE(0xffe30);
|
||||
uart_set_dma_dir = ABSOLUTE(0xffe34);
|
||||
doe = ABSOLUTE(0xffe38);
|
||||
LZ4_setStreamDecode = ABSOLUTE(0xffe3c);
|
||||
LZ4_decompress_safe_continue = ABSOLUTE(0xffe40);
|
||||
LZ4_decompress_generic = ABSOLUTE(0xffe44);
|
||||
LZ4_decompress_safe_usingDict = ABSOLUTE(0xffe48);
|
||||
dec_isd_cfg_ini = ABSOLUTE(0xffe4c);
|
||||
rom_nand_flash_get_features = ABSOLUTE(0xffe50);
|
||||
rom_nand_flash_set_features = ABSOLUTE(0xffe54);
|
||||
pcTaskName = ABSOLUTE(0xffe58);
|
||||
uxTaskStack = ABSOLUTE(0xffe5c);
|
||||
uxTaskStackDepth = ABSOLUTE(0xffe60);
|
||||
OSCtxSw2 = ABSOLUTE(0xffe64);
|
||||
OSCtxSw = ABSOLUTE(0xffe68);
|
||||
os_init = ABSOLUTE(0xffe6c);
|
||||
os_current_task_prio = ABSOLUTE(0xffe70);
|
||||
os_current_task_stask_size = ABSOLUTE(0xffe74);
|
||||
os_time_get = ABSOLUTE(0xffe78);
|
||||
os_task_create_static = ABSOLUTE(0xffe7c);
|
||||
os_task_coreaffinityset = ABSOLUTE(0xffe80);
|
||||
os_task_create_affinity_core = ABSOLUTE(0xffe84);
|
||||
os_task_create = ABSOLUTE(0xffe88);
|
||||
os_time_dly = ABSOLUTE(0xffe8c);
|
||||
os_task_del_req = ABSOLUTE(0xffe90);
|
||||
os_task_del_res = ABSOLUTE(0xffe94);
|
||||
os_task_del = ABSOLUTE(0xffe98);
|
||||
os_taskq_post = ABSOLUTE(0xffe9c);
|
||||
os_taskq_accept = ABSOLUTE(0xffea0);
|
||||
__os_taskq_pend = ABSOLUTE(0xffea4);
|
||||
os_sem_create = ABSOLUTE(0xffea8);
|
||||
os_sem_del = ABSOLUTE(0xffeac);
|
||||
os_sem_pend = ABSOLUTE(0xffeb0);
|
||||
os_sem_post = ABSOLUTE(0xffeb4);
|
||||
os_sem_set = ABSOLUTE(0xffeb8);
|
||||
os_sem_query = ABSOLUTE(0xffebc);
|
||||
os_sem_valid = ABSOLUTE(0xffec0);
|
||||
os_mutex_create = ABSOLUTE(0xffec4);
|
||||
os_mutex_del = ABSOLUTE(0xffec8);
|
||||
os_mutex_pend = ABSOLUTE(0xffecc);
|
||||
os_mutex_post = ABSOLUTE(0xffed0);
|
||||
os_mutex_valid = ABSOLUTE(0xffed4);
|
||||
os_q_create = ABSOLUTE(0xffed8);
|
||||
os_q_del = ABSOLUTE(0xffedc);
|
||||
os_q_flush = ABSOLUTE(0xffee0);
|
||||
os_taskq_flush = ABSOLUTE(0xffee4);
|
||||
os_q_pend = ABSOLUTE(0xffee8);
|
||||
os_q_recv = ABSOLUTE(0xffeec);
|
||||
os_q_peek = ABSOLUTE(0xffef0);
|
||||
os_q_post = ABSOLUTE(0xffef4);
|
||||
os_q_post_to_back = ABSOLUTE(0xffef8);
|
||||
os_q_post_to_front = ABSOLUTE(0xffefc);
|
||||
os_q_query = ABSOLUTE(0xfff00);
|
||||
os_q_valid = ABSOLUTE(0xfff04);
|
||||
os_task_get_handle = ABSOLUTE(0xfff08);
|
||||
OSInit = ABSOLUTE(0xfff0c);
|
||||
OSSchedLock = ABSOLUTE(0xfff10);
|
||||
OSSchedUnlock = ABSOLUTE(0xfff14);
|
||||
OSIdleOtherCore = ABSOLUTE(0xfff18);
|
||||
OSResumOtherCore = ABSOLUTE(0xfff1c);
|
||||
os_time_tick = ABSOLUTE(0xfff20);
|
||||
OS_SchedRoundRobin = ABSOLUTE(0xfff24);
|
||||
OS_EventTaskRdy = ABSOLUTE(0xfff28);
|
||||
OS_EventTaskWait = ABSOLUTE(0xfff2c);
|
||||
OS_EventTO = ABSOLUTE(0xfff30);
|
||||
OS_Sched = ABSOLUTE(0xfff34);
|
||||
OSUpdateIdleTime = ABSOLUTE(0xfff38);
|
||||
prvGetExpectedIdleTime = ABSOLUTE(0xfff3c);
|
||||
os_taskq_post_msg = ABSOLUTE(0xfff40);
|
||||
os_taskq_post_event = ABSOLUTE(0xfff44);
|
||||
os_taskq_post_type = ABSOLUTE(0xfff48);
|
||||
task_queue_post_event = ABSOLUTE(0xfff4c);
|
||||
task_queue_post_msg = ABSOLUTE(0xfff50);
|
||||
task_queue_post = ABSOLUTE(0xfff54);
|
||||
OSTaskQFlush = ABSOLUTE(0xfff58);
|
||||
__OSTaskQFlushMsg = ABSOLUTE(0xfff5c);
|
||||
os_taskq_pend = ABSOLUTE(0xfff60);
|
||||
os_taskq_pend_timeout = ABSOLUTE(0xfff64);
|
||||
os_current_task_rom = ABSOLUTE(0xfff68);
|
||||
OSTimeDly = ABSOLUTE(0xfff6c);
|
||||
OSTimeDlyResume = ABSOLUTE(0xfff70);
|
||||
OSTimeGet = ABSOLUTE(0xfff74);
|
||||
OSTimeSet = ABSOLUTE(0xfff78);
|
||||
OSTCBCur = ABSOLUTE(0x100328);
|
||||
OSRunning = ABSOLUTE(0x100320);
|
||||
OSRdyTbl = ABSOLUTE(0x10031c);
|
||||
OSIdleCtr = ABSOLUTE(0x100318);
|
||||
OSTCBHighRdy = ABSOLUTE(0x100324);
|
||||
OSTCBPrioTbl = ABSOLUTE(0x10032c);
|
||||
idle_tcb = ABSOLUTE(0x100430);
|
||||
OSLockNesting = ABSOLUTE(0x100314);
|
||||
OSNextTaskUnblockTime = ABSOLUTE(0x10042c);
|
||||
cpu1_run_flag = ABSOLUTE(0x10048c);
|
||||
OS_Affinity_Enable = ABSOLUTE(0x1002d2);
|
||||
MASK_CONFIG_CPU_UNMASK_IRQ_ENABLE = ABSOLUTE(0x1002d0);
|
||||
OS_Sw_Sf_Irq_Num = ABSOLUTE(0x1002d1);
|
||||
OSTaskCreate = ABSOLUTE(0xfff7c);
|
||||
os_taskq_del_type = ABSOLUTE(0xfff80);
|
||||
pmalloc_init = ABSOLUTE(0xfff84);
|
||||
pmalloc = ABSOLUTE(0xfff88);
|
||||
pfree = ABSOLUTE(0xfff8c);
|
||||
pmalloc_get_unused_pages = ABSOLUTE(0xfff90);
|
||||
get_physic_address = ABSOLUTE(0xfff94);
|
||||
pmalloc_get_hdl = ABSOLUTE(0xfff98);
|
||||
vmm_init_ = ABSOLUTE(0xfff9c);
|
||||
vmalloc_ = ABSOLUTE(0xfffa0);
|
||||
vfree_ = ABSOLUTE(0xfffa4);
|
||||
vmem_get_phy_adr = ABSOLUTE(0xfffa8);
|
||||
vmem_start = ABSOLUTE(0xfffac);
|
||||
vmem_end = ABSOLUTE(0xfffb0);
|
||||
vmalloc_get_hdl = ABSOLUTE(0xfffb4);
|
||||
vmalloc_v2 = ABSOLUTE(0xfffb8);
|
||||
vfree_v2 = ABSOLUTE(0xfffbc);
|
||||
vcopy_ = ABSOLUTE(0xfffc0);
|
||||
lock_vir_mem = ABSOLUTE(0xfffc4);
|
||||
unlock_vir_mem = ABSOLUTE(0xfffc8);
|
||||
hw_mmu_disable = ABSOLUTE(0xfffcc);
|
||||
get_sbc_frame_info = ABSOLUTE(0xfffd0);
|
||||
get_sbc_dec_ops = ABSOLUTE(0xfffd4);
|
||||
sbc_dec_loop_u = ABSOLUTE(0xfffd8);
|
||||
sbc_unpack_frame_u = ABSOLUTE(0xfffdc);
|
||||
sbc_synthesize_audio_u = ABSOLUTE(0xfffe0);
|
||||
sbc_oput_deal_normal = ABSOLUTE(0xfffe4);
|
||||
sbc_oput_deal_To_ch2 = ABSOLUTE(0xfffe8);
|
||||
sbc_bit_offset4 = ABSOLUTE(0xf88c0);
|
||||
sbc_bit_offset8 = ABSOLUTE(0xf8900);
|
||||
sbc_proto4_m0 = ABSOLUTE(0xf8980);
|
||||
sbc_proto4_m1 = ABSOLUTE(0xf89d0);
|
||||
sbc_proto8_m0 = ABSOLUTE(0xf8a20);
|
||||
sbc_proto8_m1 = ABSOLUTE(0xf8ac0);
|
||||
syn_matrix4 = ABSOLUTE(0xf8b60);
|
||||
syn_matrix8 = ABSOLUTE(0xf8be0);
|
||||
crc8_table = ABSOLUTE(0xf87c0);
|
||||
sbc_div_new_table = ABSOLUTE(0xf8de0);
|
||||
need_fix_iir_filter_buf = ABSOLUTE(0xfffec);
|
||||
fix_iir_filter_init = ABSOLUTE(0xffff0);
|
||||
fix_iir_filter_update = ABSOLUTE(0xffff4);
|
||||
fix_iir_filter_run = ABSOLUTE(0xffff8);
|
||||
fix_iir_filter_clear_mem = ABSOLUTE(0xffffc);
|
||||
_SFC_MEMORY_START_ADDR = ABSOLUTE(0xc000000);
|
||||
_IRQ_MEM_ADDR = ABSOLUTE(0x100000);
|
||||
_RAM_LIMIT_L = ABSOLUTE(0x100000);
|
||||
_RAM_LIMIT_H = ABSOLUTE(0x137000);
|
||||
_MASK_USED_MEM_END = ABSOLUTE(0x101310);
|
||||
_MASK_EXPORT_MEM_BEGIN = ABSOLUTE(0x100200);
|
||||
_MASK_EXPORT_MEM_SIZE = ABSOLUTE(0x34c);
|
||||
_UBOOT_LOADER_RAM_START = ABSOLUTE(0x102600);
|
||||
_UBOOT_LOADER_RAM_END = ABSOLUTE(0x137000);
|
||||
_UBOOT_LOADER_RAM_SIZE = ABSOLUTE(0x34a00);
|
||||
g_boot_soft_flag = ABSOLUTE(0x100204);
|
||||
irq_lock_cnt = ABSOLUTE(0x1002b8);
|
||||
efuse_page0 = ABSOLUTE(0x1002ac);
|
||||
efuse_page1 = ABSOLUTE(0x1002b0);
|
||||
efuse_page2 = ABSOLUTE(0x1002b4);
|
||||
nvram_list = ABSOLUTE(0x100214);
|
||||
/* exception_irq_handler = ABSOLUTE(0xf8004); */
|
||||
@@ -0,0 +1,67 @@
|
||||
#ifndef __P33_H__
|
||||
#define __P33_H__
|
||||
|
||||
|
||||
#include "typedef.h"
|
||||
|
||||
#include "p33_sfr.h"
|
||||
|
||||
#include "p33_app.h"
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
// lvd
|
||||
//
|
||||
//
|
||||
//
|
||||
/****************************************************************/
|
||||
typedef enum {
|
||||
LVD_RESET_MODE, //复位模式
|
||||
LVD_EXCEPTION_MODE, //异常模式，进入异常中断
|
||||
LVD_WAKEUP_MODE, //唤醒模式，进入唤醒中断，callback参数为回调函数
|
||||
} LVD_MODE;
|
||||
|
||||
typedef enum {
|
||||
VLVD_SEL_166V = 0,
|
||||
VLVD_SEL_177V,
|
||||
VLVD_SEL_188V,
|
||||
VLVD_SEL_199V,
|
||||
VLVD_SEL_210V,
|
||||
VLVD_SEL_221V,
|
||||
VLVD_SEL_232V,
|
||||
VLVD_SEL_243V,
|
||||
VLVD_SEL_254V,
|
||||
VLVD_SEL_265V,
|
||||
VLVD_SEL_276V,
|
||||
VLVD_SEL_287V,
|
||||
VLVD_SEL_298V,
|
||||
VLVD_SEL_309V,
|
||||
VLVD_SEL_320V,
|
||||
VLVD_SEL_331V,
|
||||
} LVD_VOL;
|
||||
|
||||
void lvd_config(LVD_VOL vol, u8 expin_en, LVD_MODE mode, void (*callback));
|
||||
void reset_pin_open(void);
|
||||
void reset_pin_close(void);
|
||||
void reset_pin_init(u32 pin, u32 level, u32 time);
|
||||
void reset_pin1_init(u32 pin, u32 level, u32 time);
|
||||
|
||||
void chip_reset();
|
||||
|
||||
void set_vddio_level(u8 level);
|
||||
|
||||
void set_dvdd_leve(u8 level);
|
||||
|
||||
void set_dcvdd_leve(u8 level);
|
||||
|
||||
void p33_soft_reset(void);
|
||||
|
||||
void latch_reset(void);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,825 @@
|
||||
#ifndef __P33_APP_H__
|
||||
#define __P33_APP_H__
|
||||
|
||||
|
||||
#include "typedef.h"
|
||||
|
||||
#include "p33_sfr.h"
|
||||
|
||||
|
||||
//=============================================================//
|
||||
// P33 SFR //
|
||||
//=============================================================//
|
||||
|
||||
//ROM
|
||||
u8 p33_buf(u8 buf);
|
||||
|
||||
#define p33_xor_1byte(addr, data0) (*((volatile u8 *)&addr + 0x300*4) = data0); asm volatile ("csync")
|
||||
//#define p33_xor_1byte(addr, data0) (*((volatile u8 *)&addr + 0x300*4) = data0)
|
||||
// #define p33_xor_1byte(addr, data0) addr ^= (data0)
|
||||
|
||||
#define p33_or_1byte(addr, data0) (*((volatile u8 *)&addr + 0x200*4) = data0); asm volatile ("csync")
|
||||
//#define p33_or_1byte(addr, data0) (*((volatile u8 *)&addr + 0x200*4) = data0)
|
||||
// #define p33_or_1byte(addr, data0) addr |= (data0)
|
||||
|
||||
#define p33_and_1byte(addr, data0) (*((volatile u8 *)&addr + 0x100*4) = (data0)); asm volatile ("csync")
|
||||
//#define p33_and_1byte(addr, data0) (*((volatile u8 *)&addr + 0x100*4) = (data0))
|
||||
//#define p33_and_1byte(addr, data0) addr &= (data0)
|
||||
|
||||
// void p33_tx_1byte(u16 addr, u8 data0);
|
||||
#define p33_tx_1byte(addr, data0) addr = data0
|
||||
|
||||
// u8 p33_rx_1byte(u16 addr);
|
||||
#define p33_rx_1byte(addr) addr
|
||||
|
||||
#define P33_CON_SET(sfr, start, len, data) (sfr = (sfr & ~((~(0xffffffff << (len))) << (start))) | \
|
||||
(((data) & (~(0xffffffff << (len)))) << (start)))
|
||||
|
||||
#define P33_CON_GET(sfr) (sfr)
|
||||
|
||||
|
||||
|
||||
#if 1
|
||||
|
||||
#define p33_fast_access(reg, data, en) \
|
||||
{ \
|
||||
if (en) { \
|
||||
p33_or_1byte(reg, (data)); \
|
||||
} else { \
|
||||
p33_and_1byte(reg, ~(data)); \
|
||||
} \
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
#define p33_fast_access(reg, data, en) \
|
||||
{ \
|
||||
if (en) { \
|
||||
reg |= (data); \
|
||||
} else { \
|
||||
reg &= ~(data); \
|
||||
} \
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
// for p33_analog
|
||||
//
|
||||
//
|
||||
//
|
||||
/************************P3_PSW_CON0*****************************/
|
||||
#define DVD2SVD_SHORT_EN(en) p33_fast_access(P3_PSW_CON0, BIT(6), en)
|
||||
|
||||
#define SVD2RVD2_SHORT_EN(en) p33_fast_access(P3_PSW_CON0, BIT(5), en)
|
||||
|
||||
#define SVD2RVD_SHORT_EN(en) p33_fast_access(P3_PSW_CON0, BIT(4), en)
|
||||
#define RVDD2_CAP_EN(en) p33_fast_access(P3_PSW_CON0, BIT(3), en)
|
||||
#define RVD2_EN(en) p33_fast_access(P3_PSW_CON0, BIT(2), en)
|
||||
|
||||
#define RVDD_CAP_EN(en) p33_fast_access(P3_PSW_CON0, BIT(1), en)
|
||||
|
||||
#define RVD_EN(en) p33_fast_access(P3_PSW_CON0, BIT(0), en)
|
||||
|
||||
#define NVD2IO_SHORT_EN(en) p33_fast_access(P3_PSW_CON1, BIT(7), en)
|
||||
|
||||
#define DVDD2_IFULL_EN(en) p33_fast_access(P3_PSW_CON1, BIT(6), en)
|
||||
#define DVDD2_BYPASS_EN(en) p33_fast_access(P3_PSW_CON1, BIT(5), en)
|
||||
#define DVDD2_EN(en) p33_fast_access(P3_PSW_CON1, BIT(4), en)
|
||||
|
||||
#define RVDD2_BYPASS_EN(en) p33_fast_access(P3_PSW_CON1, BIT(3), en)
|
||||
|
||||
#define RVDD_BYPASS_EN(en) p33_fast_access(P3_PSW_CON1, BIT(2), en)
|
||||
#define WVD2SVD_SHORT_EN(en) p33_fast_access(P3_PSW_CON1, BIT(1), en)
|
||||
#define WVDD_EN(en) p33_fast_access(P3_PSW_CON1, BIT(0), en)
|
||||
#define WVDD_PDOWN_ENTER() P33_CON_SET(P3_PSW_CON1, 0, 2, 0x03); P33_CON_SET(P3_PSW_CON0, 4, 3, 0x7)
|
||||
|
||||
#define WVDD_POFF_ENTER() P33_CON_SET(P3_PSW_CON1, 0, 2, 0x03); P33_CON_SET(P3_PSW_CON0, 4, 3, 0x1)
|
||||
|
||||
#define WVDD_PDOWN_POFF_EXIT() P33_CON_SET(P3_PSW_CON0, 4, 3, 0x07); P33_CON_SET(P3_PSW_CON1, 1, 1, 0x00)
|
||||
|
||||
/************************P3_PSW_CON2*****************************/
|
||||
//SS: soft start of VPQS
|
||||
#define VQPS_SS_EN(en) p33_fast_access(P3_PSW_CON2, BIT(1), en)
|
||||
|
||||
#define VQPS_EN(en) p33_fast_access(P3_PSW_CON2, BIT(0), en)
|
||||
|
||||
/************************P3_ANA_CON*****************************/
|
||||
//#define EVDD_IFULL_EN(en) p33_fast_access(P3_ANA_CON, BIT(0), en)
|
||||
|
||||
//DS: decrease undershoot and overshoot
|
||||
//#define DVD_DS_EN(en) p33_fast_access(P3_ANA_CON, BIT(1), en)
|
||||
|
||||
//#define RVD_DS_EN(en) p33_fast_access(P3_ANA_CON, BIT(2), en)
|
||||
|
||||
/************************P3_PMU_ADC0*****************************/
|
||||
enum {
|
||||
VBG_TEST_SEL_WBG04,
|
||||
VBG_TEST_SEL_MBG04,
|
||||
VBG_TEST_SEL_MBG08,
|
||||
VBG_TEST_SEL_LVDBG,
|
||||
};
|
||||
#define VBG_TEST_SEL(sel) P33_CON_SET(P3_PMU_ADC0, 4, 2, sel)
|
||||
|
||||
#define VBG_TEST_EN(en) p33_fast_access(P3_PMU_ADC0, BIT(3), en)
|
||||
|
||||
#define VBG_BUFFER_EN(en) p33_fast_access(P3_PMU_ADC0, BIT(2), en)
|
||||
|
||||
#define PMU_TOADC_OE(en) p33_fast_access(P3_PMU_ADC0, BIT(1), en)
|
||||
|
||||
#define PMU_TOADC_EN(en) p33_fast_access(P3_PMU_ADC0, BIT(0), en)
|
||||
|
||||
/************************P3_PMU_ADC1*****************************/
|
||||
#define ADC_CHANNEL_SEL(ch) P33_CON_SET(P3_PMU_ADC1, 0, 4, ch)
|
||||
|
||||
/************************P3_VBG_CON0*****************************/
|
||||
#define MVBG_SEL(sel) P33_CON_SET(P3_VBG_CON0, 0, 4, sel)
|
||||
|
||||
#define WVBG_SEL(sel) P33_CON_SET(P3_VBG_CON0, 4, 4, sel)
|
||||
|
||||
/************************P3_IOV_CON0*****************************/
|
||||
|
||||
#define VDDIOW_VOL_SEL(lev) P33_CON_SET(P3_IOV_CON0, 4, 4, lev)
|
||||
|
||||
#define GET_VDDIOW_VOL_SEL() (P33_CON_GET(P3_IOV_CON0)>>4 & 0xf)
|
||||
|
||||
//vddiom_lev
|
||||
|
||||
#define VDDIOM_VOL_SEL(lev) P33_CON_SET(P3_IOV_CON0, 0, 4, lev)
|
||||
|
||||
#define GET_VDDIOM_VOL_SEL() (P33_CON_GET(P3_IOV_CON0) & 0xf)
|
||||
|
||||
/************************P3_IOV_CON1*****************************/
|
||||
#define VDDIO_HD_SEL(hd) P33_CON_SET(P3_IOV_CON1, 0, 2, hd)
|
||||
|
||||
/************************P3_DCV_CON0*****************************/
|
||||
#define DCVD_DEOVSHOT_EN(en) p33_fast_access(P3_DCV_CON0, BIT(7), en)
|
||||
|
||||
#define DCVD_CAP_EN(en) p33_fast_access(P3_DCV_CON0, BIT(6), en)
|
||||
|
||||
#define DCVD_HD_SEL(sel) P33_CON_SET(P3_DCV_CON0, 4, 2, sel)
|
||||
|
||||
|
||||
#define DCVDD_DEFAULT_VOL DCVDD_VOL_SEL_120V
|
||||
|
||||
#define GET_DCVDD_VOL_SEL() (P33_CON_GET(P3_DCV_CON0) & 0xf)
|
||||
|
||||
#define DCVDD_VOL_SEL(sel) P33_CON_SET(P3_DCV_CON0, 0, 4, sel)
|
||||
|
||||
|
||||
/*******************************************************************/
|
||||
/*
|
||||
*-------------------P3_DCV_CON0
|
||||
*/
|
||||
enum {
|
||||
DCVDD_VOL_SEL_100V = 0,
|
||||
DCVDD_VOL_SEL_1025V,
|
||||
DCVDD_VOL_SEL_105V,
|
||||
DCVDD_VOL_SEL_1075V,
|
||||
DCVDD_VOL_SEL_110V,
|
||||
DCVDD_VOL_SEL_1125V,
|
||||
DCVDD_VOL_SEL_115V,
|
||||
DCVDD_VOL_SEL_1175V,
|
||||
DCVDD_VOL_SEL_120V,
|
||||
DCVDD_VOL_SEL_1225V,
|
||||
DCVDD_VOL_SEL_125V,
|
||||
DCVDD_VOL_SEL_1275V,
|
||||
DCVDD_VOL_SEL_130V,
|
||||
DCVDD_VOL_SEL_1325V,
|
||||
DCVDD_VOL_SEL_135V,
|
||||
DCVDD_VOL_SEL_1375V,
|
||||
};
|
||||
|
||||
#define DCVD_SEL(sel) P3_DCV_CON0 = (P3_DCV_CON0 & (~0xf)) | sel
|
||||
#define DCVDD_DEFAULT_VOL DCVDD_VOL_SEL_120V
|
||||
|
||||
/************************P3_DCD_CON0*****************************/
|
||||
enum {
|
||||
BTDCDC_OSC_SEL0520KHz = 0,
|
||||
BTDCDC_OSC_SEL0762KHz,
|
||||
BTDCDC_OSC_SEL0997KHz,
|
||||
BTDCDC_OSC_SEL1220KHz,
|
||||
BTDCDC_OSC_SEL1640KHz,
|
||||
BTDCDC_OSC_SEL1840KHz,
|
||||
BTDCDC_OSC_SEL2040KHz,
|
||||
BTDCDC_OSC_SEL2220MHz,
|
||||
};
|
||||
|
||||
#define BTDCDC_OSC_SEL(sel) P33_CON_SET(P3_DCD_CON0, 5, 3, sel)
|
||||
|
||||
#define BTDCDC_DUTY_SEL(sel) P33_CON_SET(P3_DCD_CON0, 3, 2, sel)
|
||||
|
||||
#define BTDCDC_V17_TEST_OE(en) p33_fast_access(P3_DCD_CON0, BIT(2), en);
|
||||
|
||||
#define BTDCDC_RAMP_SHORT(en) p33_fast_access(P3_DCD_CON0, BIT(1), en)
|
||||
|
||||
#define BTDCDC_PFM_MODE(en) p33_fast_access(P3_DCD_CON0, BIT(0), en)
|
||||
|
||||
#define GET_BTDCDC_PFM_MODE() (P33_CON_GET(P3_DCD_CON0) & BIT(0) ? 1 : 0)
|
||||
|
||||
/************************P3_DCD_CON1*****************************/
|
||||
#define BTDCDC_COMP_HD(sel) P33_CON_SET(P3_DCD_CON1, 6, 2, sel)
|
||||
|
||||
#define BTDCDC_ISENSE_HD(sel) P33_CON_SET(P3_DCD_CON1, 4, 2, sel)
|
||||
|
||||
#define BTDCDC_DT_S(sel) P33_CON_SET(P3_DCD_CON1, 2, 2, sel)
|
||||
|
||||
#define BTDCDC_V21_RES_S(sel) P33_CON_SET(P3_DCD_CON1, 0, 2, sel)
|
||||
|
||||
/************************P3_DCD_CON2*****************************/
|
||||
#define BTDCDC_PMOS_S(sel) P33_CON_SET(P3_DCD_CON2, 5, 3, sel)
|
||||
|
||||
#define BTDCDC_NMOS_S(sel) P33_CON_SET(P3_DCD_CON2, 1, 3, sel)
|
||||
|
||||
/************************P3_DCD_CON3*****************************/
|
||||
#define BTDCDC_OSC_TEST_OE(en) p33_fast_access(P3_DCD_CON3, BIT(7), en)
|
||||
|
||||
#define BTDCDC_HD_BIAS_SEL(sel) P33_CON_SET(P3_DCD_CON3, 5, 2, sel)
|
||||
|
||||
#define BTDCDC_CLK_SEL(sel) p33_fast_access(P3_DCD_CON3, BIT(4), sel)
|
||||
|
||||
#define GET_BTDCDC_CLK_SEL() ((P33_CON_GET(P3_DCD_CON3) & BIT(4) ? 1 : 0))
|
||||
|
||||
#define BTDCDC_ZCD_RES(sel) P33_CON_SET(P3_DCD_CON3, 2, 2, sel)
|
||||
|
||||
#define BTDCDC_ZCD_EN(en) p33_fast_access(P3_DCD_CON3, BIT(0), en)
|
||||
|
||||
/************************P3_DCD_CON4*****************************/
|
||||
#define BTDCDC_VHH_SEL(sel) P33_CON_SET(P3_DCD_CON4, 4, 3, sel)
|
||||
|
||||
#define BTDCDC_PFM_HYS_SEL(sel) P33_CON_SET(P3_DCD_CON4, 0, 2, sel)
|
||||
|
||||
/*******************************************************************/
|
||||
/*
|
||||
*-------------------P3_DVD_CON0
|
||||
*/
|
||||
enum {
|
||||
DVDD_VOL_SEL_0725V = 0,
|
||||
DVDD_VOL_SEL_075V,
|
||||
DVDD_VOL_SEL_0775V,
|
||||
DVDD_VOL_SEL_080V,
|
||||
DVDD_VOL_SEL_0825V,
|
||||
DVDD_VOL_SEL_0850V,
|
||||
DVDD_VOL_SEL_0875V,
|
||||
DVDD_VOL_SEL_090V,
|
||||
DVDD_VOL_SEL_0925V,
|
||||
DVDD_VOL_SEL_0950V,
|
||||
DVDD_VOL_SEL_0975V,
|
||||
DVDD_VOL_SEL_100V,
|
||||
DVDD_VOL_SEL_1025V,
|
||||
DVDD_VOL_SEL_105V,
|
||||
DVDD_VOL_SEL_1075V,
|
||||
DVDD_VOL_SEL_110V,
|
||||
};
|
||||
|
||||
/************************P3_DVD_CON0*****************************/
|
||||
|
||||
#define DVDD_DEFAULT_VOL DVDD_VOL_SEL_090V
|
||||
|
||||
#define DVDD_VOL_SEL(sel) P33_CON_SET(P3_DVD_CON0, 0, 4, sel)
|
||||
|
||||
#define GET_DVDD_VOL_SEL() (P33_CON_GET(P3_DVD_CON0) & 0xf)
|
||||
|
||||
#define DVDD_HD_SEL(sel) P33_CON_SET(P3_DVD_CON0, 4, 2, sel)
|
||||
|
||||
#define DVDD_CAP_EN(en) p33_fast_access(P3_DVD_CON0, BIT(6), en)
|
||||
|
||||
/*******************************************************************/
|
||||
/*
|
||||
*-------------------P3_RVD_CON0
|
||||
*/
|
||||
enum {
|
||||
RVDD_VOL_SEL_0725V = 0,
|
||||
RVDD_VOL_SEL_075V,
|
||||
RVDD_VOL_SEL_0775V,
|
||||
RVDD_VOL_SEL_080V,
|
||||
RVDD_VOL_SEL_0825V,
|
||||
RVDD_VOL_SEL_0850V,
|
||||
RVDD_VOL_SEL_0875V,
|
||||
RVDD_VOL_SEL_090V,
|
||||
RVDD_VOL_SEL_0925V,
|
||||
RVDD_VOL_SEL_0950V,
|
||||
RVDD_VOL_SEL_0975V,
|
||||
RVDD_VOL_SEL_100V,
|
||||
RVDD_VOL_SEL_1025V,
|
||||
RVDD_VOL_SEL_105V,
|
||||
RVDD_VOL_SEL_1075V,
|
||||
RVDD_VOL_SEL_110V,
|
||||
};
|
||||
|
||||
|
||||
#define RVDD_VOL_SEL(sel) P33_CON_SET(P3_RVD_CON0, 0, 4, sel)
|
||||
|
||||
#define RVDD_DEFAULT_VOL RVDD_VOL_SEL_090V
|
||||
|
||||
#define GET_RVDD_VOL_SEL() (P33_CON_GET(P3_RVD_CON0) & 0xf)
|
||||
|
||||
#define RVDD_HD_SEL(en) P33_CON_SET(P3_RVD_CON0, 4, 2, en)
|
||||
|
||||
/************************P3_RVD_CON1*****************************/
|
||||
#define RVDD_CMP_EN(en) p33_fast_access(P3_RVD_CON1, BIT(4), en)
|
||||
|
||||
#define PVDD_DCDC_LEV_SEL(sel) P33_CON_SET(P3_RVD_CON1, 0, 4, sel)
|
||||
|
||||
#define GET_PVDD_DCDC_LEV_SEL() (P33_CON_GET(P3_RVD_CON1) & 0xf)
|
||||
|
||||
/************************P3_WVD_CON0*****************************/
|
||||
#define WVDD_LOAD_EN(en) p33_fast_access(P3_WVD_CON0, BIT(4), en)
|
||||
|
||||
#define WVDD_VOL_SEL(sel) P33_CON_SET(P3_WVD_CON0, 0, 4, sel)
|
||||
|
||||
|
||||
/************************P3_PVD_CON0*****************************/
|
||||
#define PVD_DEUDSHT_EN(en) p33_fast_access(P3_PVD_CON0, BIT(3), en)
|
||||
|
||||
#define GET_PVD_DEUDST_EN() ((P33_CON_GET(P3_PVD_CON0) & BIT(3)) ? 1:0)
|
||||
|
||||
#define PVDD_HD_SEL(sel) P33_CON_SET(P3_PVD_CON0, 0, 3, sel)
|
||||
|
||||
#define GET_PVDD_HD_SEL() (P33_CON_GET(P3_PVD_CON0) & 0x7)
|
||||
|
||||
/************************P3_EVD_CON0*****************************/
|
||||
enum {
|
||||
EVD_VOL_SEL_100V = 0,
|
||||
EVD_VOL_SEL_105V,
|
||||
EVD_VOL_SEL_110V,
|
||||
EVD_VOL_SEL_115V,
|
||||
};
|
||||
|
||||
#define EVD_CAP_EN(en) p33_fast_access(P3_EVD_CON0, BIT(4), en)
|
||||
|
||||
#define EVD_HD_SEL(sel) P33_CON_SET(P3_EVD_CON0, 2, 2, sel)
|
||||
|
||||
#define EVD_VOL_SEL(sel) P33_CON_SET(P3_EVD_CON0, 0, 2, sel)
|
||||
|
||||
#define RVD_DEUDSHT_EN(en) p33_fast_access(P3_ANA_MFIX, BIT(2), en)
|
||||
#define DVD_DEUDSHT_EN(en) p33_fast_access(P3_ANA_MFIX, BIT(1), en)
|
||||
#define EVD_ILMT_EN(en) p33_fast_access(P3_ANA_MFIX, BIT(0), en)
|
||||
|
||||
/************************P3_CHG_CON0*****************************/
|
||||
#define LRC_Hz_DEFAULT (200 * 1000L)
|
||||
|
||||
#define LRC_CON0_INIT \
|
||||
/* */ (0 << 7) |\
|
||||
/* */ (0 << 6) |\
|
||||
/*RC32K_RPPS_S1_33v */ (1 << 5) |\
|
||||
/*RC32K_RPPS_S0_33v */ (1 << 4) |\
|
||||
/* */ (0 << 3) |\
|
||||
/* */ (0 << 2) |\
|
||||
/*RC32K_RN_TRIM_33v */ (1 << 1) |\
|
||||
/*RC32K_EN_33v */ (1 << 0)
|
||||
|
||||
#define LRC_CON1_INIT \
|
||||
/* */ (0 << 7) |\
|
||||
/*RC32K_CAP_S2_33v */ (0 << 6) |\
|
||||
/*RC32K_CAP_S1_33v */ (1 << 5) |\
|
||||
/*RC32K_CAP_S0_33v */ (1 << 4) |\
|
||||
/* 2bit */ (0 << 2) |\
|
||||
/*RC32K_RNPS_S1_33v */ (1 << 1) |\
|
||||
/*RC32K_RNPS_S0_33v */ (0 << 0)
|
||||
/************************P3_LRC_CON0*****************************/
|
||||
|
||||
#define LRC32K_RPPS_SEL(sel) P33_CON_SET(P3_LRC_CON0, 4, 2, sel)
|
||||
|
||||
#define LRC32K_RN_TRIM(en) p33_fast_access(P3_LRC_CON0, BIT(1), en)
|
||||
|
||||
#define LRC_EN(en) p33_fast_access(P3_LRC_CON0, BIT(0), en);\
|
||||
p33_fast_access(P3_LRC_CON0, BIT(1), en)
|
||||
|
||||
/************************P3_LRC_CON1*****************************/
|
||||
#define LRC32K_CAP_SEL(sel) P33_CON_SET(P3_LRC_CON1, 4, 3, sel)
|
||||
|
||||
#define LRC32K_PNPS_SEL(sel) P33_CON_SET(P3_LRC_CON1, 0, 2, sel)
|
||||
|
||||
#define CLOSE_LRC() p33_tx_1byte(P3_LRC_CON0, 0);\
|
||||
p33_tx_1byte(P3_LRC_CON1, 0)
|
||||
|
||||
/*******************************************************************/
|
||||
/************************P3_VLVD_CON0*****************************/
|
||||
#define VLVD_PND() ((P33_CON_GET(P3_VLVD_CON0) & BIT(7)) ? 1 : 0)
|
||||
|
||||
#define VLVD_PND_CLR() p33_fast_access(P3_VLVD_CON0, BIT(6), 1)
|
||||
|
||||
#define P33_VLVD_PS(en) p33_fast_access(P3_VLVD_CON0, BIT(2), en)
|
||||
|
||||
#define P33_VLVD_OE(en) p33_fast_access(P3_VLVD_CON0, BIT(1), en)
|
||||
|
||||
#define P33_VLVD_EN(en) p33_fast_access(P3_VLVD_CON0, BIT(0), en)
|
||||
|
||||
#define GET_P33_VLVD_EN() ((P33_CON_GET(P3_VLVD_CON0) & BIT(0)) ? 1:0)
|
||||
|
||||
/************************P3_VLVD_FLT*****************************/
|
||||
#define VLVD_FLT(sel) P33_CON_SET(P3_VLVD_FLT, 0, 2, sel);
|
||||
|
||||
/************************P3_RST_CON0*****************************/
|
||||
#define PVDDOK_OE(en) p33_fast_access(P3_RST_CON0, BIT(7), en)
|
||||
|
||||
#define DVDDOK2_OE(en) p33_fast_access(P3_RST_CON0, BIT(6), en)
|
||||
|
||||
#define DVDDOK_OE(en) p33_fast_access(P3_RST_CON0, BIT(5), en)
|
||||
|
||||
#define PPOR_MASK(en) p33_fast_access(P3_RST_CON0, BIT(4), en)
|
||||
|
||||
#define DPOR2_MASK(en) p33_fast_access(P3_RST_CON0, BIT(3), en)
|
||||
|
||||
#define DPOR_MASK(en) p33_fast_access(P3_RST_CON0, BIT(2), en)
|
||||
|
||||
#define P11_TO_P33_RST_MASK(en) p33_fast_access(P3_RST_CON0, BIT(1), en)
|
||||
|
||||
#define FAST_PU_SYS(en) p33_fast_access(P3_RST_CON0, BIT(0), en)
|
||||
|
||||
/************************P3_RST_CON1*****************************/
|
||||
#define IS_VCM_DET_EN() ((P33_CON_GET(P3_RST_CON1) & BIT(0)) ? 1: 0 )
|
||||
#define DVD2_DRST_MASK(en) p33_fast_access(P3_RST_CON1, BIT(5), en)
|
||||
#define DVD_DRST_MASK(en) p33_fast_access(P3_RST_CON1, BIT(4), en)
|
||||
#define VLVD_WKUP_EN(en) p33_fast_access(P3_RST_CON1, BIT(3), en)
|
||||
#define VLVD_RST_EN(en) p33_fast_access(P3_RST_CON1, BIT(2), en)
|
||||
#define VLVD_EXPT_EN(en) p33_fast_access(P3_RST_CON1, BIT(1), en)
|
||||
|
||||
#define VCM_DET_EN(en) p33_fast_access(P3_RST_CON1, BIT(0), en)
|
||||
|
||||
/************************P3_CLK_CON0*****************************/
|
||||
#define RC_250K_EN(a) p33_fast_access(P3_CLK_CON0, BIT(0), a)
|
||||
|
||||
/************************P3_VLD_KEEP*****************************/
|
||||
#define RTC_WKUP_KEEP(a) p33_fast_access(P3_VLD_KEEP, BIT(1), a)
|
||||
|
||||
#define P33_WKUP_P11_EN(a) p33_fast_access(P3_VLD_KEEP, BIT(2), a)
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
// for pmu flow
|
||||
//
|
||||
//
|
||||
//
|
||||
/************************P3_P11_CPU*****************************/
|
||||
#define P11_CPU_BRANCH_POWEROFF(en) p33_fast_access(P3_P11_CPU, BIT(1), en)
|
||||
|
||||
#define P11_CPU_RELEASE(en) p33_fast_access(P3_P11_CPU, BIT(0), en)
|
||||
|
||||
/************************P3_LP_CTL*****************************/
|
||||
//控制p11的低功耗
|
||||
#define LP_FLOW_EN(en) p33_fast_access(P3_LP_CTL, BIT(0), en)
|
||||
|
||||
#define LP_FLOW_CPND() p33_fast_access(P3_LP_CTL, BIT(6), 1)
|
||||
|
||||
#define POWER_ON_END() ((P33_CON_GET(P3_LP_CTL) & BIT(5)) ? 1: 0 )
|
||||
|
||||
|
||||
#define MBG_EN_EN(a) \
|
||||
if (a) { \
|
||||
p33_or_1byte(P3_ANA_FLOW0, BIT(7)); \
|
||||
} else { \
|
||||
p33_and_1byte(P3_ANA_FLOW0, ~BIT(7)); \
|
||||
}
|
||||
|
||||
/************************P3_ANA_FLOW0*****************************/
|
||||
#define DVD_EN(en) p33_fast_access(P3_ANA_FLOW0, BIT(0), en)
|
||||
|
||||
|
||||
#define DCVD_TO_DIG_EN(en) p33_fast_access(P3_ANA_FLOW0, BIT(0)|BIT(1), en)
|
||||
|
||||
#define DCVD_LDO_EN(en) p33_fast_access(P3_ANA_FLOW0, BIT(2), en)
|
||||
|
||||
#define PAVD_LDO_EN(en) p33_fast_access(P3_ANA_FLOW0, BIT(3), en)
|
||||
|
||||
#define GET_DCVD_STA() ((P33_CON_GET(P3_ANA_FLOW0) & (BIT(2))) ? 1:0)
|
||||
|
||||
#define GET_PAVD_LDO_EN() ((P33_CON_GET(P3_ANA_FLOW0) & BIT(3)) ? 1:0)
|
||||
|
||||
#define PVDD_EN(en) p33_fast_access(P3_ANA_FLOW0, BIT(4), en)
|
||||
|
||||
#define MVIO_VBAT_EN(en) p33_fast_access(P3_ANA_FLOW0, BIT(5), en)
|
||||
|
||||
#define MVIO_VPWR_EN(en) p33_fast_access(P3_ANA_FLOW0, BIT(6), en)
|
||||
|
||||
#define PW_GATE_EN(en) p33_fast_access(P3_ANA_FLOW0, BIT(5)|BIT(6), en)
|
||||
|
||||
#define MBG_EN(en) p33_fast_access(P3_ANA_FLOW0, BIT(7), en)
|
||||
|
||||
#define MVIO_PVDD_MVBG_ONLY() p33_tx_1byte(P3_ANA_FLOW0, BIT(4) | BIT(5) | BIT(6) | BIT(7))
|
||||
|
||||
#define PVDD_MVBG_ONLY() p33_tx_1byte(P3_ANA_FLOW0, BIT(4) | BIT(7))
|
||||
|
||||
#define PVDD_ONLY() p33_tx_1byte(P3_ANA_FLOW0, BIT(4))
|
||||
|
||||
/************************P3_ANA_FLOW1*****************************/
|
||||
#define MIOV_VLMT_EN(en) p33_fast_access(P3_ANA_FLOW1, BIT(4), en)
|
||||
|
||||
#define MIOV_IFULL_EN(en) p33_fast_access(P3_ANA_FLOW1, BIT(3), en)
|
||||
|
||||
#define PAVD_IFULL_EN(en) p33_fast_access(P3_ANA_FLOW1, BIT(2), en)
|
||||
|
||||
#define DCVD_IFULL_EN(en) p33_fast_access(P3_ANA_FLOW1, BIT(1), en)
|
||||
|
||||
|
||||
#define DVD_IFULL_EN(en) p33_fast_access(P3_ANA_FLOW1, BIT(0), en)
|
||||
|
||||
/************************P3_ANA_FLOW2*****************************/
|
||||
#define NVD2PVD_WSHORT_EN(en) p33_fast_access(P3_ANA_FLOW2, BIT(1), en)
|
||||
|
||||
#define NVD2PVD_SHORT_EN(en) p33_fast_access(P3_ANA_FLOW2, BIT(0), en)
|
||||
|
||||
|
||||
/************************P3_NVRAM_PWR*****************************/
|
||||
#define NVRAM_PWR_MODE(sel) P33_CON_SET(P3_NVRAM_PWR, 4, 2, sel)
|
||||
|
||||
|
||||
/************************P3_PVDD0_AUTO*****************************/
|
||||
|
||||
#define PVDD_AUTO_PRD(sel) P33_CON_SET(P3_PVDD0_AUTO, 5, 3, sel);
|
||||
|
||||
#define PVDD_LEVEL_AUTO(en) p33_fast_access(P3_PVDD0_AUTO, BIT(4), en);
|
||||
|
||||
#define PVDD_LEVEL_LOW(sel) P33_CON_SET(P3_PVDD0_AUTO, 0, 4, sel);
|
||||
|
||||
|
||||
/************************P3_PVDD1_AUTO*****************************/
|
||||
#define PVDD_LEVEL_HIGH_NOW(sel) p33_tx_1byte(P3_PVDD1_AUTO, (sel<<4)|sel);
|
||||
|
||||
#define PVDD_LEVEL_HIGH(sel) P33_CON_SET(P3_PVDD1_AUTO, 4, 4, sel)
|
||||
|
||||
#define PVDD_LEVEL_NOW(sel) P33_CON_SET(P3_PVDD1_AUTO, 0, 4, sel)
|
||||
|
||||
#define GET_PVDD_LEVEL_NOW() (P33_CON_GET(P3_PVDD1_AUTO) & 0x0f)
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
// for ANA_control
|
||||
//
|
||||
//
|
||||
/////
|
||||
/*******************************************************************/
|
||||
/************************P3_LS_XX*****************************/
|
||||
enum PWR_LAT {
|
||||
DVDDLS_LAT,
|
||||
PVDDLS_LAT,
|
||||
};
|
||||
|
||||
#define DVDDLS_OR_BIT(a) \
|
||||
p33_or_1byte(P3_LS_IO_USR , BIT(a)); \
|
||||
p33_or_1byte(P3_LS_IO_ROM , BIT(a));
|
||||
|
||||
#define SHALS_OR_BIT(a) \
|
||||
p33_or_1byte(P3_LS_IO_SHA , BIT(a)); \
|
||||
p33_or_1byte(P3_LS_IO_PINR , BIT(a));
|
||||
|
||||
#define PVDDLS_OR_BIT(a) \
|
||||
p33_or_1byte(P3_LS_CTMU , BIT(a)); \
|
||||
p33_or_1byte(P3_LS_P11 , BIT(a));
|
||||
|
||||
#define DVDDLS_AND_NBIT(a) \
|
||||
p33_and_1byte(P3_LS_IO_USR , (u8)~BIT(a)); \
|
||||
p33_and_1byte(P3_LS_IO_ROM , (u8)~BIT(a));
|
||||
|
||||
#define SHALS_AND_NBIT(a) \
|
||||
p33_and_1byte(P3_LS_IO_SHA , (u8)~BIT(a)); \
|
||||
p33_and_1byte(P3_LS_IO_PINR , (u8)~BIT(a));
|
||||
|
||||
#define PVDDLS_AND_NBIT(a) \
|
||||
p33_and_1byte(P3_LS_CTMU , (u8)~BIT(a)); \
|
||||
p33_and_1byte(P3_LS_P11 , (u8)~BIT(a));
|
||||
|
||||
#define DVDDLS_TX_BYTE(a) \
|
||||
p33_tx_1byte(P3_LS_IO_USR , a); \
|
||||
p33_tx_1byte(P3_LS_IO_ROM , a);
|
||||
|
||||
#define SHALS_TX_BYTE(a) \
|
||||
p33_tx_1byte(P3_LS_IO_SHA , a); \
|
||||
p33_tx_1byte(P3_LS_IO_PINR , a);
|
||||
|
||||
#define PVDDLS_TX_BYTE(a) \
|
||||
p33_tx_1byte(P3_LS_CTMU , a); \
|
||||
p33_tx_1byte(P3_LS_P11 , a);
|
||||
|
||||
#define DVDDLS_ANA_NBIT(a) \
|
||||
p33_and_1byte(P3_LS_IO_USR , ~BIT(a)); \
|
||||
p33_and_1byte(P3_LS_IO_ROM , ~BIT(a)); \
|
||||
p33_and_1byte(P3_LS_IO_SHA , ~BIT(a)); \
|
||||
p33_and_1byte(P3_LS_CTMU , ~BIT(a)); \
|
||||
|
||||
#define SHALS_ANA_NBIT(a) \
|
||||
p33_and_1byte(P3_LS_IO_SHA , (u8)~BIT(a)); \
|
||||
p33_and_1byte(P3_LS_CTMU , (u8)~BIT(a)); \
|
||||
|
||||
#define PVDDLS_ANA_NBIT(a) \
|
||||
p33_and_1byte(P3_LS_P11 , ~BIT(a));
|
||||
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
// for reset_source
|
||||
//
|
||||
//
|
||||
//
|
||||
/************************P3_PR_PWR*****************************/
|
||||
#define P3_SOFT_RESET() P33_CON_SET(P3_PR_PWR, 4, 1, 1)
|
||||
|
||||
/************************P3_IVS_CLR*****************************/
|
||||
#define PWVLD(a) \
|
||||
if (a) { \
|
||||
p33_tx_1byte(P3_IVS_SET, BIT(7)); \
|
||||
} else { \
|
||||
p33_tx_1byte(P3_IVS_CLR, BIT(7)); \
|
||||
}
|
||||
|
||||
#define P33_SF_KICK_START() P33_CON_SET(P3_IVS_CLR, 0, 8, 0b00101010)
|
||||
|
||||
#define PWR_BY_SOFTWARE(a) \
|
||||
if (a) { \
|
||||
p33_or_1byte(P3_RST_CON1, BIT(6)); \
|
||||
p33_tx_1byte(P3_ANA_KEEP0, 0xff); \
|
||||
p33_tx_1byte(P3_ANA_KEEP1, 0xff); \
|
||||
PWVLD(0); \
|
||||
} else { \
|
||||
PWVLD(1); \
|
||||
p33_and_1byte(P3_RST_CON1, ~BIT(6)); \
|
||||
}
|
||||
|
||||
|
||||
/************************P3_RST_SRC*****************************/
|
||||
#define GET_P33_SYS_RST_SRC() P33_CON_GET(P3_RST_SRC)
|
||||
|
||||
/************************P3_RST_FLAG*****************************/
|
||||
#define GET_P33_SYS_POWER_FLAG() ((P33_CON_GET(P3_RST_FLAG) & BIT(3)) ? 1 : 0)
|
||||
|
||||
#define GET_P33_SYS_RST_LEVEL2() ((P33_CON_GET(P3_RST_FLAG) & BIT(3)) ? 1 : 0)
|
||||
#define GET_P33_SYS_RST_LEVEL1() ((P33_CON_GET(P3_RST_FLAG) & BIT(5)) ? 1 : 0)
|
||||
#define GET_P33_SYS_RST_LEVEL0() ((P33_CON_GET(P3_RST_FLAG) & BIT(7)) ? 1 : 0)
|
||||
|
||||
#define P33_LV2_RST_FLAG_CLR() (p33_fast_access(P3_RST_FLAG, BIT(2), 1))
|
||||
#define P33_LV1_RST_FLAG_CLR() (p33_fast_access(P3_RST_FLAG, BIT(4), 1))
|
||||
#define P33_LV0_RST_FLAG_CLR() (p33_fast_access(P3_RST_FLAG, BIT(6), 1))
|
||||
|
||||
|
||||
//-----special operation----------
|
||||
#define P33_WKUP_ENABLE() \
|
||||
p33_or_1byte(P3_VLD_KEEP , BIT(2))
|
||||
|
||||
#define P33_WKUP_DISABLE() \
|
||||
p33_and_1byte(P3_VLD_KEEP , ~BIT(2))
|
||||
|
||||
#define P33_IE_ENABLE() \
|
||||
bit_set_ie(IRQ_P33_IDX)
|
||||
|
||||
#define P33_IE_DISABLE() \
|
||||
bit_clr_ie(IRQ_P33_IDX)
|
||||
|
||||
#define IS_CHARGE_EN_NOW() (P3_CHG_CON0 & BIT(0))
|
||||
|
||||
/*
|
||||
*-------------------P3_ANA_FLOW0
|
||||
*/
|
||||
|
||||
|
||||
#define DCVDD_EN(a) \
|
||||
if (a) { \
|
||||
p33_or_1byte(P3_ANA_FLOW0, BIT(2)); \
|
||||
} else { \
|
||||
p33_and_1byte(P3_ANA_FLOW0, ~BIT(2)); \
|
||||
}
|
||||
|
||||
#define DCDC13_EN(a) \
|
||||
if (a) { \
|
||||
p33_or_1byte(P3_ANA_FLOW0, BIT(3)); \
|
||||
} else { \
|
||||
p33_and_1byte(P3_ANA_FLOW0, ~BIT(3)); \
|
||||
}
|
||||
|
||||
#define IS_DCDC13_EN() ((P3_ANA_FLOW0 & BIT(3)) ? 1: 0 )
|
||||
|
||||
|
||||
|
||||
|
||||
/*
|
||||
*-------------------P3_ANA_FLOW1
|
||||
*/
|
||||
|
||||
#define IOVD_IFULL_EN(a) \
|
||||
if (a) { \
|
||||
p33_or_1byte(P3_ANA_FLOW1, (BIT(0) | BIT(1))); \
|
||||
} else { \
|
||||
p33_and_1byte(P3_ANA_FLOW1, ~(BIT(0) | BIT(1))); \
|
||||
}
|
||||
|
||||
#define IOVD_VLMT_EN(a) \
|
||||
if (a) { \
|
||||
p33_or_1byte(P3_ANA_FLOW1, (BIT(2) | BIT(3))); \
|
||||
} else { \
|
||||
p33_and_1byte(P3_ANA_FLOW1, ~(BIT(2) | BIT(3))); \
|
||||
}
|
||||
|
||||
|
||||
#define DVD_POR_EN(a) \
|
||||
if (a) { \
|
||||
p33_or_1byte(P3_ANA_FLOW1, BIT(6)); \
|
||||
} else { \
|
||||
p33_and_1byte(P3_ANA_FLOW1, ~BIT(6)); \
|
||||
}
|
||||
|
||||
#define PVD_POR_EN(a) \
|
||||
if (a) { \
|
||||
p33_or_1byte(P3_ANA_FLOW1, BIT(7)); \
|
||||
} else { \
|
||||
p33_and_1byte(P3_ANA_FLOW1, ~BIT(7)); \
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/*******************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************/
|
||||
|
||||
|
||||
/*
|
||||
*-------------------P3_VLVD_CON1
|
||||
*/
|
||||
#define VLVD_SEL(a) P3_VLVD_CON1 = (P3_VLVD_CON1 & (~0xf)) | a
|
||||
//macro for VLVD_SEL
|
||||
enum {
|
||||
VLVD_sel_16V = 0,
|
||||
VLVD_sel_17V,
|
||||
VLVD_sel_18V,
|
||||
VLVD_sel_19V,
|
||||
VLVD_sel_20V,
|
||||
VLVD_sel_21V,
|
||||
VLVD_sel_22V,
|
||||
VLVD_sel_23V,
|
||||
VLVD_sel_24V,
|
||||
VLVD_sel_25V,
|
||||
VLVD_sel_26V,
|
||||
VLVD_sel_27V,
|
||||
VLVD_sel_28V,
|
||||
VLVD_sel_29V,
|
||||
VLVD_sel_30V,
|
||||
VLVD_sel_31V,
|
||||
};
|
||||
|
||||
/*******************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************/
|
||||
/*
|
||||
*-------------------P3_IOV_CON0
|
||||
*/
|
||||
//vddiom_lev
|
||||
enum {
|
||||
VDDIOM_VOL_21V = 0,
|
||||
VDDIOM_VOL_22V,
|
||||
VDDIOM_VOL_23V,
|
||||
VDDIOM_VOL_24V,
|
||||
VDDIOM_VOL_25V,
|
||||
VDDIOM_VOL_26V,
|
||||
VDDIOM_VOL_27V,
|
||||
VDDIOM_VOL_28V,
|
||||
VDDIOM_VOL_29V,
|
||||
VDDIOM_VOL_30V,
|
||||
VDDIOM_VOL_31V,
|
||||
VDDIOM_VOL_32V,
|
||||
VDDIOM_VOL_33V,
|
||||
VDDIOM_VOL_34V,
|
||||
VDDIOM_VOL_35V,
|
||||
VDDIOM_VOL_36V,
|
||||
};
|
||||
|
||||
#define GET_MVIO_SEL() (P3_IOV_CON0 & 0xf)
|
||||
|
||||
#define MVIO_SEL(a) P3_IOV_CON0 = (P3_IOV_CON0 & (~0xf)) | a
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* *-------------------P3_RST_FLAG
|
||||
* */
|
||||
#define P33_SYS_POWERUP_CLEAR() p33_or_1byte(P3_RST_FLAG, BIT(2)|BIT(4)|BIT(6))
|
||||
|
||||
|
||||
|
||||
|
||||
//need 1mS to recorver
|
||||
//P3_ANA_KEEP0 = 0; \
|
||||
//P3_ANA_KEEP1 = 0;
|
||||
|
||||
//while(POWER_ON_END());
|
||||
//P3_ANA_KEEP0 = 0; \
|
||||
//P3_ANA_KEEP1 = 0;
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,340 @@
|
||||
#ifndef __P33_SFR_H__
|
||||
#define __P33_SFR_H__
|
||||
|
||||
#include "typedef.h"
|
||||
|
||||
#ifdef PMU_SYSTEM
|
||||
#define P33_ACCESS(x) (*(volatile u32 *)(0xc000 + x*4))
|
||||
#else
|
||||
#define P33_ACCESS(x) (*(volatile u32 *)(0xf20000 + 0xc000 + x*4))
|
||||
#endif
|
||||
|
||||
#ifdef PMU_SYSTEM
|
||||
#define RTC_ACCESS(x) (*(volatile u32 *)(0xd000 + x*4))
|
||||
#else
|
||||
#define RTC_ACCESS(x) (*(volatile u32 *)(0xf20000 + 0xd000 + x*4))
|
||||
#endif
|
||||
|
||||
//===========
|
||||
//===============================================================================//
|
||||
//
|
||||
//
|
||||
//
|
||||
//===============================================================================//
|
||||
//............. 0x0000 - 0x000f............
|
||||
//#define P3_VLMT_CON P33_ACCESS(0x01)
|
||||
//#define P3_POR_CON P33_ACCESS(0x02)
|
||||
#define P3_VLVD_CON0 P33_ACCESS(0x03)
|
||||
#define P3_VLVD_CON1 P33_ACCESS(0x04)
|
||||
#define P3_VLVD_FLT P33_ACCESS(0x05)
|
||||
#define P3_WDT_CON P33_ACCESS(0x06)
|
||||
#define P3_OCP_CON0 P33_ACCESS(0x07)
|
||||
|
||||
#define P3_ANA_FLOW0 P33_ACCESS(0x08)
|
||||
#define P3_ANA_FLOW1 P33_ACCESS(0x09)
|
||||
#define P3_ANA_FLOW2 P33_ACCESS(0x0a)
|
||||
|
||||
#define P3_ANA_KEEP0 P33_ACCESS(0x0c)
|
||||
#define P3_ANA_KEEP1 P33_ACCESS(0x0d)
|
||||
#define P3_ANA_KEEP2 P33_ACCESS(0x0e)
|
||||
|
||||
//............. 0X0010 - 0X001F.........for analog others
|
||||
#define P3_OSL_CON P33_ACCESS(0x10)
|
||||
#define P3_RST_FLAG P33_ACCESS(0x11)
|
||||
#define P3_VBAT_TYPE P33_ACCESS(0x12)
|
||||
#define P3_LRC_CON0 P33_ACCESS(0x13)
|
||||
#define P3_LRC_CON1 P33_ACCESS(0x14)
|
||||
#define P3_RST_CON0 P33_ACCESS(0x15)
|
||||
#define P3_RST_CON1 P33_ACCESS(0x16)
|
||||
#define P3_RST_CON2 P33_ACCESS(0x17)
|
||||
#define P3_VLD_KEEP P33_ACCESS(0x18)
|
||||
#define P3_CLK_CON0 P33_ACCESS(0x19)
|
||||
#define P3_ANA_READ P33_ACCESS(0x1a)
|
||||
#define P3_CHG_CON0 P33_ACCESS(0x1b)
|
||||
#define P3_CHG_CON1 P33_ACCESS(0x1c)
|
||||
#define P3_CHG_CON2 P33_ACCESS(0x1d)
|
||||
#define P3_CHG_CON3 P33_ACCESS(0x1e)
|
||||
#define P3_CHG_CON4 P33_ACCESS(0x1f)
|
||||
|
||||
//............. 0X0020 - 0X002F............ for buck circuit
|
||||
//#define P3_BUCK1_CON0 P33_ACCESS(0x20)
|
||||
//#define P3_BUCK1_CON1 P33_ACCESS(0x21)
|
||||
//#define P3_BUCK1_CON2 P33_ACCESS(0x22)
|
||||
//#define P3_BUCK1_CON3 P33_ACCESS(0x23)
|
||||
//#define P3_BUCK1_CON4 P33_ACCESS(0x24)
|
||||
//#define P3_BUCK1_CON5 P33_ACCESS(0x25)
|
||||
//#define P3_BUCK1_CON6 P33_ACCESS(0x26)
|
||||
//#define P3_BUCK1_CON7 P33_ACCESS(0x27)
|
||||
#define P3_BUCK2_CON0 P33_ACCESS(0x20)
|
||||
#define P3_BUCK2_CON1 P33_ACCESS(0x21)
|
||||
#define P3_BUCK2_CON2 P33_ACCESS(0x22)
|
||||
#define P3_BUCK2_CON3 P33_ACCESS(0x23)
|
||||
#define P3_BUCK2_CON4 P33_ACCESS(0x24)
|
||||
#define P3_BUCK2_CON5 P33_ACCESS(0x25)
|
||||
#define P3_BUCK2_CON6 P33_ACCESS(0x26)
|
||||
#define P3_BUCK2_CON7 P33_ACCESS(0x27)
|
||||
//#define P3_BUCK3_CON0 P33_ACCESS(0x28)
|
||||
//#define P3_BUCK3_CON1 P33_ACCESS(0x29)
|
||||
//#define P3_BUCK3_CON2 P33_ACCESS(0x2a)
|
||||
//#define P3_BUCK3_CON3 P33_ACCESS(0x2b)
|
||||
//#define P3_BUCK3_CON4 P33_ACCESS(0x2c)
|
||||
//#define P3_BUCK3_CON5 P33_ACCESS(0x2d)
|
||||
//#define P3_BUCK3_CON6 P33_ACCESS(0x2e)
|
||||
//#define P3_BUCK3_CON7 P33_ACCESS(0x2f)
|
||||
|
||||
//............. 0X0030 - 0X003F............ for PMU manager
|
||||
#define P3_SFLAG0 P33_ACCESS(0x30)
|
||||
#define P3_SFLAG1 P33_ACCESS(0x31)
|
||||
#define P3_SFLAG2 P33_ACCESS(0x32)
|
||||
#define P3_SFLAG3 P33_ACCESS(0x33)
|
||||
#define P3_SFLAG4 P33_ACCESS(0x34)
|
||||
#define P3_SFLAG5 P33_ACCESS(0x35)
|
||||
#define P3_SFLAG6 P33_ACCESS(0x36)
|
||||
#define P3_SFLAG7 P33_ACCESS(0x37)
|
||||
#define P3_SFLAG8 P33_ACCESS(0x38)
|
||||
#define P3_SFLAG9 P33_ACCESS(0x39)
|
||||
#define P3_SFLAGA P33_ACCESS(0x3a)
|
||||
#define P3_SFLAGB P33_ACCESS(0x3b)
|
||||
|
||||
//............. 0X0040 - 0X004F............ for
|
||||
#define P3_IVS_RD P33_ACCESS(0x40)
|
||||
#define P3_IVS_SET P33_ACCESS(0x41)
|
||||
#define P3_IVS_CLR P33_ACCESS(0x42)
|
||||
#define P3_PVDD0_AUTO P33_ACCESS(0x43)
|
||||
#define P3_PVDD1_AUTO P33_ACCESS(0x44)
|
||||
#define P3_WKUP_DLY P33_ACCESS(0x45)
|
||||
|
||||
#define P3_PCNT_FLT P33_ACCESS(0x48)
|
||||
#define P3_PCNT_CON P33_ACCESS(0x49)
|
||||
#define P3_PCNT_SET0 P33_ACCESS(0x4a)
|
||||
#define P3_PCNT_SET1 P33_ACCESS(0x4b)
|
||||
#define P3_PCNT_DAT0 P33_ACCESS(0x4c)
|
||||
#define P3_PCNT_DAT1 P33_ACCESS(0x4d)
|
||||
|
||||
#define P3_P11_CPU P33_ACCESS(0x4f)
|
||||
|
||||
//............. 0X0050 - 0X005F............ for port wake up
|
||||
#define P3_WKUP_FLT_EN0 P33_ACCESS(0x50)
|
||||
#define P3_WKUP_P_IE0 P33_ACCESS(0x51)
|
||||
#define P3_WKUP_N_IE0 P33_ACCESS(0x52)
|
||||
#define P3_WKUP_LEVEL0 P33_ACCESS(0x53)
|
||||
#define P3_WKUP_P_CPND0 P33_ACCESS(0x54)
|
||||
#define P3_WKUP_N_CPND0 P33_ACCESS(0x55)
|
||||
#define P3_WKUP_P_PND0 P33_ACCESS(0x56)
|
||||
#define P3_WKUP_N_PND0 P33_ACCESS(0x57)
|
||||
#define P3_WKUP_FLT_EN1 P33_ACCESS(0x58)
|
||||
#define P3_WKUP_P_IE1 P33_ACCESS(0x59)
|
||||
#define P3_WKUP_N_IE1 P33_ACCESS(0x5a)
|
||||
#define P3_WKUP_LEVEL1 P33_ACCESS(0x5b)
|
||||
#define P3_WKUP_P_CPND1 P33_ACCESS(0x5c)
|
||||
#define P3_WKUP_N_CPND1 P33_ACCESS(0x5d)
|
||||
#define P3_WKUP_P_PND1 P33_ACCESS(0x5e)
|
||||
#define P3_WKUP_N_PND1 P33_ACCESS(0x5f)
|
||||
|
||||
//............. 0X0060 - 0X006F............ for analog wake up
|
||||
#define P3_AWKUP_FLT_EN P33_ACCESS(0x60)
|
||||
#define P3_AWKUP_P_IE P33_ACCESS(0x61)
|
||||
#define P3_AWKUP_N_IE P33_ACCESS(0x62)
|
||||
#define P3_AWKUP_LEVEL P33_ACCESS(0x63)
|
||||
#define P3_AWKUP_P_PND P33_ACCESS(0x64)
|
||||
#define P3_AWKUP_N_PND P33_ACCESS(0x65)
|
||||
#define P3_AWKUP_P_CPND P33_ACCESS(0x66)
|
||||
#define P3_AWKUP_N_CPND P33_ACCESS(0x67)
|
||||
#define P3_WKUP_CLK_SEL P33_ACCESS(0x68)
|
||||
#define P3_AWKUP_CLK_SEL P33_ACCESS(0x69)
|
||||
#define P3_SYS_PWR0 P33_ACCESS(0x6a)
|
||||
#define P3_SYS_PWR1 P33_ACCESS(0x6b)
|
||||
#define P3_SYS_PWR2 P33_ACCESS(0x6c)
|
||||
#define P3_SYS_PWR3 P33_ACCESS(0x6d)
|
||||
#define P3_SYS_PWR4 P33_ACCESS(0x6e)
|
||||
#define P3_SYS_PWR5 P33_ACCESS(0x6f)
|
||||
|
||||
//............. 0X0070 - 0X007F............ for
|
||||
#define P3_PGDR_CON0 P33_ACCESS(0x70)
|
||||
#define P3_PGDR_CON1 P33_ACCESS(0x71)
|
||||
#define P3_PGSD_CON P33_ACCESS(0x72)
|
||||
|
||||
#define P3_LP_CTL P33_ACCESS(0x74)
|
||||
#define P3_LP_CFG P33_ACCESS(0x75)
|
||||
#define P3_NVRAM_PWR P33_ACCESS(0x76)
|
||||
#define P3_WVD_CON0 P33_ACCESS(0x77)
|
||||
#define P3_PVD_CON0 P33_ACCESS(0x78)
|
||||
#define P3_EVD_CON0 P33_ACCESS(0x79)
|
||||
#define P3_PMU_CON0 P33_ACCESS(0x7a)
|
||||
|
||||
#define P3_PMU_CON4 P33_ACCESS(0x7e)
|
||||
#define P3_PMU_CON5 P33_ACCESS(0x7f)
|
||||
|
||||
//............. 0X0080 - 0X008F............ for
|
||||
#define P3_PINR_CON P33_ACCESS(0x80)
|
||||
#define P3_PINR_CON1 P33_ACCESS(0x81)
|
||||
#define P3_PINR_SAFE P33_ACCESS(0x82)
|
||||
#define P3_PINR_SAFE1 P33_ACCESS(0x83)
|
||||
#define P3_PINR_PND1 P33_ACCESS(0x84)
|
||||
|
||||
#define P3_RST_SRC0 P33_ACCESS(0x8e)
|
||||
#define P3_RST_SRC1 P33_ACCESS(0x8f)
|
||||
|
||||
//............. 0X0090 - 0X009F............ for
|
||||
#define P3_PSW_CON0 P33_ACCESS(0x90)
|
||||
#define P3_PSW_CON1 P33_ACCESS(0x91)
|
||||
#define P3_PSW_CON2 P33_ACCESS(0x92)
|
||||
#define P3_PMU_ADC0 P33_ACCESS(0x93)
|
||||
#define P3_PMU_ADC1 P33_ACCESS(0x94)
|
||||
#define P3_VBG_CON0 P33_ACCESS(0x95)
|
||||
#define P3_VBG_CON1 P33_ACCESS(0x96)
|
||||
#define P3_IOV_CON0 P33_ACCESS(0x97)
|
||||
#define P3_IOV_CON1 P33_ACCESS(0x98)
|
||||
#define P3_PAVD_CON0 P33_ACCESS(0x99)
|
||||
#define P3_DCV_CON0 P33_ACCESS(0x9a)
|
||||
#define P3_DVD_CON0 P33_ACCESS(0x9b)
|
||||
#define P3_DVD2_CON0 P33_ACCESS(0x9c)
|
||||
#define P3_RVD_CON0 P33_ACCESS(0x9d)
|
||||
#define P3_RVD_CON1 P33_ACCESS(0x9e)
|
||||
#define P3_RVD2_CON0 P33_ACCESS(0x9f)
|
||||
|
||||
//............. 0X00A0 - 0X00AF............
|
||||
#define P3_PR_PWR P33_ACCESS(0xa0)
|
||||
#define P3_VPWR_CON0 P33_ACCESS(0xa1)
|
||||
#define P3_VPWR_CON1 P33_ACCESS(0xa2)
|
||||
#define P3_RTC_ADC0 P33_ACCESS(0xa3)
|
||||
#define P3_LS_P11 P33_ACCESS(0xa4)
|
||||
#define P3_LS_EN P33_ACCESS(0xa5)
|
||||
|
||||
#define P3_EXT_EFUSE_CON P33_ACCESS(0xa6)
|
||||
|
||||
#define P3_WKUP_SRC P33_ACCESS(0xa8)
|
||||
#define P3_ANA_MFIX P33_ACCESS(0xa9)
|
||||
#define P3_DBG_CON0 P33_ACCESS(0xaa)
|
||||
#define P3_DBG_CON1 P33_ACCESS(0xab)
|
||||
#define P3_MFIX_OPT P33_ACCESS(0xac)
|
||||
|
||||
//............. 0X00B0 - 0X00BF............ for EFUSE
|
||||
#define P3_EFUSE_CON0 P33_ACCESS(0xb0)
|
||||
#define P3_EFUSE_CON1 P33_ACCESS(0xb1)
|
||||
#define P3_EFUSE_CON2 P33_ACCESS(0xb2)
|
||||
#define P3_EFUSE_RDAT P33_ACCESS(0xb3)
|
||||
#define P3_EFUSE_PU_DAT0 P33_ACCESS(0xb4)
|
||||
#define P3_EFUSE_PU_DAT1 P33_ACCESS(0xb5)
|
||||
#define P3_EFUSE_PU_DAT2 P33_ACCESS(0xb6)
|
||||
#define P3_EFUSE_PU_DAT3 P33_ACCESS(0xb7)
|
||||
|
||||
#define P3_FUNC_EN P33_ACCESS(0xb8)
|
||||
#define P3_FUNC_CTL0 P33_ACCESS(0xb9)
|
||||
#define P3_FUNC_CTL1 P33_ACCESS(0xba)
|
||||
#define P3_FUNC_CTL2 P33_ACCESS(0xbb)
|
||||
#define P3_EFUSE_ANA0 P33_ACCESS(0xbc)
|
||||
|
||||
//............. 0X00C0 - 0X00CF............ for port input select
|
||||
#define P3_PORT_SEL0 P33_ACCESS(0xc0)
|
||||
#define P3_PORT_SEL1 P33_ACCESS(0xc1)
|
||||
#define P3_PORT_SEL2 P33_ACCESS(0xc2)
|
||||
#define P3_PORT_SEL3 P33_ACCESS(0xc3)
|
||||
#define P3_PORT_SEL4 P33_ACCESS(0xc4)
|
||||
#define P3_PORT_SEL5 P33_ACCESS(0xc5)
|
||||
#define P3_PORT_SEL6 P33_ACCESS(0xc6)
|
||||
#define P3_PORT_SEL7 P33_ACCESS(0xc7)
|
||||
|
||||
//............. 0x00d0 - 0x00df............
|
||||
#define P3_LS_IO_USR P33_ACCESS(0xd0) //TODO: check sync with verilog head file chip_def.v LEVEL_SHIFTER
|
||||
#define P3_LS_IO_ROM P33_ACCESS(0xd1)
|
||||
#define P3_LS_IO_PINR P33_ACCESS(0xd2)
|
||||
#define P3_LS_CTMU P33_ACCESS(0xd3)
|
||||
#define P3_LS_IO_SHA P33_ACCESS(0xd4)
|
||||
#define P3_LS_LRC24M P33_ACCESS(0xd5)
|
||||
#define P3_LS_BT P33_ACCESS(0xd6)
|
||||
#define P3_LS_PLL P33_ACCESS(0xd7)
|
||||
|
||||
//............. 0X00E0 - 0X00FF............ for p33 lp timer
|
||||
#define P3_LP_RSC00 P33_ACCESS(0xe0)
|
||||
#define P3_LP_RSC01 P33_ACCESS(0xe1)
|
||||
#define P3_LP_RSC02 P33_ACCESS(0xe2)
|
||||
#define P3_LP_RSC03 P33_ACCESS(0xe3)
|
||||
#define P3_LP_PRD00 P33_ACCESS(0xe4)
|
||||
#define P3_LP_PRD01 P33_ACCESS(0xe5)
|
||||
#define P3_LP_PRD02 P33_ACCESS(0xe6)
|
||||
#define P3_LP_PRD03 P33_ACCESS(0xe7)
|
||||
#define P3_LP_RSC10 P33_ACCESS(0xe8)
|
||||
#define P3_LP_RSC11 P33_ACCESS(0xe9)
|
||||
#define P3_LP_RSC12 P33_ACCESS(0xea)
|
||||
#define P3_LP_RSC13 P33_ACCESS(0xeb)
|
||||
#define P3_LP_RSC14 P33_ACCESS(0xec)
|
||||
#define P3_LP_RSC15 P33_ACCESS(0xed)
|
||||
#define P3_LP_PRD10 P33_ACCESS(0xee)
|
||||
#define P3_LP_PRD11 P33_ACCESS(0xef)
|
||||
#define P3_LP_PRD12 P33_ACCESS(0xf0)
|
||||
#define P3_LP_PRD13 P33_ACCESS(0xf1)
|
||||
#define P3_LP_PRD14 P33_ACCESS(0xf2)
|
||||
#define P3_LP_PRD15 P33_ACCESS(0xf3)
|
||||
#define P3_LP_TMR0_CLK P33_ACCESS(0xf4)
|
||||
#define P3_LP_TMR1_CLK P33_ACCESS(0xf5)
|
||||
#define P3_LP_TMR0_CON P33_ACCESS(0xf6)
|
||||
#define P3_LP_TMR1_CON P33_ACCESS(0xf7)
|
||||
#define P3_LP_TMR_CFG P33_ACCESS(0xf8)
|
||||
#define P3_LP_CNTRD0 P33_ACCESS(0xf9)
|
||||
#define P3_LP_CNT0 P33_ACCESS(0xfa)
|
||||
#define P3_LP_CNT1 P33_ACCESS(0xfb)
|
||||
#define P3_LP_CNT2 P33_ACCESS(0xfc)
|
||||
#define P3_LP_CNT3 P33_ACCESS(0xfd)
|
||||
#define P3_LP_CNT4 P33_ACCESS(0xfe)
|
||||
#define P3_LP_CNT5 P33_ACCESS(0xff)
|
||||
|
||||
|
||||
|
||||
//===============================================================================//
|
||||
//
|
||||
// P33 RTCVDD
|
||||
//
|
||||
//===============================================================================//
|
||||
|
||||
//............. 0X0080 - 0X008F............ for RTC
|
||||
#define R3_ALM_CON RTC_ACCESS(0x80)
|
||||
|
||||
#define R3_RTC_CON0 RTC_ACCESS(0x84)
|
||||
#define R3_RTC_CON1 RTC_ACCESS(0x85)
|
||||
#define R3_RTC_DAT0 RTC_ACCESS(0x86)
|
||||
#define R3_RTC_DAT1 RTC_ACCESS(0x87)
|
||||
#define R3_RTC_DAT2 RTC_ACCESS(0x88)
|
||||
#define R3_RTC_DAT3 RTC_ACCESS(0x89)
|
||||
#define R3_RTC_DAT4 RTC_ACCESS(0x8a)
|
||||
#define R3_ALM_DAT0 RTC_ACCESS(0x8b)
|
||||
#define R3_ALM_DAT1 RTC_ACCESS(0x8c)
|
||||
#define R3_ALM_DAT2 RTC_ACCESS(0x8d)
|
||||
#define R3_ALM_DAT3 RTC_ACCESS(0x8e)
|
||||
#define R3_ALM_DAT4 RTC_ACCESS(0x8f)
|
||||
|
||||
//............. 0X0090 - 0X009F............ for wake up
|
||||
#define R3_WKUP_EN RTC_ACCESS(0x90)
|
||||
#define R3_WKUP_EDGE RTC_ACCESS(0x91)
|
||||
#define R3_WKUP_CPND RTC_ACCESS(0x92)
|
||||
#define R3_WKUP_PND RTC_ACCESS(0x93)
|
||||
#define R3_WKUP_LEVEL RTC_ACCESS(0x94)
|
||||
|
||||
//............. 0X00A0 - 0X00AF............ for system
|
||||
#define R3_TIME_CON RTC_ACCESS(0xa0)
|
||||
#define R3_TIME_CPND RTC_ACCESS(0xa1)
|
||||
#define R3_TIME_PND RTC_ACCESS(0xa2)
|
||||
|
||||
#define R3_ADC_CON RTC_ACCESS(0xa4)
|
||||
#define R3_OSL_CON RTC_ACCESS(0xa5)
|
||||
|
||||
#define R3_WKUP_SRC RTC_ACCESS(0xa8)
|
||||
#define R3_RST_SRC RTC_ACCESS(0xa9)
|
||||
|
||||
#define R3_RST_CON RTC_ACCESS(0xab)
|
||||
#define R3_CLK_CON RTC_ACCESS(0xac)
|
||||
|
||||
//............. 0X00B0 - 0X00BF............ for PORT control
|
||||
#define R3_PR_IN RTC_ACCESS(0xb0)
|
||||
#define R3_PR_OUT RTC_ACCESS(0xb1)
|
||||
#define R3_PR_DIR RTC_ACCESS(0xb2)
|
||||
#define R3_PR_DIE RTC_ACCESS(0xb3)
|
||||
#define R3_PR_PU0 RTC_ACCESS(0xb4)
|
||||
#define R3_PR_PU1 RTC_ACCESS(0xb5)
|
||||
#define R3_PR_PD0 RTC_ACCESS(0xb6)
|
||||
#define R3_PR_PD1 RTC_ACCESS(0xb7)
|
||||
#define R3_PR_HD0 RTC_ACCESS(0xb8)
|
||||
#define R3_PR_HD1 RTC_ACCESS(0xb9)
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,17 @@
|
||||
#ifndef __TIMER_H__
|
||||
#define __TIMER_H__
|
||||
|
||||
|
||||
#include "typedef.h"
|
||||
|
||||
|
||||
u32 tmr_2ms_cnt_get(void);
|
||||
|
||||
void sys_tmr_init(void (*cb)(void));
|
||||
|
||||
void sys_tmr_close(void);
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,10 @@
|
||||
#ifndef __UART_H__
|
||||
#define __UART_H__
|
||||
|
||||
#include "typedef.h"
|
||||
|
||||
int putchar(int a);
|
||||
void uart_init(const char *tx_io, u32 baud);
|
||||
void uart_close(void);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,32 @@
|
||||
#ifndef __WDT_H__
|
||||
#define __WDT_H__
|
||||
|
||||
#include "typedef.h"
|
||||
|
||||
enum {
|
||||
WDT_1ms = 0,
|
||||
WDT_2ms,
|
||||
WDT_4ms,
|
||||
WDT_8ms,
|
||||
WDT_16ms,
|
||||
WDT_32ms,
|
||||
WDT_64ms,
|
||||
WDT_128ms,
|
||||
WDT_256ms,
|
||||
WDT_512ms,
|
||||
WDT_1s,
|
||||
WDT_2s,
|
||||
WDT_4s,
|
||||
WDT_8s,
|
||||
WDT_16s,
|
||||
WDT_32s,
|
||||
};
|
||||
|
||||
|
||||
void wdt_init(u32 level);
|
||||
|
||||
void wdt_clear();
|
||||
|
||||
|
||||
#endif /*WDT_H*/
|
||||
|
||||
Reference in New Issue
Block a user