初版
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huxi
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@@ -0,0 +1,41 @@
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#ifndef __Q32DSP_CACHE__
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#define __Q32DSP_CACHE__
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#include "icache.h"
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#include "dcache.h"
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//#include "generic/typedef.h"
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typedef struct __cache_info {
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unsigned int cache_type; // 0:icache; 1:dcache
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unsigned int cpu_id;
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unsigned int efficiency;
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} CACHE_INFO;
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#if 0 // 供外界使用的接口,已经在 icache.h 和 rocache.h 中定义
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// void flush_dcache(void *ptr, int len);
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// void flushinv_dcache(void *ptr, int len);
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void IcuEnable(void);
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void DcuEnable(void);
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void IcuWaitIdle(void);
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void DcuWaitIdle(void);
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void IcuDisable(void);
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void DcuDisable(void);
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void IcuFlushinvAll(void);
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void IcuUnlockAll(void);
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void IcuFlushinvRegion(int *beg, int len);
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void IcuUnlockRegion(int *beg, int len);
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void IcuLockRegion(int *beg, int len);
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void IcuPfetchRegion(int *beg, int len);
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void DcuFlushinvAll(void);
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void DcuFlushinvRegion(int *beg, int len);
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void DcuPfetchRegion(int *beg, int len);
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void IcuInitial(void);
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void DcuInitial(void);
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#endif
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#define WAIT_DCACHE_IDLE do {DcuWaitIdle();} while(0);
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#define WAIT_ICACHE_IDLE do {IcuWaitIdle();} while(0);
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//#define WAIT_DCACHE_IDLE do{asm volatile("csync"); while(!(JL_DCU->CON & BIT(31)));} while(0);
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#endif
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@@ -0,0 +1,170 @@
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#ifndef _CHARGE_H_
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#define _CHARGE_H_
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#include "typedef.h"
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#include "device.h"
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/*------充满电电压选择 4.044V-4.634V-------*/
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//4.2V电池配置0~15
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#define CHARGE_FULL_V_4040_4P2V 0
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#define CHARGE_FULL_V_4060_4P2V 1
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#define CHARGE_FULL_V_4080_4P2V 2
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#define CHARGE_FULL_V_4100_4P2V 3
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#define CHARGE_FULL_V_4120_4P2V 4
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#define CHARGE_FULL_V_4140_4P2V 5
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#define CHARGE_FULL_V_4160_4P2V 6
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#define CHARGE_FULL_V_4180_4P2V 7
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#define CHARGE_FULL_V_4200_4P2V 8
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#define CHARGE_FULL_V_4220_4P2V 9
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#define CHARGE_FULL_V_4240_4P2V 10
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#define CHARGE_FULL_V_4260_4P2V 11
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#define CHARGE_FULL_V_4280_4P2V 12
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#define CHARGE_FULL_V_4300_4P2V 13
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#define CHARGE_FULL_V_4320_4P2V 14
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#define CHARGE_FULL_V_4340_4P2V 15
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//4.4V电池配置16~31
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#define CHARGE_FULL_V_4240_4P4V 16
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#define CHARGE_FULL_V_4260_4P4V 17
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#define CHARGE_FULL_V_4280_4P4V 18
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#define CHARGE_FULL_V_4300_4P4V 19
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#define CHARGE_FULL_V_4320_4P4V 20
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#define CHARGE_FULL_V_4340_4P4V 21
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#define CHARGE_FULL_V_4360_4P4V 22
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#define CHARGE_FULL_V_4380_4P4V 23
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#define CHARGE_FULL_V_4400_4P4V 24
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#define CHARGE_FULL_V_4420_4P4V 25
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#define CHARGE_FULL_V_4440_4P4V 26
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#define CHARGE_FULL_V_4460_4P4V 27
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#define CHARGE_FULL_V_4480_4P4V 28
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#define CHARGE_FULL_V_4500_4P4V 29
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#define CHARGE_FULL_V_4520_4P4V 30
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#define CHARGE_FULL_V_4540_4P4V 31
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//4.5V电池配置32-47
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#define CHARGE_FULL_V_4340_4P5V 32
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#define CHARGE_FULL_V_4360_4P5V 33
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#define CHARGE_FULL_V_4380_4P5V 34
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#define CHARGE_FULL_V_4400_4P5V 35
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#define CHARGE_FULL_V_4420_4P5V 36
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#define CHARGE_FULL_V_4440_4P5V 37
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#define CHARGE_FULL_V_4460_4P5V 38
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#define CHARGE_FULL_V_4480_4P5V 39
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#define CHARGE_FULL_V_4500_4P5V 40
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#define CHARGE_FULL_V_4520_4P5V 41
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#define CHARGE_FULL_V_4540_4P5V 42
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#define CHARGE_FULL_V_4560_4P5V 43
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#define CHARGE_FULL_V_4580_4P5V 44
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#define CHARGE_FULL_V_4600_4P5V 45
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#define CHARGE_FULL_V_4620_4P5V 46
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#define CHARGE_FULL_V_4640_4P5V 47
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#define CHARGE_FULL_V_MAX 48
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/*
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充电电流选择
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恒流：40-300mA
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*/
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#define CHARGE_mA_40 0
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#define CHARGE_mA_50 1
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#define CHARGE_mA_60 2
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#define CHARGE_mA_70 3
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#define CHARGE_mA_80 4
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#define CHARGE_mA_100 5
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#define CHARGE_mA_120 6
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#define CHARGE_mA_140 7
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#define CHARGE_mA_160 8
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#define CHARGE_mA_180 9
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#define CHARGE_mA_200 10
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#define CHARGE_mA_220 11
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#define CHARGE_mA_240 12
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#define CHARGE_mA_260 13
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#define CHARGE_mA_280 14
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#define CHARGE_mA_300 15
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#define CHARGE_mA_4 (BIT(4)|CHARGE_mA_40)
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#define CHARGE_mA_5 (BIT(4)|CHARGE_mA_50)
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#define CHARGE_mA_6 (BIT(4)|CHARGE_mA_60)
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#define CHARGE_mA_7 (BIT(4)|CHARGE_mA_70)
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#define CHARGE_mA_8 (BIT(4)|CHARGE_mA_80)
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#define CHARGE_mA_10 (BIT(4)|CHARGE_mA_100)
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#define CHARGE_mA_12 (BIT(4)|CHARGE_mA_120)
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#define CHARGE_mA_14 (BIT(4)|CHARGE_mA_140)
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#define CHARGE_mA_16 (BIT(4)|CHARGE_mA_160)
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#define CHARGE_mA_18 (BIT(4)|CHARGE_mA_180)
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#define CHARGE_mA_20 (BIT(4)|CHARGE_mA_200)
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#define CHARGE_mA_22 (BIT(4)|CHARGE_mA_220)
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#define CHARGE_mA_24 (BIT(4)|CHARGE_mA_240)
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#define CHARGE_mA_26 (BIT(4)|CHARGE_mA_260)
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#define CHARGE_mA_28 (BIT(4)|CHARGE_mA_280)
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#define CHARGE_mA_30 (BIT(4)|CHARGE_mA_300)
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#define CHARGE_TRICKLE_EN BIT(4)
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/* 充电口下拉电阻 50k ~ 200k */
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#define CHARGE_PULLDOWN_50K 0
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#define CHARGE_PULLDOWN_100K 1
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#define CHARGE_PULLDOWN_150K 2
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#define CHARGE_PULLDOWN_200K 3
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#define CHARGE_CCVOL_V 300 //涓流充电向恒流充电的转换点
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#define DEVICE_EVENT_FROM_CHARGE (('C' << 24) | ('H' << 16) | ('G' << 8) | '\0')
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struct charge_platform_data {
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u8 charge_en; //内置充电使能
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u8 charge_poweron_en; //开机充电使能
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u8 charge_full_V; //充满电电压大小
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u8 charge_full_mA; //充满电电流大小
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u16 charge_mA; //恒流充电电流大小
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u16 charge_trickle_mA; //涓流充电电流大小
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u8 ldo5v_pulldown_en; //下拉使能位
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u8 ldo5v_pulldown_lvl; //ldo5v的下拉电阻配置项,若充电舱需要更大的负载才能检测到插入时，请将该变量置为对应阻值
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u8 ldo5v_pulldown_keep; //下拉电阻在softoff时是否保持,ldo5v_pulldown_en=1时有效
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u16 ldo5v_off_filter; //ldo5v拔出过滤值，过滤时间 = (filter*2 + 20)ms,ldoin<0.6V且时间大于过滤时间才认为拔出,对于充满直接从5V掉到0V的充电仓，该值必须设置成0，对于充满由5V先掉到0V之后再升压到xV的充电仓，需要根据实际情况设置该值大小
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u16 ldo5v_on_filter; //ldo5v>vbat插入过滤值,电压的过滤时间 = (filter*2)ms
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u16 ldo5v_keep_filter; //1V<ldo5v<vbat维持电压过滤值,过滤时间= (filter*2)ms
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u16 charge_full_filter; //充满过滤值,连续检测充满信号恒为1才认为充满,过滤时间 = (filter*2)ms
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};
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#define CHARGE_PLATFORM_DATA_BEGIN(data) \
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struct charge_platform_data data = {
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#define CHARGE_PLATFORM_DATA_END() \
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};
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enum {
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CHARGE_EVENT_CHARGE_START,
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CHARGE_EVENT_CHARGE_CLOSE,
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CHARGE_EVENT_CHARGE_FULL,
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CHARGE_EVENT_LDO5V_KEEP,
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CHARGE_EVENT_LDO5V_IN,
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CHARGE_EVENT_LDO5V_OFF,
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};
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//使用的电池类型
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enum {
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BAT_4P2, //4.2V的电池
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BAT_4P4,
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BAT_4P5,
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};
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void set_charge_event_flag(u8 flag);
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void set_charge_online_flag(u8 flag);
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void set_charge_event_flag(u8 flag);
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u8 get_charge_online_flag(void);
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u8 get_charge_poweron_en(void);
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void set_charge_poweron_en(u32 onOff);
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void charge_start(void);
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void charge_close(void);
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u8 get_charge_mA_config(void);
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void set_charge_mA(u8 charge_mA);
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u8 get_ldo5v_pulldown_en(void);
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u8 get_ldo5v_pulldown_res(void);
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u8 get_ldo5v_online_hw(void);
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u8 get_lvcmp_det(void);
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void charge_check_and_set_pinr(u8 mode);
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u16 get_charge_full_value(void);
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void charge_module_stop(void);
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void charge_module_restart(void);
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void ldoin_wakeup_isr(void);
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int charge_init(const struct charge_platform_data *data);
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void charge_set_ldo5v_detect_stop(u8 stop);
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u8 check_pinr_shutdown_enable(void);
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#endif //_CHARGE_H_
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@@ -0,0 +1,83 @@
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#ifndef __BR28_CHARGESTORE_H__
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#define __BR28_CHARGESTORE_H__
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#include "generic/typedef.h"
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enum {
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CMD_COMPLETE,
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CMD_RECVDATA,
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};
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enum {
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MODE_RECVDATA,
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MODE_SENDDATA,
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};
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enum {
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TYPE_NORMAL,
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TYPE_F95,
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};
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#define PROTOCAL_DEFAULT 0
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#define PROTOCAL_LOADER 1
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#define LDOIN_BIND_IO IO_PORTP_00
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struct chargestore_platform_data {
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u32 baudrate;
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u32 io_port;
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u8 uart_irq;
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void (*init)(const struct chargestore_platform_data *);
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void (*open)(u8 mode);
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void (*close)(void);
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void (*write)(u8 *, u8);
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};
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struct chargestore_data_handler {
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int (*data_cb)(u8 *buf, u8 len);
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};
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#define CHARGESTORE_HANDLE_REG(name, data_callback) \
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const struct chargestore_data_handler chargestore_##name \
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SEC_USED(.chargestore_callback_txt) = {data_callback};
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extern struct chargestore_data_handler chargestore_handler_begin[];
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extern struct chargestore_data_handler chargestore_handler_end[];
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#define list_for_each_loop_chargestore(h) \
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for (h=chargestore_handler_begin; h<chargestore_handler_end; h++)
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#define CHARGESTORE_PLATFORM_DATA_BEGIN(data) \
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static const struct chargestore_platform_data data = {
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#define CHARGESTORE_PLATFORM_DATA_END() \
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.baudrate = 9600, \
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.init = chargestore_init, \
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.open = chargestore_open, \
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.close = chargestore_close, \
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.write = chargestore_write, \
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};
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void chargestore_open(u8 mode);
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void chargestore_close(void);
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void chargestore_write(u8 *data, u8 len);
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void chargestore_init(const struct chargestore_platform_data *);
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void chargestore_set_update_ram(void);
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u8 chargestore_get_det_level(u8 chip_type);
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//app层使用的接口
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void chargestore_api_close(void);
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int chargestore_api_write(u8 *buf, u8 len);
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void chargestore_api_init(const struct chargestore_platform_data *arg);
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void chargestore_api_wait_complete(void);
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void chargestore_api_set_timeout(u16 timeout);
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void chargestore_api_stop(void);
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void chargestore_api_restart(void);
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u8 chargestore_api_crc8(u8 *ptr, u8 len);
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int loader_uart_write(u8 *buf, u8 len);
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void chargestore_set_protocal(u8 protocal);
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void chargestore_set_loader_update_callback(void (*loader_callback)(void *p, void *buf, u32 len));
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void chargestore_ldo5v_fall_deal(void);
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void chargestore_set_baudrate(u32 baudrate);
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#endif
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@@ -0,0 +1,124 @@
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#ifndef __CLOCK_HAL_H__
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#define __CLOCK_HAL_H__
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#include "typedef.h"
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enum CLK_OUT_SOURCE0 {
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CLK_OUT_SRC0_NULL = 0,
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CLK_OUT_SRC0_LRC_CLK,
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CLK_OUT_SRC0_STD_12M,
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CLK_OUT_SRC0_STD_24M,
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CLK_OUT_SRC0_STD_48M,
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CLK_OUT_SRC0_BTOSC_24M,
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CLK_OUT_SRC0_BTOSC_48M,
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CLK_OUT_SRC0_HSB_CLK,
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CLK_OUT_SRC0_LSB_CLK,
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CLK_OUT_SRC0_PLL_96M,
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CLK_OUT_SRC0_RC_250K,
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CLK_OUT_SRC0_RC_16M,
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CLK_OUT_SRC0_LRC_24M,
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CLK_OUT_SRC0_ALNK0_CLK,
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CLK_OUT_SRC0_RF_CKO_CLK,
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CLK_OUT_SRC0_USB_CLK,
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};
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enum CLK_OUT_SOURCE1 {
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CLK_OUT_SRC2_NULL = 0,
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CLK_OUT_SRC2_SYS_PLL_D3P5 = 4,
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CLK_OUT_SRC2_SYS_PLL_D2P5,
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CLK_OUT_SRC2_SYS_PLL_D2P0,
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CLK_OUT_SRC2_SYS_PLL_D1P5,
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CLK_OUT_SRC2_SYS_PLL_D1P0,
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};
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void clk_out0(u8 gpio, enum CLK_OUT_SOURCE0 clk);
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void clk_out2(u8 gpio, enum CLK_OUT_SOURCE1 clk, u8 div);
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//无 clk_out1
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void clk_out0_close(u8 gpio);
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void clk_out2_close(u8 gpio);
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enum CLK_OUT_SOURCE {
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//ch0,ch1. no div
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CLK_OUT_NULL = 0x0100,
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CLK_OUT_LRC_CLK,
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CLK_OUT_STD_12M,
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CLK_OUT_STD_24M,
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CLK_OUT_STD_48M,
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CLK_OUT_BTOSC_24M,
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CLK_OUT_BTOSC_48M,
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CLK_OUT_HSB_CLK,
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CLK_OUT_LSB_CLK,
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CLK_OUT_PLL_96M,
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CLK_OUT_RC_250K,
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CLK_OUT_RC_16M,
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CLK_OUT_LRC_24M,
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CLK_OUT_ALNK0_CLK,
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CLK_OUT_RF_CKO_CLK,
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CLK_OUT_USB_CLK,
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//ch2. div:0~63(div1~div64)
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CLK_OUT_NULL_DIV = 0x0400,
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CLK_OUT_SYS_PLL_D3P5_DIV = 0x0404,
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CLK_OUT_SYS_PLL_D2P5_DIV,
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CLK_OUT_SYS_PLL_D2P0_DIV,
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CLK_OUT_SYS_PLL_D1P5_DIV,
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CLK_OUT_SYS_PLL_D1P0_DIV,
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};
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#define CLK_OUT_CH_MASK 0b111
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#define CLK_OUT_CH0_SEL(clk) SFR(JL_LSBCLK->STD_CON1,0,5,clk)
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#define CLK_OUT_CH0_GET_CLK() ((JL_LSBCLK->STD_CON1>>0)&0x01f)
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#define CLK_OUT_CH0_DIV(div) //no div
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#define CLK_OUT_CH0_EN(en) //no en
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#define CLK_OUT0_FIXED_IO_EN(en) //no en
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#define IS_CLK_OUT0_FIXED_IO() (0)//no fix
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#define CLK_OUT_CH1_SEL(clk) SFR(JL_LSBCLK->STD_CON1,5,5,clk)
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#define CLK_OUT_CH1_GET_CLK() ((JL_LSBCLK->STD_CON1>>5)&0x01f)
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#define CLK_OUT_CH1_DIV(div) //no div
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#define CLK_OUT_CH1_EN(en) //no en
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#define CLK_OUT1_FIXED_IO_EN(en) //no en
|
||||
#define IS_CLK_OUT1_FIXED_IO() (0)//no fix
|
||||
|
||||
#define CLK_OUT_CH2_SEL(clk) SFR(JL_LSBCLK->STD_CON1,10,4,clk)
|
||||
#define CLK_OUT_CH2_GET_CLK() ((JL_LSBCLK->STD_CON1>>10)&0x0f)
|
||||
#define CLK_OUT_CH2_DIV(div) SFR(JL_LSBCLK->STD_CON1,14,6,div)
|
||||
#define CLK_OUT_CH2_EN(en) //no en
|
||||
#define CLK_OUT2_FIXED_IO_EN(en) //no en
|
||||
#define IS_CLK_OUT2_FIXED_IO() (0)//no fix
|
||||
|
||||
#define CLK_OUT_CH3_SEL(clk) //no ch3
|
||||
#define CLK_OUT_CH3_GET_CLK() (0)//no ch3
|
||||
#define CLK_OUT_CH3_DIV(div) //no div
|
||||
#define CLK_OUT_CH3_EN(en) //no en
|
||||
#define CLK_OUT3_FIXED_IO_EN(en) //no en
|
||||
#define IS_CLK_OUT3_FIXED_IO() (0)//no fix
|
||||
|
||||
#define CLK_OUT_CH4_SEL(clk) //no ch4
|
||||
#define CLK_OUT_CH4_GET_CLK() (0)//no ch4
|
||||
#define CLK_OUT_CH4_DIV(div) //no div
|
||||
#define CLK_OUT_CH4_EN(en) //no en
|
||||
#define CLK_OUT4_FIXED_IO_EN(en) //no en
|
||||
#define IS_CLK_OUT4_FIXED_IO() (0)//no fix
|
||||
u32 clk_out_fixed_io_check(u32 gpio);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//for bt
|
||||
void clk_set_osc_cap(u8 sel_l, u8 sel_r);
|
||||
u32 clk_get_osc_cap();
|
||||
|
||||
#define BT_CLOCK_IN(x) //SFR(JL_CLOCK->CLK_CON1, 14, 2, x)
|
||||
//for MACRO - BT_CLOCK_IN
|
||||
enum {
|
||||
BT_CLOCK_IN_PLL48M = 0,
|
||||
BT_CLOCK_IN_HSB,
|
||||
BT_CLOCK_IN_LSB,
|
||||
BT_CLOCK_IN_DISABLE,
|
||||
};
|
||||
|
||||
|
||||
#endif /*CLOCK_HAL_H*/
|
||||
@@ -0,0 +1,278 @@
|
||||
|
||||
#ifndef ASM_CPU_H
|
||||
#define ASM_CPU_H
|
||||
|
||||
|
||||
#include "br35.h"
|
||||
#include "csfr.h"
|
||||
#include "cache.h"
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#if ((!defined __cplusplus) && (!defined BOOL_DEFINE_CONFLICT))
|
||||
typedef unsigned char bool;
|
||||
#endif
|
||||
typedef unsigned char u8, BOOL;
|
||||
typedef char s8;
|
||||
typedef unsigned short u16;
|
||||
typedef signed short s16;
|
||||
typedef unsigned int u32;
|
||||
typedef signed int s32;
|
||||
typedef unsigned long long u64;
|
||||
typedef u32 FOURCC;
|
||||
typedef long long s64;
|
||||
typedef unsigned long long u64;
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#define ___trig __asm__ volatile ("trigger")
|
||||
|
||||
|
||||
#ifndef BIG_ENDIAN
|
||||
#define BIG_ENDIAN 0x3021
|
||||
#endif
|
||||
#ifndef LITTLE_ENDIAN
|
||||
#define LITTLE_ENDIAN 0x4576
|
||||
#endif
|
||||
#define CPU_ENDIAN LITTLE_ENDIAN
|
||||
|
||||
|
||||
#define CPU_CORE_NUM 1
|
||||
|
||||
#define CONFIG_SPINLOCK_ENABLE 0
|
||||
|
||||
#define OS_CORE_AFFINITY_ENABLE CONFIG_OS_AFFINITY_ENABLE //app_cfg.mk中定义, Modify Me: 0: 自由分配, 1: 固定核
|
||||
|
||||
extern const int CONFIG_CPU_UNMASK_IRQ_ENABLE;
|
||||
///屏蔽的优先级, < N的优先级不可以响应
|
||||
#define CPU_IRQ_IPMASK_LEVEL 6
|
||||
|
||||
#define CPU_TASK_CLR(a)
|
||||
#define CPU_TASK_SW(a) \
|
||||
do { \
|
||||
q32DSP(a)->ILAT_SET |= BIT(3-a); \
|
||||
} while (0)
|
||||
|
||||
|
||||
#define CPU_INT_NESTING 2
|
||||
|
||||
#define CORE_IDLE_TICK_TIMER_PERIOD 4000 //10 ~ 16000 ms
|
||||
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#if CPU_CORE_NUM > 1
|
||||
__attribute__((always_inline))
|
||||
static int current_cpu_id()
|
||||
{
|
||||
unsigned id;
|
||||
asm volatile("%0 = cnum" : "=r"(id) ::);
|
||||
return id ;
|
||||
}
|
||||
|
||||
__attribute__((always_inline))
|
||||
static int core_num(void)
|
||||
{
|
||||
u32 num;
|
||||
asm volatile("%0 = cnum" : "=r"(num) :);
|
||||
return num;
|
||||
}
|
||||
|
||||
#else
|
||||
static inline int current_cpu_id()
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int core_num(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static inline int cpu_in_irq()
|
||||
{
|
||||
int flag;
|
||||
__asm__ volatile("%0 = icfg" : "=r"(flag));
|
||||
return flag & 0xff;
|
||||
}
|
||||
|
||||
extern int __cpu_irq_disabled();
|
||||
static inline int cpu_irq_disabled()
|
||||
{
|
||||
int flag;
|
||||
int ret;
|
||||
|
||||
if (CONFIG_CPU_UNMASK_IRQ_ENABLE) {
|
||||
return __cpu_irq_disabled();
|
||||
} else {
|
||||
__asm__ volatile("%0 = icfg" : "=r"(flag));
|
||||
ret = ((flag & 0x300) != 0x300);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#if 0
|
||||
static inline int data_sat_s16(int ind)
|
||||
{
|
||||
if (ind > 32767) {
|
||||
ind = 32767;
|
||||
} else if (ind < -32768) {
|
||||
ind = -32768;
|
||||
}
|
||||
return ind;
|
||||
}
|
||||
|
||||
#else
|
||||
static inline int data_sat_s16(int ind)
|
||||
{
|
||||
__asm__ volatile(
|
||||
" %0 = sat16(%0)(s) \t\n"
|
||||
: "=&r"(ind)
|
||||
: "0"(ind)
|
||||
:);
|
||||
return ind;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
static inline u32 reverse_u32(u32 data32)
|
||||
{
|
||||
#if 0
|
||||
u8 *dataptr = (u8 *)(&data32);
|
||||
data32 = (((u32)dataptr[0] << 24) | ((u32)dataptr[1] << 16) | ((u32)dataptr[2] << 8) | (u32)dataptr[3]);
|
||||
#else
|
||||
__asm__ volatile("%0 = rev8(%0) \t\n" : "=&r"(data32) : "0"(data32) :);
|
||||
#endif
|
||||
return data32;
|
||||
}
|
||||
|
||||
static inline u32 reverse_u16(u16 data16)
|
||||
{
|
||||
u32 retv;
|
||||
#if 0
|
||||
u8 *dataptr = (u8 *)(&data16);
|
||||
retv = (((u32)dataptr[0] << 8) | ((u32)dataptr[1]));
|
||||
#else
|
||||
retv = ((u32)data16) << 16;
|
||||
__asm__ volatile("%0 = rev8(%0) \t\n" : "=&r"(retv) : "0"(retv) :);
|
||||
#endif
|
||||
return retv;
|
||||
}
|
||||
|
||||
static inline u32 rand32()
|
||||
{
|
||||
return JL_RAND->R64L;
|
||||
}
|
||||
|
||||
#define __asm_sine(s64, precision) \
|
||||
({ \
|
||||
u64 ret; \
|
||||
u8 sel = 0; \
|
||||
__asm__ volatile ("%0 = copex(%1) (%2)" : "=r"(ret) : "r"(s64), "i"(sel)); \
|
||||
ret = ret>>32; \
|
||||
ret;\
|
||||
})
|
||||
|
||||
void p33_soft_reset(void);
|
||||
static inline void cpu_reset(void)
|
||||
{
|
||||
// JL_CLOCK->PWR_CON |= (1 << 4);
|
||||
p33_soft_reset();
|
||||
}
|
||||
|
||||
#define __asm_csync() \
|
||||
do { \
|
||||
asm volatile("csync;"); \
|
||||
} while (0)
|
||||
|
||||
#include "asm/irq.h"
|
||||
#include "generic/printf.h"
|
||||
#include "generic/log.h"
|
||||
|
||||
|
||||
#define arch_atomic_read(v) \
|
||||
({ \
|
||||
__asm_csync(); \
|
||||
(*(volatile int *)&(v)->counter); \
|
||||
})
|
||||
|
||||
static inline void q32DSP_testset(u8 volatile *ptr)
|
||||
{
|
||||
asm volatile(
|
||||
" 1: \n\t "
|
||||
" testset b[%0] \n\t "
|
||||
" ifeq goto 1b \n\t "
|
||||
:
|
||||
: "p"(ptr)
|
||||
: "memory"
|
||||
);
|
||||
}
|
||||
|
||||
static inline void q32DSP_testclr(u8 volatile *ptr)
|
||||
{
|
||||
asm volatile(
|
||||
" b[%0] = %1 \n\t "
|
||||
:
|
||||
: "p"(ptr), "r"(0)
|
||||
: "memory"
|
||||
);
|
||||
}
|
||||
|
||||
#define arch_spin_lock(lock) \
|
||||
do { \
|
||||
q32DSP_testset(&lock->rwlock);\
|
||||
}while(0)
|
||||
|
||||
#define arch_spin_unlock(lock) \
|
||||
do{ \
|
||||
q32DSP_testclr(&lock->rwlock) ;\
|
||||
}while(0)
|
||||
|
||||
|
||||
|
||||
extern void local_irq_disable();
|
||||
extern void local_irq_enable();
|
||||
|
||||
#define CPU_SR_ALLOC() \
|
||||
// int flags
|
||||
|
||||
#define CPU_CRITICAL_ENTER() \
|
||||
do { \
|
||||
local_irq_disable(); \
|
||||
}while(0)
|
||||
|
||||
|
||||
#define CPU_CRITICAL_EXIT() \
|
||||
do { \
|
||||
local_irq_enable(); \
|
||||
}while(0)
|
||||
|
||||
|
||||
|
||||
extern void cpu_assert_debug();
|
||||
extern const int config_asser;
|
||||
#define ASSERT(a,...) \
|
||||
do { \
|
||||
if(config_asser){\
|
||||
if(!(a)){ \
|
||||
printf("cpu %d file:%s, line:%d",current_cpu_id(), __FILE__, __LINE__); \
|
||||
printf("ASSERT-FAILD: "#a" "__VA_ARGS__); \
|
||||
while(1);/*cpu_assert_debug();*/ \
|
||||
} \
|
||||
}else {\
|
||||
if(!(a)){ \
|
||||
cpu_reset(); \
|
||||
}\
|
||||
}\
|
||||
}while(0);
|
||||
|
||||
|
||||
|
||||
#endif //__ASSEMBLY__
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,35 @@
|
||||
#ifndef __CPU_CRC16_H__
|
||||
#define __CPU_CRC16_H__
|
||||
|
||||
|
||||
#include "typedef.h"
|
||||
|
||||
|
||||
|
||||
u16 CRC16(const void *ptr, u32 len);
|
||||
|
||||
/* i_val: CRC校验初值 */
|
||||
u16 CRC16_with_initval(const void *ptr, u32 len, u16 i_val);
|
||||
|
||||
u16 CRC16_with_code(const void *ptr, u32 len, u16 code);
|
||||
|
||||
void spi_crc16_set(u16 crc);
|
||||
u16 spi_crc16_get(void);
|
||||
|
||||
void CrcDecode(void *buf, u16 len);
|
||||
|
||||
u16 get_page_efuse(u32 page, u32 delay_cnt);
|
||||
void init_enc_key(u8 cmd);
|
||||
u32 get_sfc_enc_key(void);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@@ -0,0 +1,425 @@
|
||||
//*********************************************************************************//
|
||||
// Module name : csfr.h //
|
||||
// Description : q32DSP core sfr define //
|
||||
// By Designer : zequan_liu //
|
||||
// Dat changed : //
|
||||
//*********************************************************************************//
|
||||
|
||||
#ifndef __Q32DSP_CSFR__
|
||||
#define __Q32DSP_CSFR__
|
||||
|
||||
#define __RW volatile // read write
|
||||
#define __RO volatile const // only read
|
||||
#define __WO volatile // only write
|
||||
|
||||
#define __u8 unsigned int // u8 to u32 special for struct
|
||||
#define __u16 unsigned int // u16 to u32 special for struct
|
||||
#define __u32 unsigned int
|
||||
|
||||
#define csfr_base 0xff0000
|
||||
|
||||
//*********************************************************************************
|
||||
//
|
||||
// hcore_sfr
|
||||
//
|
||||
//*********************************************************************************
|
||||
|
||||
//............. 0x0000 - 0x00ff............
|
||||
typedef struct {
|
||||
__RW __u32 CON0;
|
||||
__RW __u32 FTMAX;
|
||||
} JL_CMNG_TypeDef;
|
||||
|
||||
#define JL_CMNG_BASE (csfr_base + map_adr(0x00, 0x00))
|
||||
#define JL_CMNG ((JL_CMNG_TypeDef *)JL_CMNG_BASE)
|
||||
|
||||
//............. 0x0100 - 0x01ff............
|
||||
//typedef struct {
|
||||
// __RW __u32 CON;
|
||||
// __RW __u32 KEY;
|
||||
//} JL_SDTAP_TypeDef;
|
||||
|
||||
//#define JL_SDTAP_BASE (csfr_base + map_adr(0x01, 0x00))
|
||||
//#define JL_SDTAP ((JL_SDTAP_TypeDef *)JL_SDTAP_BASE)
|
||||
|
||||
//............. 0x0200 - 0x02ff............
|
||||
typedef struct {
|
||||
__RW __u32 WREN;
|
||||
__RW __u32 CON0;
|
||||
__RW __u32 CON1;
|
||||
__RW __u32 CON2;
|
||||
__RW __u32 CON3;
|
||||
__RW __u32 MSG0;
|
||||
__RW __u32 MSG1;
|
||||
__RW __u32 MSG2;
|
||||
__RW __u32 MSG3;
|
||||
__RO __u32 ID;
|
||||
} JL_CEMU_TypeDef;
|
||||
|
||||
#define JL_CEMU_BASE (csfr_base + map_adr(0x02, 0x00))
|
||||
#define JL_CEMU ((JL_CEMU_TypeDef *)JL_CEMU_BASE)
|
||||
|
||||
//............. 0x0300 - 0x03ff............
|
||||
|
||||
#define MPU_INV (1<<31)
|
||||
#define MPU_PWEN (1<<16)
|
||||
#define MPU_PREN (1<<8)
|
||||
#define MPU_PEN (MPU_PWEN | MPU_PREN)
|
||||
#define MPU_XEN (1<<2)
|
||||
#define MPU_WEN (1<<1)
|
||||
#define MPU_REN (1<<0)
|
||||
|
||||
#define MPU_IDx_cfg(n, id) (id<<(n*8))
|
||||
#define MPU_IDx_pen(n, pr, pw) ((pr<<(9+n)) | (pw<<(17+n)))
|
||||
|
||||
typedef struct {
|
||||
__RW __u32 CON[15]; // 0-1 used in br35
|
||||
__RO __u32 REV0;
|
||||
__RW __u32 CID[15]; // 0-1 used in br35
|
||||
__RO __u32 REV1;
|
||||
__RW __u32 BEG[15]; // 0-1 used in br35
|
||||
__RO __u32 REV2;
|
||||
__RW __u32 END[15]; // 0-1 used in br35
|
||||
__RW __u32 WREN;
|
||||
} JL_MPU_TypeDef;
|
||||
|
||||
#define JL_MPU_BASE (csfr_base + map_adr(0x03, 0x00))
|
||||
#define JL_MPU ((JL_MPU_TypeDef *)JL_MPU_BASE)
|
||||
|
||||
//............. 0x0400 - 0x04ff............
|
||||
|
||||
typedef struct {
|
||||
__RW __u32 CON;
|
||||
__RW __u32 TLB1_BEG;
|
||||
__RW __u32 TLB1_END;
|
||||
} JL_MMU_TypeDef;
|
||||
|
||||
#define JL_MMU_BASE (csfr_base + map_adr(0x04, 0x00))
|
||||
#define JL_MMU ((JL_MMU_TypeDef *)JL_MMU_BASE)
|
||||
|
||||
typedef struct {
|
||||
short page: 14;
|
||||
short vld: 1;
|
||||
} JL_MMU_TLB1_TypeDef;
|
||||
|
||||
#define JL_MMU_TLB1 ((JL_MMU_TLB1_TypeDef *)(JL_MMU->TLB1_BEG))
|
||||
|
||||
//............. 0x0500 - 0x05ff............
|
||||
//#define JL_TypeDef_L1P JL_TypeDef_q32DSP_ICU
|
||||
#define JL_TypeDef_L1P JL_TypeDef_q32DSP_DCU
|
||||
#define JL_L1P_BASE (csfr_base + map_adr(0x05, 0x00))
|
||||
#define JL_L1P ((JL_TypeDef_L1P *)JL_L1P_BASE)
|
||||
|
||||
//............. 0x0600 - 0x06ff............
|
||||
#define JL_TypeDef_L2I JL_TypeDef_q32DSP_ICU
|
||||
#define JL_L2I_BASE (csfr_base + map_adr(0x06, 0x00))
|
||||
#define JL_L2I ((JL_TypeDef_L2I *)JL_L2I_BASE)
|
||||
|
||||
//............. 0x0700 - 0x07ff............
|
||||
#define JL_TypeDef_L2D JL_TypeDef_q32DSP_DCU
|
||||
#define JL_L2D_BASE (csfr_base + map_adr(0x07, 0x00))
|
||||
#define JL_L2D ((JL_TypeDef_L2D *)JL_L2D_BASE)
|
||||
|
||||
//............. 0x0800 - 0x08ff............
|
||||
typedef struct {
|
||||
__RO __u32 CHIP_ID;
|
||||
__RO __u32 CHIP_VER;
|
||||
} JL_SYSTEM_TypeDef;
|
||||
|
||||
#define JL_SYSTEM_BASE (csfr_base + map_adr(0x08, 0x00))
|
||||
#define JL_SYSTEM ((JL_SYSTEM_TypeDef *)JL_SYSTEM_BASE)
|
||||
|
||||
//............. 0x0900 - 0x09ff............
|
||||
typedef struct {
|
||||
__RW __u32 CON;
|
||||
__RW __u32 BEG;
|
||||
__RW __u32 END;
|
||||
__RW __u32 DAT_VLD0;
|
||||
__RW __u32 DAT_VLD1;
|
||||
__RW __u32 DAT_VLD2;
|
||||
__RW __u32 DAT_VLD3;
|
||||
__RO __u32 ROM_CRC;
|
||||
__RW __u32 MCFG0_SEL;
|
||||
__RW __u32 MCFG1_SEL;
|
||||
__RW __u32 MCFG0_RF1P;
|
||||
__RW __u32 MCFG0_RF2P;
|
||||
__RW __u32 MCFG0_RM1P;
|
||||
__RW __u32 MCFG0_RM2P;
|
||||
__RW __u32 MCFG0_VROM;
|
||||
__RW __u32 MCFG1_RM1P;
|
||||
__RW __u32 MCFG0_CON[2];
|
||||
__RW __u32 MCFG1_CON[2];
|
||||
} JL_MBIST_TypeDef;
|
||||
|
||||
#define JL_MBIST_BASE (csfr_base + map_adr(0x09, 0x00))
|
||||
#define JL_MBIST ((JL_MBIST_TypeDef *)JL_MBIST_BASE)
|
||||
|
||||
//............. 0x0a00 - 0x0aff............
|
||||
//typedef struct {
|
||||
// __RW __u32 CON;
|
||||
// __RW __u32 CADR;
|
||||
// __RW __u32 ACC0L;
|
||||
// __RW __u32 ACC0H;
|
||||
// __RW __u32 ACC1L;
|
||||
// __RW __u32 ACC1H;
|
||||
// __RW __u32 CONST;
|
||||
// __RW __u32 TEST1;
|
||||
//} JL_FFT_TypeDef;
|
||||
//
|
||||
//#define JL_FFT_BASE (csfr_base + map_adr(0x0a, 0x00))
|
||||
//#define JL_FFT ((JL_FFT_TypeDef *)JL_FFT_BASE)
|
||||
|
||||
//............. 0x0b00 - 0x0bff............
|
||||
//typedef struct {
|
||||
///* 00 */ __RW __u32 CON0;
|
||||
///* 01 */ __RW __u32 LPEN_CON;
|
||||
///* 02 */ __RW __u32 LSEN_CON;
|
||||
///* 03 */ __RO __u32 LS_PND;
|
||||
///* 04 */ __RO __u32 CE_PND;
|
||||
///* 05 */ __RW __u32 LS_PRD_32K;
|
||||
///* 06 */ __RW __u32 CE_PRD_32K;
|
||||
///* 07 */ __RW __u32 LS_PRD_64K;
|
||||
///* 08 */ __RW __u32 CE_PRD_64K;
|
||||
///* 09 */ __RW __u32 LS_PRD_ROM;
|
||||
///* 0a */ __RW __u32 CE_PRD_ROM;
|
||||
//} JL_ATOLP_TypeDef;
|
||||
|
||||
//#define JL_ATOLP_BASE (csfr_base + map_adr(0x0b, 0x00))
|
||||
//#define JL_ATOLP ((JL_ATOLP_TypeDef *)JL_ATOLP_BASE)
|
||||
|
||||
//*********************************************************************************
|
||||
//
|
||||
// q32DSP_sfr
|
||||
//
|
||||
//*********************************************************************************
|
||||
|
||||
//---------------------------------------------//
|
||||
// q32DSP define
|
||||
//---------------------------------------------//
|
||||
|
||||
#define q32DSP_sfr_offset 0x000800
|
||||
#define q32DSP_sfr_base (csfr_base + 0xe000)
|
||||
|
||||
#define q32DSP_cpu_base (q32DSP_sfr_base + 0x0000)
|
||||
#define q32DSP_icu_base (q32DSP_sfr_base + 0x0400)
|
||||
|
||||
#define q32DSP(n) ((JL_TypeDef_q32DSP *)(q32DSP_sfr_base + q32DSP_sfr_offset*n))
|
||||
#define q32DSP_icu(n) ((JL_TypeDef_q32DSP_ICU *)(q32DSP_icu_base + q32DSP_sfr_offset*n))
|
||||
|
||||
//---------------------------------------------//
|
||||
// q32DSP core sfr
|
||||
//---------------------------------------------//
|
||||
|
||||
typedef struct {
|
||||
/* 00 */ __RO __u32 DR00;
|
||||
/* 01 */ __RO __u32 DR01;
|
||||
/* 02 */ __RO __u32 DR02;
|
||||
/* 03 */ __RO __u32 DR03;
|
||||
/* 04 */ __RO __u32 DR04;
|
||||
/* 05 */ __RO __u32 DR05;
|
||||
/* 06 */ __RO __u32 DR06;
|
||||
/* 07 */ __RO __u32 DR07;
|
||||
/* 08 */ __RO __u32 DR08;
|
||||
/* 09 */ __RO __u32 DR09;
|
||||
/* 0a */ __RO __u32 DR10;
|
||||
/* 0b */ __RO __u32 DR11;
|
||||
/* 0c */ __RO __u32 DR12;
|
||||
/* 0d */ __RO __u32 DR13;
|
||||
/* 0e */ __RO __u32 DR14;
|
||||
/* 0f */ __RO __u32 DR15;
|
||||
|
||||
/* 10 */ __RO __u32 RETI;
|
||||
/* 11 */ __RO __u32 RETE;
|
||||
/* 12 */ __RO __u32 RETX;
|
||||
/* 13 */ __RO __u32 RETS;
|
||||
/* 14 */ __RO __u32 SR04;
|
||||
/* 15 */ __RO __u32 PSR;
|
||||
/* 16 */ __RO __u32 CNUM;
|
||||
/* 17 */ __RO __u32 SR07;
|
||||
/* 18 */ __RO __u32 SR08;
|
||||
/* 19 */ __RO __u32 SR09;
|
||||
/* 1a */ __RO __u32 SR10;
|
||||
/* 1b */ __RO __u32 ICFG;
|
||||
/* 1c */ __RO __u32 USP;
|
||||
/* 1d */ __RO __u32 SSP;
|
||||
/* 1e */ __RO __u32 SP;
|
||||
/* 1f */ __RO __u32 PCRS;
|
||||
|
||||
/* 20 */ __RW __u32 BPCON;
|
||||
/* 21 */ __RW __u32 BSP;
|
||||
/* 22 */ __RW __u32 BP0;
|
||||
/* 23 */ __RW __u32 BP1;
|
||||
/* 24 */ __RW __u32 BP2;
|
||||
/* 25 */ __RW __u32 BP3;
|
||||
/* 26 */ __WO __u32 CMD_PAUSE;
|
||||
/* 27 */ __RW __u32 BP4;
|
||||
/* 28 */ __RW __u32 BP5;
|
||||
/* 29 */ __RW __u32 BP6;
|
||||
/* 2a */ __RW __u32 BP7;
|
||||
/* */ __RO __u32 REV2a[0x30 - 0x2a - 1];
|
||||
|
||||
/* 30 */ __RW __u32 PMU_CON0;
|
||||
/* 31 */ __RW __u32 PMU_CON1;
|
||||
/* 32 */ __RO __u32 RST_ADDR;
|
||||
/* */ __RO __u32 REV32[0x3b - 0x32 - 1];
|
||||
/* 3b */ __RW __u8 TTMR_CON;
|
||||
/* 3c */ __RW __u32 TTMR_CNT;
|
||||
/* 3d */ __RW __u32 TTMR_PRD;
|
||||
/* */ __RO __u32 REV3d[0x40 - 0x3d - 1];
|
||||
|
||||
/* 40 */ __RW __u32 ICFG00;
|
||||
/* 41 */ __RW __u32 ICFG01;
|
||||
/* 42 */ __RW __u32 ICFG02;
|
||||
/* 43 */ __RW __u32 ICFG03;
|
||||
/* 44 */ __RW __u32 ICFG04;
|
||||
/* 45 */ __RW __u32 ICFG05;
|
||||
/* 46 */ __RW __u32 ICFG06;
|
||||
/* 47 */ __RW __u32 ICFG07;
|
||||
/* 48 */ __RW __u32 ICFG08;
|
||||
/* 49 */ __RW __u32 ICFG09;
|
||||
/* 4a */ __RW __u32 ICFG10;
|
||||
/* 4b */ __RW __u32 ICFG11;
|
||||
/* 4c */ __RW __u32 ICFG12;
|
||||
/* 4d */ __RW __u32 ICFG13;
|
||||
/* 4e */ __RW __u32 ICFG14;
|
||||
/* 4f */ __RW __u32 ICFG15;
|
||||
|
||||
/* 50 */ __RW __u32 ICFG16;
|
||||
/* 51 */ __RW __u32 ICFG17;
|
||||
/* 52 */ __RW __u32 ICFG18;
|
||||
/* 53 */ __RW __u32 ICFG19;
|
||||
/* 54 */ __RW __u32 ICFG20;
|
||||
/* 55 */ __RW __u32 ICFG21;
|
||||
/* 56 */ __RW __u32 ICFG22;
|
||||
/* 57 */ __RW __u32 ICFG23;
|
||||
/* 58 */ __RW __u32 ICFG24;
|
||||
/* 59 */ __RW __u32 ICFG25;
|
||||
/* 5a */ __RW __u32 ICFG26;
|
||||
/* 5b */ __RW __u32 ICFG27;
|
||||
/* 5c */ __RW __u32 ICFG28;
|
||||
/* 5d */ __RW __u32 ICFG29;
|
||||
/* 5e */ __RW __u32 ICFG30;
|
||||
/* 5f */ __RW __u32 ICFG31;
|
||||
|
||||
/* 60 */ __RO __u32 IPND0;
|
||||
/* 61 */ __RO __u32 IPND1;
|
||||
/* 62 */ __RO __u32 IPND2;
|
||||
/* 63 */ __RO __u32 IPND3;
|
||||
/* 64 */ __RO __u32 IPND4;
|
||||
/* 65 */ __RO __u32 IPND5;
|
||||
/* 66 */ __RO __u32 IPND6;
|
||||
/* 67 */ __RO __u32 IPND7;
|
||||
/* 68 */ __WO __u32 ILAT_SET;
|
||||
/* 69 */ __WO __u32 ILAT_CLR;
|
||||
/* 6a */ __RW __u32 IPMASK;
|
||||
/* 6b */ __RW __u32 GIEMASK;
|
||||
/* 6c */ __RW __u32 IWKUP_NUM;
|
||||
/* */ __RO __u32 REV6c[0x70 - 0x6c - 1];
|
||||
|
||||
/* 70 */ __RW __u32 ETM_CON;
|
||||
/* 71 */ __RO __u32 ETM_PC0;
|
||||
/* 72 */ __RO __u32 ETM_PC1;
|
||||
/* 73 */ __RO __u32 ETM_PC2;
|
||||
/* 74 */ __RO __u32 ETM_PC3;
|
||||
/* 75 */ __RW __u32 WP0_ADRH;
|
||||
/* 76 */ __RW __u32 WP0_ADRL;
|
||||
/* 77 */ __RW __u32 WP0_DATH;
|
||||
/* 78 */ __RW __u32 WP0_DATL;
|
||||
/* 79 */ __RO __u32 WP0_PC;
|
||||
/* 7a */ __RO __u32 WP0_AMSG;
|
||||
/* */ __RO __u32 REV7b[0x80 - 0x7a - 1];
|
||||
|
||||
/* 80 */ __RW __u32 EMU_CON;
|
||||
/* 81 */ __RW __u32 EMU_MSG;
|
||||
/* 82 */ __RW __u32 EMU_SSP_H;
|
||||
/* 83 */ __RW __u32 EMU_SSP_L;
|
||||
/* 84 */ __RW __u32 EMU_USP_H;
|
||||
/* 85 */ __RW __u32 EMU_USP_L;
|
||||
/* 86 */ __RW __u32 LIM_PC0_H;
|
||||
/* 87 */ __RW __u32 LIM_PC0_L;
|
||||
/* 88 */ __RW __u32 LIM_PC1_H;
|
||||
/* 89 */ __RW __u32 LIM_PC1_L;
|
||||
/* 8a */ __RW __u32 LIM_PC2_H;
|
||||
/* 8b */ __RW __u32 LIM_PC2_L;
|
||||
/* */ __RO __u32 REV8b[0x90 - 0x8b - 1];
|
||||
|
||||
/* 90 */ __RW __u32 ESU_CON;
|
||||
/* 91 */ __RO __u32 CNT_CHIT;
|
||||
/* 92 */ __RO __u32 CNT_CMIS;
|
||||
/* 93 */ __RO __u32 CNT_FILL;
|
||||
/* 94 */ __RO __u32 CNT_IHIT;
|
||||
/* 95 */ __RO __u32 CNT_IMIS;
|
||||
/* 96 */ __RO __u32 CNT_RHIT;
|
||||
/* 97 */ __RO __u32 CNT_RMIS;
|
||||
/* 98 */ __RO __u32 CNT_WHIT;
|
||||
/* 99 */ __RO __u32 CNT_WMIS;
|
||||
} JL_TypeDef_q32DSP;
|
||||
|
||||
//---------------------------------------------//
|
||||
// q32DSP icache sfr
|
||||
//---------------------------------------------//
|
||||
|
||||
typedef struct {
|
||||
__RW __u32 CON;
|
||||
__RW __u32 EMU_CON;
|
||||
__RW __u32 EMU_MSG;
|
||||
__RW __u32 EMU_ID;
|
||||
__RW __u32 CMD_CON;
|
||||
__RW __u32 CMD_BEG;
|
||||
__RW __u32 CMD_END;
|
||||
__RW __u32 CNT_RACK;
|
||||
__RW __u32 CNT_RNAK;
|
||||
__RW __u32 MBIST_SEL;
|
||||
__RW __u32 MCFG0_CON[2];
|
||||
} JL_TypeDef_q32DSP_ICU;
|
||||
|
||||
|
||||
//---------------------------------------------//
|
||||
// q32DSP dcache sfr
|
||||
//---------------------------------------------//
|
||||
|
||||
typedef struct {
|
||||
__RW __u32 CON;
|
||||
__RW __u32 EMU_CON;
|
||||
__RW __u32 EMU_MSG;
|
||||
__RW __u32 EMU_ID;
|
||||
__RW __u32 CNT_WACK;
|
||||
__RW __u32 CNT_WNAK;
|
||||
__RW __u32 CNT_RACK;
|
||||
__RW __u32 CNT_RNAK;
|
||||
__RW __u32 CMD_CON[4];
|
||||
__RW __u32 CMD_BEG[4];
|
||||
__RW __u32 CMD_END[4];
|
||||
__RW __u32 MBIST_SEL;
|
||||
__RW __u32 MCFG0_CON[2];
|
||||
__RO __u32 REV1[0x20 - 0x16 - 1];
|
||||
__WO __u32 CMO[32];
|
||||
} JL_TypeDef_q32DSP_DCU;
|
||||
|
||||
|
||||
//*********************************************************************************//
|
||||
|
||||
#define TICK_CON (q32DSP(0)->TTMR_CON)
|
||||
#define TICK_PRD (q32DSP(0)->TTMR_PRD)
|
||||
#define TICK_CNT (q32DSP(0)->TTMR_CNT)
|
||||
|
||||
#define SOFT_CLEAR_PENDING (q32DSP(0)->ILAT_CLR)
|
||||
|
||||
#define CPU_MSG (q32DSP(0)->EMU_MSG)
|
||||
#define CPU_CON (q32DSP(0)->EMU_CON)
|
||||
|
||||
#undef __RW
|
||||
#undef __RO
|
||||
#undef __WO
|
||||
|
||||
#undef __u8
|
||||
#undef __u16
|
||||
#undef __u32
|
||||
|
||||
//*********************************************************************************//
|
||||
// //
|
||||
// end of this module //
|
||||
// //
|
||||
//*********************************************************************************//
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,45 @@
|
||||
#ifndef _CTMU_DRV_H_
|
||||
#define _CTMU_DRV_H_
|
||||
|
||||
#include "typedef.h"
|
||||
|
||||
#define CTMU_KEY_CH_MAX 3
|
||||
|
||||
typedef struct _CTMU_KEY_VAR {
|
||||
s32 touch_release_buf[CTMU_KEY_CH_MAX]; //按键释放值滤波器buffer
|
||||
u16 touch_cnt_buf[CTMU_KEY_CH_MAX]; //按键计数值滤波器buffer
|
||||
s16 FLT1CFG1; //滤波器1配置参数1
|
||||
s16 FLT1CFG2; //滤波器1配置参数2, 等于(-RELEASECFG0)<<FLT1CFG0
|
||||
s16 PRESSCFG; //按下判决门限
|
||||
s16 RELEASECFG0; //释放判决门限0
|
||||
s16 RELEASECFG1; //释放判决门限1
|
||||
s8 FLT0CFG; //滤波器0配置参数(0/1/2/3)
|
||||
s8 FLT1CFG0; //滤波器1配置参数0
|
||||
u16 touch_key_state; //按键状态标志，随时可能被中断改写，按键处理程序需要将此标志复制出来再行处理
|
||||
u8 touch_init_cnt[CTMU_KEY_CH_MAX]; //初始化计数器，非0时进行初始化
|
||||
} sCTMU_KEY_VAR;
|
||||
|
||||
|
||||
struct ctmu_key_port {
|
||||
u8 port; //触摸按键IO
|
||||
u8 key_value; //按键返回值
|
||||
};
|
||||
|
||||
struct ctmu_touch_key_platform_data {
|
||||
u8 num; //触摸按键个数
|
||||
s16 press_cfg; //按下判决门限
|
||||
s16 release_cfg0; //释放判决门限0
|
||||
s16 release_cfg1; //释放判决门限1
|
||||
const struct ctmu_key_port *port_list;
|
||||
};
|
||||
|
||||
/* =========== ctmu API ============= */
|
||||
//ctmu 初始化
|
||||
int ctmu_init(void *_data);
|
||||
|
||||
//获取plcnt按键状态
|
||||
u8 get_ctmu_value(void);
|
||||
|
||||
|
||||
#endif /* #ifndef _CTMU_DRV_H_ */
|
||||
|
||||
@@ -0,0 +1,150 @@
|
||||
#ifndef __Q32DSP_DCACHE__
|
||||
#define __Q32DSP_DCACHE__
|
||||
|
||||
//*********************************************************************************//
|
||||
// Module name : dcache.h //
|
||||
// Description : q32DSP dcache control head file //
|
||||
// By Designer : zequan_liu //
|
||||
// Dat changed : //
|
||||
//*********************************************************************************//
|
||||
|
||||
#define INCLUDE_DCU_RPT 0
|
||||
#define INCLUDE_DCU_EMU 0
|
||||
#define INCLUDE_L1D 0
|
||||
#define INCLUDE_L2D 0
|
||||
|
||||
//------------------------------------------------------//
|
||||
// peripheral level 1 function
|
||||
//------------------------------------------------------//
|
||||
|
||||
#if (INCLUDE_L1D)
|
||||
|
||||
void L1pEnable(void);
|
||||
void L1pDisable(void);
|
||||
void L1pInitial(void);
|
||||
void L1pSetWayNum(unsigned int way);
|
||||
|
||||
void L1pInvalidAll(void);
|
||||
void L1pInvalidRegion(unsigned int *beg, unsigned int len); // note len!=0
|
||||
void L1pFlushAll(void);
|
||||
void L1pFlushRegion(unsigned int *beg, unsigned int len); // note len!=0
|
||||
void L1pFlushinvAll(void);
|
||||
void L1pFlushinvRegion(unsigned int *beg, unsigned int len); // note len!=0
|
||||
void L1pPfetchRegion(unsigned int *beg, unsigned int len); // note len!=0
|
||||
|
||||
void L1pReportEnable(void);
|
||||
void L1pReportDisable(void);
|
||||
void L1pReportClear(void);
|
||||
void L1pReportPrintf(void);
|
||||
|
||||
void L1pEmuEnable(void);
|
||||
void L1pEmuDisable(void);
|
||||
void L1pEmuMessage(void);
|
||||
|
||||
void L1pWrThroughRegion(unsigned int num, unsigned int *beg, unsigned int len);
|
||||
void L1pRwThroughRegion(unsigned int num, unsigned int *beg, unsigned int len);
|
||||
void L1pPrivateRegion(unsigned int num, unsigned int *beg, unsigned int len);
|
||||
|
||||
#else
|
||||
|
||||
#define L1pEnable DcuEnable
|
||||
#define L1pDisable DcuDisable
|
||||
#define L1pInitial DcuInitial
|
||||
#define L1pWaitIdle DcuWaitIdle
|
||||
#define L1pSetWayNum DcuSetWayNum
|
||||
|
||||
#define L1pInvalidAll DcuInvalidAll
|
||||
#define L1pInvalidRegion DcuInvalidRegion
|
||||
#define L1pFlushAll DcuFlushAll
|
||||
#define L1pFlushRegion DcuFlushRegion
|
||||
#define L1pFlushinvAll DcuFlushinvAll
|
||||
#define L1pFlushinvRegion DcuFlushinvRegion
|
||||
#define L1pPfetchRegion DcuPfetchRegion
|
||||
|
||||
#define L1pReportEnable DcuReportEnable
|
||||
#define L1pReportDisable DcuReportDisable
|
||||
#define L1pReportClear DcuReportClear
|
||||
#define L1pReportPrintf DcuReportPrintf
|
||||
|
||||
#define L1pEmuEnable DcuEmuEnable
|
||||
#define L1pEmuDisable DcuEmuDisable
|
||||
#define L1pEmuMessage DcuEmuMessage
|
||||
|
||||
#define L1pWrThroughRegion DcuWrThroughRegion
|
||||
#define L1pRwThroughRegion DcuRwThroughRegion
|
||||
#define L1pPrivateRegion DcuPrivateRegion
|
||||
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------//
|
||||
// dcache level 1 function
|
||||
//------------------------------------------------------//
|
||||
|
||||
void DcuEnable(void);
|
||||
void DcuDisable(void);
|
||||
void DcuInitial(void);
|
||||
void DcuWaitIdle(void);
|
||||
void DcuSetWayNum(unsigned int way);
|
||||
|
||||
void DcuInvalidAll(void);
|
||||
void DcuInvalidRegion(unsigned int *beg, unsigned int len); // note len!=0
|
||||
void DcuFlushAll(void);
|
||||
void DcuFlushRegion(unsigned int *beg, unsigned int len); // note len!=0
|
||||
void DcuFlushinvAll(void);
|
||||
void DcuFlushinvRegion(unsigned int *beg, unsigned int len); // note len!=0
|
||||
void DcuPfetchRegion(unsigned int *beg, unsigned int len); // note len!=0
|
||||
|
||||
void DcuReportEnable(void);
|
||||
void DcuReportDisable(void);
|
||||
void DcuReportClear(void);
|
||||
void DcuReportPrintf(void);
|
||||
|
||||
void DcuEmuEnable(void);
|
||||
void DcuEmuDisable(void);
|
||||
void DcuEmuMessage(void);
|
||||
|
||||
void DcuWrThroughRegion(unsigned int num, unsigned int *beg, unsigned int len);
|
||||
void DcuRwThroughRegion(unsigned int num, unsigned int *beg, unsigned int len);
|
||||
void DcuPrivateRegion(unsigned int num, unsigned int *beg, unsigned int len);
|
||||
|
||||
//------------------------------------------------------//
|
||||
// dcache level 2 function
|
||||
//------------------------------------------------------//
|
||||
|
||||
#if (INCLUDE_L2D)
|
||||
|
||||
void L2dEnable(void);
|
||||
void L2dDisable(void);
|
||||
void L2dInitial(void);
|
||||
void L2dSetWayNum(unsigned int way);
|
||||
|
||||
void L2dInvalidAll(void);
|
||||
void L2dInvalidRegion(unsigned int *beg, unsigned int len); // note len!=0
|
||||
void L2dFlushAll(void);
|
||||
void L2dFlushRegion(unsigned int *beg, unsigned int len); // note len!=0
|
||||
void L2dFlushinvAll(void);
|
||||
void L2dFlushinvRegion(unsigned int *beg, unsigned int len); // note len!=0
|
||||
void L2dPfetchRegion(unsigned int *beg, unsigned int len); // note len!=0
|
||||
|
||||
void L2dReportEnable(void);
|
||||
void L2dReportDisable(void);
|
||||
void L2dReportClear(void);
|
||||
void L2dReportPrintf(void);
|
||||
|
||||
void L2dEmuEnable(void);
|
||||
void L2dEmuDisable(void);
|
||||
void L2dEmuMessage(void);
|
||||
|
||||
void L2dWrThroughRegion(unsigned int num, unsigned int *beg, unsigned int len);
|
||||
void L2dRwThroughRegion(unsigned int num, unsigned int *beg, unsigned int len);
|
||||
void L2dPrivateRegion(unsigned int num, unsigned int *beg, unsigned int len);
|
||||
|
||||
#endif
|
||||
|
||||
//*********************************************************************************//
|
||||
// //
|
||||
// end of this module //
|
||||
// //
|
||||
//*********************************************************************************//
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,91 @@
|
||||
#ifndef __DEBUG_H__
|
||||
#define __DEBUG_H__
|
||||
|
||||
|
||||
typedef enum etm_detect_mode {
|
||||
CPU_SFR_DETECT_MODE = 1,
|
||||
CPU_RD_BUS_DETECT_MODE,
|
||||
CPU_WR_BUS_DETECT_MODE,
|
||||
CPU_RD_WR_BUS_DETECT_MODE,
|
||||
} ETM_DETECT_MODE;
|
||||
|
||||
|
||||
#define CDBG_IDx(n, id) ((1<<(n+4)) | (id<<(n*8+8)))
|
||||
#define CDBG_INV (1<<7)
|
||||
#define CDBG_PEN (1<<3)
|
||||
#define CDBG_XEN (1<<2)
|
||||
#define CDBG_WEN (1<<1)
|
||||
#define CDBG_REN (1<<0)
|
||||
|
||||
void debug_init();
|
||||
void exception_analyze();
|
||||
|
||||
/********************************** DUBUG SFR *****************************************/
|
||||
|
||||
u32 get_dev_id(char *name);
|
||||
|
||||
/* ---------------------------------------------------------------------------- */
|
||||
/**
|
||||
* @brief Memory权限保护设置
|
||||
*
|
||||
* @param idx: 保护框索引, 范围: 0 ~ 3, 目前系统默认使用0和3, 用户可用1和2
|
||||
* @param begin: Memory开始地址
|
||||
* @param end: Memory结束地址
|
||||
* @param inv: 0: 保护框内, 1: 保护框外
|
||||
* @param format: "Cxwr0rw1rw2rw3rw", CPU:外设0:外设1:外设2:外设3,
|
||||
* @param ...: 外设ID号索引, 如: DBG_EQ, 见debug.h
|
||||
*/
|
||||
/* ---------------------------------------------------------------------------- */
|
||||
void mpu_set(int idx, u32 begin, u32 end, u32 inv, const char *format, ...);
|
||||
|
||||
|
||||
/* ---------------------------------------------------------------------------- */
|
||||
/**
|
||||
* @brief 取消指定框的mpu保护
|
||||
*
|
||||
* @param idx: 保护框索引号
|
||||
*/
|
||||
/* ---------------------------------------------------------------------------- */
|
||||
void mpu_disable_by_index(u8 idx);
|
||||
|
||||
|
||||
/* ---------------------------------------------------------------------------- */
|
||||
/**
|
||||
* @brief :取消所有保护框mpu保护
|
||||
*/
|
||||
/* ---------------------------------------------------------------------------- */
|
||||
void mpu_diasble(void);
|
||||
|
||||
|
||||
/* ---------------------------------------------------------------------------- */
|
||||
/**
|
||||
* @brief flash PC范围设置为Flash外区域, 调用该接口后调用flash里的函数将触发异常
|
||||
*/
|
||||
/* ---------------------------------------------------------------------------- */
|
||||
void flash_pc_limit_disable();
|
||||
|
||||
/* ---------------------------------------------------------------------------- */
|
||||
/**
|
||||
* @brief flash PC范围限制恢复为flash代码区域, 调用该接口后可调用flash里的函数
|
||||
*/
|
||||
/* ---------------------------------------------------------------------------- */
|
||||
void flash_pc_limit_enable();
|
||||
|
||||
/* ---------------------------------------------------------------------------- */
|
||||
/**
|
||||
* @brief CPU内存监测点设置
|
||||
*
|
||||
* @param low_addr: 监测区域起始地址
|
||||
* @param high_addr: 监测区域结束地址
|
||||
* @param low_limit_value: 监测内存下限值
|
||||
* @param high_limit_value: 监测内存上限值
|
||||
* @param mode: 监测模式(ETM_DETECT_MODE)
|
||||
* @param limit_range_out: 0(框内触发中断) 1(框外触发中断)
|
||||
* @param trigger_exception: 0(触发普通中断) 1(触发异常中断)
|
||||
*/
|
||||
/* ---------------------------------------------------------------------------- */
|
||||
void cpu_etm_range_value_limit_detect(void *low_addr, void *high_addr, u32 low_limit_value, u32 high_limit_value, int mode, int limit_range_out, int trigger_exception);
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@@ -0,0 +1,45 @@
|
||||
#ifndef __EFUSE_H__
|
||||
#define __EFUSE_H__
|
||||
|
||||
|
||||
u32 get_chip_version();
|
||||
u32 efuse_get_chip_id();
|
||||
u16 get_chip_id();
|
||||
u32 efuse_get_gpadc_vbg_trim();
|
||||
void efuse_init();
|
||||
|
||||
u8 get_en_act();
|
||||
u8 get_vddio_lvd_en();
|
||||
u8 efuse_get_lvd_act();
|
||||
u8 efuse_get_vddio_lvd_lev();
|
||||
u8 efuse_get_vio_act();
|
||||
u8 efuse_get_vddio_lev();
|
||||
u8 efuse_get_mclr_en_dis();
|
||||
u8 efuse_get_xosc_pin_auto();
|
||||
u8 efuse_get_xosc_pin_mode();
|
||||
u8 efuse_get_sfc_fast_boot_dis();
|
||||
u8 efuse_get_pin_reset_en();
|
||||
u8 efuse_get_fast_up();
|
||||
u8 efuse_get_flash_io_select();
|
||||
u8 efuse_get_vbg_act();
|
||||
u8 efuse_get_lvd_bg_trim();
|
||||
u8 efuse_get_mvbg_lev();
|
||||
u8 efuse_get_en_wvbg_lev();
|
||||
|
||||
u8 efuse_get_cp_pass();
|
||||
u8 efuse_get_ft_pass();
|
||||
u8 efuse_get_wvdd_level_trim();
|
||||
u8 efuse_get_vbat_trim_4p2(void);
|
||||
u8 efuse_get_vbat_trim_4p4(void);
|
||||
u8 efuse_get_vbat_trim_4p5(void);
|
||||
u8 efuse_get_charge_cur_trim(void);
|
||||
u8 efuse_get_io_pu_100k(void);
|
||||
u8 efuse_get_flash_type_select(void);//1: NOR 0:NAND
|
||||
|
||||
u8 efuse_get_apa_vb17_vbg();
|
||||
u8 efuse_get_xosc_ldo();
|
||||
u8 efuse_get_xosc_ext_init();
|
||||
u8 efuse_get_lrc24m_caps();
|
||||
u8 efuse_get_lrc24m_rs();
|
||||
|
||||
#endif /*EFUSE_H*/
|
||||
@@ -0,0 +1,29 @@
|
||||
#ifndef __FM_INSIDE_API_H_
|
||||
#define __FM_INSIDE_API_H_
|
||||
#include "typedef.h"
|
||||
|
||||
enum {
|
||||
SET_FM_INSIDE_SCAN_ARG1,
|
||||
SET_FM_INSIDE_SCAN_ARG2,
|
||||
SET_FM_INSIDE_PRINTF,
|
||||
SET_FM_INSIDE_SYS_CLK,
|
||||
};
|
||||
void fm_inside_io_ctrl(int ctrl, ...);
|
||||
|
||||
void fm_inside_default_config(void);
|
||||
void fm_inside_on(void);
|
||||
void fm_inside_off(void);
|
||||
u8 fm_inside_freq_set(u32 freq);
|
||||
void fm_inside_int_set(u8 mute);
|
||||
u16 fm_inside_id_read(void);
|
||||
s32 fm_inside_rssi_read(void); //unit DB
|
||||
void fm_inside_scan_info_printf(u16 freq_start, u16 freq_end);
|
||||
//more inside fm api function, see file fm_inside_api.h
|
||||
|
||||
//Following function Call is valid Only after fm_inside_on();
|
||||
void fm_inside_set_stereo(u8 set); //set[0,127], 0 mono, 127 stereo.
|
||||
void fm_inside_set_abw(u8 set); //audio bandwidth set //set[0,127] <=>2k~16k
|
||||
void fm_inside_deempasis_set(u8 set);// set[0/1], 0:50us, 1:75us
|
||||
void set_fm_pcm_out_fun(void *fun);
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,156 @@
|
||||
#ifndef __GPADC_HW_H__
|
||||
#define __GPADC_HW_H__
|
||||
//br35专用
|
||||
#include "generic/typedef.h"
|
||||
#include "asm/efuse.h"
|
||||
#include "gpio.h"
|
||||
#include "jiffies.h"
|
||||
#include "clock.h"
|
||||
|
||||
#define ADC_CH_MASK_TYPE_SEL 0xffff0000
|
||||
#define ADC_CH_MASK_CH_SEL 0x0000ffff
|
||||
|
||||
#define ADC_CH_TYPE_BT (0x0<<16)
|
||||
#define ADC_CH_TYPE_AUDIO (0x1<<16)
|
||||
#define ADC_CH_TYPE_PMU (0x2<<16)
|
||||
#define ADC_CH_TYPE_LRC200K (0x3<<16)
|
||||
#define ADC_CH_TYPE_LRC24M (0x4<<16)
|
||||
#define ADC_CH_TYPE_SYSPLL (0x5<<16)
|
||||
#define ADC_CH_TYPE_LPCTM (0x6<<16)
|
||||
#define ADC_CH_TYPE_CALSSD (0x7<<16)
|
||||
#define ADC_CH_TYPE_WAT (0x8<<16)
|
||||
#define ADC_CH_TYPE_IO (0x10<<16)
|
||||
#define ADC_CH_TYPE_DIFF (0x11<<16)
|
||||
|
||||
#define ADC_CH_BT_ (ADC_CH_TYPE_BT | 0x0)
|
||||
#define ADC_CH_AUDIO_ (ADC_CH_TYPE_AUDIO | 0x0)
|
||||
|
||||
#define ADC_CH_PMU_VBG (ADC_CH_TYPE_PMU | 0x0)//MVBG/WVBG
|
||||
#define ADC_CH_PMU_VSW (ADC_CH_TYPE_PMU | 0x1)
|
||||
#define ADC_CH_PMU_PROGI (ADC_CH_TYPE_PMU | 0x2)
|
||||
#define ADC_CH_PMU_OCP_OUT (ADC_CH_TYPE_PMU | 0x3)
|
||||
#define ADC_CH_PMU_VTEMP (ADC_CH_TYPE_PMU | 0x4)
|
||||
#define ADC_CH_PMU_VPWR_4 (ADC_CH_TYPE_PMU | 0x5) //1/4vpwr
|
||||
#define ADC_CH_PMU_VBAT_4 (ADC_CH_TYPE_PMU | 0x6) //1/4vbat
|
||||
#define ADC_CH_PMU_VBAT_2 (ADC_CH_TYPE_PMU | 0x7)
|
||||
#define ADC_CH_PMU_VP17_DCDC (ADC_CH_TYPE_PMU | 0x8)
|
||||
#define ADC_CH_PMU_PVDD (ADC_CH_TYPE_PMU | 0x9)
|
||||
#define ADC_CH_PMU_DCVDD (ADC_CH_TYPE_PMU | 0xa)
|
||||
#define ADC_CH_PMU_DVDD (ADC_CH_TYPE_PMU | 0xb)
|
||||
#define ADC_CH_PMU_WVDD (ADC_CH_TYPE_PMU | 0xc)
|
||||
#define ADC_CH_PMU_PADC0 (ADC_CH_TYPE_PMU | 0xd)
|
||||
#define ADC_CH_PMU_PVD_PORB_11V (ADC_CH_TYPE_PMU | 0xe)
|
||||
#define ADC_CH_PMU_VIN_4 (ADC_CH_TYPE_PMU | 0xf) //1/4VIN
|
||||
|
||||
#define ADC_CH_LRC200K_ (ADC_CH_TYPE_LRC200K | 0x0)
|
||||
#define ADC_CH_LRC24M_ (ADC_CH_TYPE_LRC24M | 0x0)
|
||||
#define ADC_CH_SYSPLL_ (ADC_CH_TYPE_SYSPLL | 0x0)
|
||||
#define ADC_CH_LPCTM_ (ADC_CH_TYPE_LPCTM | 0x0)
|
||||
#define ADC_CH_CALSSD_ (ADC_CH_TYPE_CALSSD | 0x0)
|
||||
#define ADC_CH_WAT_ (ADC_CH_TYPE_WAT | 0x0)
|
||||
|
||||
#define ADC_CH_IO_PA0 (ADC_CH_TYPE_IO | 0x0)
|
||||
#define ADC_CH_IO_PA1 (ADC_CH_TYPE_IO | 0x1)
|
||||
#define ADC_CH_IO_PA5 (ADC_CH_TYPE_IO | 0x2)
|
||||
#define ADC_CH_IO_PA6 (ADC_CH_TYPE_IO | 0x3)
|
||||
#define ADC_CH_IO_PA10 (ADC_CH_TYPE_IO | 0x4)
|
||||
#define ADC_CH_IO_PA11 (ADC_CH_TYPE_IO | 0x5)
|
||||
#define ADC_CH_IO_PA13 (ADC_CH_TYPE_IO | 0x6)
|
||||
#define ADC_CH_IO_PB0 (ADC_CH_TYPE_IO | 0x7)
|
||||
#define ADC_CH_IO_PB1 (ADC_CH_TYPE_IO | 0x8)
|
||||
#define ADC_CH_IO_PC2 (ADC_CH_TYPE_IO | 0x9)
|
||||
#define ADC_CH_IO_PC3 (ADC_CH_TYPE_IO | 0xa)
|
||||
#define ADC_CH_IO_PC10 (ADC_CH_TYPE_IO | 0xb)
|
||||
#define ADC_CH_IO_PC11 (ADC_CH_TYPE_IO | 0xc)
|
||||
#define ADC_CH_IO_DP (ADC_CH_TYPE_IO | 0xd)
|
||||
#define ADC_CH_IO_DM (ADC_CH_TYPE_IO | 0xe)
|
||||
#define ADC_CH_IO_FSPG (ADC_CH_TYPE_IO | 0xf)
|
||||
|
||||
#define ADC_CH_DIFF_ (ADC_CH_TYPE_DIFF | 0x0)
|
||||
|
||||
enum AD_CH {
|
||||
AD_CH_BT = ADC_CH_BT_,
|
||||
|
||||
AD_CH_AUDIO = ADC_CH_AUDIO_,
|
||||
|
||||
AD_CH_PMU_VBG = ADC_CH_PMU_VBG, //MVBG/WVBG
|
||||
AD_CH_PMU_VSW,
|
||||
AD_CH_PMU_PROGI,
|
||||
AD_CH_PMU_OCP_OUT,
|
||||
AD_CH_PMU_VTEMP,
|
||||
AD_CH_PMU_VPWR_4, //1/4vpwr
|
||||
AD_CH_PMU_VBAT_4, //1/4vbat
|
||||
AD_CH_PMU_VBAT_2,
|
||||
AD_CH_PMU_VP17_DCDC,
|
||||
AD_CH_PMU_PVDD,
|
||||
AD_CH_PMU_DCVDD,
|
||||
AD_CH_PMU_DVDD,
|
||||
AD_CH_PMU_WVDD,
|
||||
AD_CH_PMU_PADC0,
|
||||
AD_CH_PMU_PVD_PORB_11V,
|
||||
AD_CH_PMU_VIN_4, //1/4VIN
|
||||
|
||||
AD_CH_LRC200K = ADC_CH_LRC200K_,
|
||||
|
||||
AD_CH_LRC24M = ADC_CH_LRC24M_,
|
||||
|
||||
AD_CH_SYSPLL = ADC_CH_SYSPLL_,
|
||||
|
||||
AD_CH_LPCTM = ADC_CH_LPCTM_,
|
||||
|
||||
AD_CH_CALSSD_ = ADC_CH_CALSSD_,
|
||||
|
||||
AD_CH_WAT = ADC_CH_WAT_,
|
||||
|
||||
AD_CH_IO_PA0 = ADC_CH_IO_PA0,
|
||||
AD_CH_IO_PA1,
|
||||
AD_CH_IO_PA5,
|
||||
AD_CH_IO_PA6,
|
||||
AD_CH_IO_PA10,
|
||||
AD_CH_IO_PA11,
|
||||
AD_CH_IO_PA13,
|
||||
AD_CH_IO_PB0,
|
||||
AD_CH_IO_PB1,
|
||||
AD_CH_IO_PC2,
|
||||
AD_CH_IO_PC3,
|
||||
AD_CH_IO_PC10,
|
||||
AD_CH_IO_PC11,
|
||||
AD_CH_IO_DP,
|
||||
AD_CH_IO_DM,
|
||||
AD_CH_IO_FSPG,
|
||||
|
||||
AD_CH_DIFF = ADC_CH_DIFF_,
|
||||
|
||||
AD_CH_IOVDD = 0xffffffff,
|
||||
};
|
||||
|
||||
#define AD_CH_IO_CH0 IO_PORTA_00
|
||||
#define AD_CH_IO_CH1 IO_PORTA_01
|
||||
#define AD_CH_IO_CH2 IO_PORTA_05
|
||||
#define AD_CH_IO_CH3 IO_PORTA_06
|
||||
#define AD_CH_IO_CH4 IO_PORTA_10
|
||||
#define AD_CH_IO_CH5 IO_PORTA_11
|
||||
#define AD_CH_IO_CH6 IO_PORTA_13
|
||||
#define AD_CH_IO_CH7 IO_PORTB_00
|
||||
#define AD_CH_IO_CH8 IO_PORTB_01
|
||||
#define AD_CH_IO_CH9 IO_PORTC_02
|
||||
#define AD_CH_IO_CH10 IO_PORTC_03
|
||||
#define AD_CH_IO_CH11 IO_PORTC_10
|
||||
#define AD_CH_IO_CH12 IO_PORTC_11
|
||||
#define AD_CH_IO_CH13 IO_PORT_DP
|
||||
#define AD_CH_IO_CH14 IO_PORT_DM
|
||||
#define AD_CH_IO_CH15 0xff//IO_PORT_FSPG
|
||||
|
||||
#define ADC_VBG_CENTER 800
|
||||
#define ADC_VBG_TRIM_STEP 3
|
||||
#define ADC_VBG_DATA_WIDTH 4
|
||||
|
||||
//防编译报错
|
||||
#define AD_CH_LDOREF AD_CH_PMU_VBG
|
||||
#define AD_CH_PMU_VBAT AD_CH_PMU_VBAT_4
|
||||
#define AD_CH_LPCTMU AD_CH_LPCTM
|
||||
|
||||
#define AD_CH_IO_PB7 AD_CH_PMU_PADC0 //仅br35使用
|
||||
|
||||
#endif /*GPADC_HW_H*/
|
||||
|
||||
@@ -0,0 +1,170 @@
|
||||
#ifndef _GPIO_H
|
||||
#define _GPIO_H
|
||||
|
||||
#define IO_PORT_SPILT(io) ((u32)(io)) / 16, BIT(((u32)(io)) %16)
|
||||
|
||||
|
||||
// PORT引脚输入输出模式
|
||||
enum gpio_mode {
|
||||
PORT_OUTPUT_LOW = 0,
|
||||
PORT_OUTPUT_HIGH = 1,
|
||||
PORT_HIGHZ = 2, //高阻模式
|
||||
|
||||
PORT_INPUT_FLOATING = 0x10, //浮空输入
|
||||
PORT_INPUT_PULLUP_10K = 0x11,
|
||||
PORT_INPUT_PULLUP_100K,
|
||||
PORT_INPUT_PULLUP_1M,
|
||||
|
||||
PORT_INPUT_PULLDOWN_10K = 0x21,
|
||||
PORT_INPUT_PULLDOWN_100K,
|
||||
PORT_INPUT_PULLDOWN_1M,
|
||||
|
||||
PORT_KEEP_STATE = 0x30,
|
||||
};
|
||||
|
||||
enum gpio_drive_strength {
|
||||
PORT_DRIVE_STRENGT_2p4mA, ///< 最大驱动电流 2.4mA
|
||||
PORT_DRIVE_STRENGT_8p0mA, ///< 最大驱动电流 8.0mA
|
||||
PORT_DRIVE_STRENGT_24p0mA, ///< 最大驱动电流 24.0mA
|
||||
PORT_DRIVE_STRENGT_64p0mA, ///< 最大驱动电流 64.0mA
|
||||
};
|
||||
|
||||
enum gpio_pullup_mode {
|
||||
GPIO_PULLUP_DISABLE,
|
||||
GPIO_PULLUP_10K,
|
||||
GPIO_PULLUP_100K,
|
||||
GPIO_PULLUP_1M,
|
||||
};
|
||||
enum gpio_pulldown_mode {
|
||||
GPIO_PULLDOWN_DISABLE,
|
||||
GPIO_PULLDOWN_10K,
|
||||
GPIO_PULLDOWN_100K,
|
||||
GPIO_PULLDOWN_1M,
|
||||
};
|
||||
|
||||
|
||||
#define PORT_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
|
||||
#define PORT_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
|
||||
#define PORT_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
|
||||
#define PORT_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
|
||||
#define PORT_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
|
||||
#define PORT_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
|
||||
#define PORT_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
|
||||
#define PORT_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
|
||||
#define PORT_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
|
||||
#define PORT_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
|
||||
#define PORT_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
|
||||
#define PORT_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
|
||||
#define PORT_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
|
||||
#define PORT_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
|
||||
#define PORT_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
|
||||
#define PORT_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
|
||||
#define PORT_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
|
||||
|
||||
#define PORT_PIN_MASK (0x0000FFFFu) /* PIN mask for assert test */
|
||||
|
||||
#include "asm/gpio_hw.h"
|
||||
|
||||
struct gpio_config {
|
||||
u32 pin;
|
||||
enum gpio_mode mode;
|
||||
enum gpio_drive_strength hd;
|
||||
};
|
||||
//配置同组多个io模式及强驱. 形参详见枚举; pin:PORT_PIN_0 or PORT_PIN_0 | PORT_PIN_2等
|
||||
int gpio_init(enum gpio_port port, const struct gpio_config *config);
|
||||
//恢复同组多个io为高阻态. 形参详见枚举; pin:PORT_PIN_0 or PORT_PIN_0 | PORT_PIN_2等
|
||||
int gpio_deinit(enum gpio_port port, u32 pin);
|
||||
//配置同组多个io模式. 形参详见枚举; pin:PORT_PIN_0 or PORT_PIN_0 | PORT_PIN_2等
|
||||
//return:<0:error
|
||||
int gpio_set_mode(enum gpio_port port, u32 pin, enum gpio_mode mode);
|
||||
int gpio_keep_mode_at_sleep(enum gpio_port port, u32 pin);
|
||||
enum gpio_mode gpio_get_mode(enum gpio_port port, u32 pin);
|
||||
|
||||
// 读取单个io输入值. gpio:IO_PORTA_00
|
||||
int gpio_read(u32 gpio);
|
||||
//读取同组多个io值. 形参详见枚举; pin:PORT_PIN_0 or PORT_PIN_0 | PORT_PIN_2等
|
||||
int gpio_read_port(enum gpio_port port, u32 pin);
|
||||
|
||||
// 设置单个io输出电平(需先配置为输出). gpio:IO_PORTA_00; value:0:out 0, 1:out 1
|
||||
int gpio_write(u32 gpio, u32 value);
|
||||
// 设置同组多个io输出电平(需先配置为输出).
|
||||
// pin:PORT_PIN_0 or PORT_PIN_0 | PORT_PIN_2等
|
||||
// out_state:0:out 0, 1:out 1
|
||||
int gpio_write_port(enum gpio_port port, u32 pin, int out_state);
|
||||
|
||||
//翻转同组多个io输出电平(需先配置为输出). pin:PORT_PIN_0 or PORT_PIN_0 | PORT_PIN_2等
|
||||
//return:<0:error
|
||||
int gpio_toggle_port(enum gpio_port port, u32 pin);
|
||||
|
||||
// 获取同组多个io输出电平
|
||||
int gpio_get_out_level(enum gpio_port port, u32 pin);
|
||||
|
||||
// 设置同组多个io强驱
|
||||
int gpio_set_drive_strength(enum gpio_port port, u32 pin, enum gpio_drive_strength drive);
|
||||
|
||||
// 获取单个io输出强度 pin:只能带入1个io
|
||||
enum gpio_drive_strength gpio_get_drive_strength(enum gpio_port port, u32 pin);
|
||||
|
||||
//打印芯片全部gpio寄存器,crossbar信息
|
||||
void gpio_dump();
|
||||
//打印芯片指定io寄存器,crossbar信息
|
||||
void gpio_appoint_dump(enum gpio_port port, u32 pin);
|
||||
|
||||
|
||||
// ----------------------------------------
|
||||
// PORT中断
|
||||
enum gpio_irq_edge {
|
||||
PORT_IRQ_DISABLE = 0, ///< Disable PORT interrupt
|
||||
PORT_IRQ_EDGE_RISE = 1, ///< PORT interrupt type : rising edge
|
||||
PORT_IRQ_EDGE_FALL = 2, ///< PORT interrupt type : falling edge
|
||||
PORT_IRQ_ANYEDGE = 3, ///< PORT interrupt type : both rising and falling edge
|
||||
};
|
||||
typedef void (*gpio_irq_callback_p)(enum gpio_port port, u32 pin, enum gpio_irq_edge edge);
|
||||
struct gpio_irq_config_st {
|
||||
u32 pin;
|
||||
enum gpio_irq_edge irq_edge;
|
||||
gpio_irq_callback_p callback;
|
||||
u8 irq_priority;//中断优先级
|
||||
};
|
||||
//配置中断(已使能)
|
||||
//禁止同一个io同一边沿多次注册
|
||||
//单边沿与双边沿切换: 请先注销(PORT_IRQ_DISABLE)再注册
|
||||
int gpio_irq_config(enum gpio_port port, const struct gpio_irq_config_st *config);//pa,pb,pc,pp0,usb
|
||||
//修改中断回调函数
|
||||
int gpio_irq_set_callback(enum gpio_port port, u32 pin, gpio_irq_callback_p callback);
|
||||
//快速切换使能同组多个io中断响应
|
||||
int gpio_irq_enable(enum gpio_port port, u32 pin);
|
||||
//快速切换暂停同组多个io中断响应
|
||||
int gpio_irq_disable(enum gpio_port port, u32 pin);
|
||||
|
||||
//只有注册单边沿触发才能调用该函数切换边沿
|
||||
//单边沿与双边沿切换: 请先注销再注册
|
||||
int gpio_irq_set_edge(enum gpio_port port, u32 pin, enum gpio_irq_edge irq_edge);
|
||||
// 获取单个io触发边沿 pin:只能带入1个io
|
||||
enum gpio_irq_edge gpio_irq_get_edge(enum gpio_port port, u32 pin);
|
||||
|
||||
|
||||
|
||||
|
||||
// ----------------------------------------
|
||||
// PORT 功能配置
|
||||
// 配置单个io为特殊功能. pin:只能带入1个io
|
||||
//return:<0:error
|
||||
int gpio_set_function(enum gpio_port port, u32 pin, enum gpio_function fn);
|
||||
// 注销单个io的特殊功能. pin:只能带入1个io
|
||||
//return:<0:error
|
||||
int gpio_disable_function(enum gpio_port port, u32 pin, enum gpio_function fn);
|
||||
/* 示例：
|
||||
gpio_set_function(PORTA, PORT_PIN_0, PORT_FUNC_UART0_TX);
|
||||
gpio_set_function(PORTA, PORT_PIN_1, PORT_FUNC_UART0_RX);
|
||||
gpio_set_function(PORTA, PORT_PIN_2, PORT_FUNC_UART0_CTS);
|
||||
gpio_set_function(PORTA, PORT_PIN_3, PORT_FUNC_UART0_RTS);
|
||||
*/
|
||||
|
||||
// io复用时，io资源申请
|
||||
int gpio_request_function(enum gpio_port port, u32 pin, enum gpio_function fn, u32 timeout);
|
||||
// io复用时，io资源释放
|
||||
int gpio_release_function(enum gpio_port port, u32 pin, enum gpio_function fn);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,589 @@
|
||||
#ifndef __GPIO_HW_H__
|
||||
#define __GPIO_HW_H__
|
||||
|
||||
#include "typedef.h"
|
||||
#include "asm/power_interface.h"
|
||||
|
||||
|
||||
#define IO_GROUP_NUM 16
|
||||
#define IO_PORTA_00 (IO_GROUP_NUM * 0 + 0)
|
||||
#define IO_PORTA_01 (IO_GROUP_NUM * 0 + 1)
|
||||
#define IO_PORTA_02 (IO_GROUP_NUM * 0 + 2)
|
||||
#define IO_PORTA_03 (IO_GROUP_NUM * 0 + 3)
|
||||
#define IO_PORTA_04 (IO_GROUP_NUM * 0 + 4)
|
||||
#define IO_PORTA_05 (IO_GROUP_NUM * 0 + 5)
|
||||
#define IO_PORTA_06 (IO_GROUP_NUM * 0 + 6)
|
||||
#define IO_PORTA_07 (IO_GROUP_NUM * 0 + 7)
|
||||
#define IO_PORTA_08 (IO_GROUP_NUM * 0 + 8)
|
||||
#define IO_PORTA_09 (IO_GROUP_NUM * 0 + 9)
|
||||
#define IO_PORTA_10 (IO_GROUP_NUM * 0 + 10)
|
||||
#define IO_PORTA_11 (IO_GROUP_NUM * 0 + 11)
|
||||
#define IO_PORTA_12 (IO_GROUP_NUM * 0 + 12)
|
||||
#define IO_PORTA_13 (IO_GROUP_NUM * 0 + 13)
|
||||
#define IO_PORT_PA_MASK 0x3fff
|
||||
|
||||
#define IO_PORTB_00 (IO_GROUP_NUM * 1 + 0)
|
||||
#define IO_PORTB_01 (IO_GROUP_NUM * 1 + 1)
|
||||
#define IO_PORTB_02 (IO_GROUP_NUM * 1 + 2)
|
||||
#define IO_PORTB_03 (IO_GROUP_NUM * 1 + 3)
|
||||
#define IO_PORTB_04 (IO_GROUP_NUM * 1 + 4)
|
||||
#define IO_PORTB_05 (IO_GROUP_NUM * 1 + 5)
|
||||
#define IO_PORTB_06 (IO_GROUP_NUM * 1 + 6)
|
||||
#define IO_PORTB_07 (IO_GROUP_NUM * 1 + 7)
|
||||
#define IO_PORTB_08 (IO_GROUP_NUM * 1 + 8)
|
||||
#define IO_PORT_PB_MASK 0x01ff
|
||||
|
||||
#define IO_PORTC_00 (IO_GROUP_NUM * 2 + 0)
|
||||
#define IO_PORTC_01 (IO_GROUP_NUM * 2 + 1)
|
||||
#define IO_PORTC_02 (IO_GROUP_NUM * 2 + 2)
|
||||
#define IO_PORTC_03 (IO_GROUP_NUM * 2 + 3)
|
||||
#define IO_PORTC_04 (IO_GROUP_NUM * 2 + 4)
|
||||
#define IO_PORTC_05 (IO_GROUP_NUM * 2 + 5)
|
||||
#define IO_PORTC_06 (IO_GROUP_NUM * 2 + 6)
|
||||
#define IO_PORTC_07 (IO_GROUP_NUM * 2 + 7)
|
||||
#define IO_PORTC_08 (IO_GROUP_NUM * 2 + 8)
|
||||
#define IO_PORTC_09 (IO_GROUP_NUM * 2 + 9)
|
||||
#define IO_PORTC_10 (IO_GROUP_NUM * 2 + 10)
|
||||
#define IO_PORTC_11 (IO_GROUP_NUM * 2 + 11)
|
||||
#define IO_PORT_PC_MASK 0x0fff
|
||||
|
||||
#define IO_PORTD_00 (IO_GROUP_NUM * 3 + 0)
|
||||
#define IO_PORTD_01 (IO_GROUP_NUM * 3 + 1)
|
||||
#define IO_PORTD_02 (IO_GROUP_NUM * 3 + 2)
|
||||
#define IO_PORTD_03 (IO_GROUP_NUM * 3 + 3)
|
||||
// #define IO_PORTD_04 (IO_GROUP_NUM * 3 + 4)
|
||||
// #define IO_PORTD_05 (IO_GROUP_NUM * 3 + 5)
|
||||
// #define IO_PORTD_06 (IO_GROUP_NUM * 3 + 6)
|
||||
// #define IO_PORTD_07 (IO_GROUP_NUM * 3 + 7)
|
||||
// #define IO_PORTD_08 (IO_GROUP_NUM * 3 + 8)
|
||||
#define IO_PORTD_09 (IO_GROUP_NUM * 3 + 9)
|
||||
#define IO_PORT_PD_MASK 0x0000
|
||||
|
||||
#define IO_PORTF_00 (IO_GROUP_NUM * 5 + 0)
|
||||
#define IO_PORTF_01 (IO_GROUP_NUM * 5 + 1)
|
||||
#define IO_PORTF_02 (IO_GROUP_NUM * 5 + 2)
|
||||
#define IO_PORTF_03 (IO_GROUP_NUM * 5 + 3)
|
||||
#define IO_PORTF_04 (IO_GROUP_NUM * 5 + 4)
|
||||
#define IO_PORTF_05 (IO_GROUP_NUM * 5 + 5)
|
||||
#define IO_PORT_PF_MASK 0x003f
|
||||
|
||||
#define IO_PORTP_00 (IO_GROUP_NUM * 13 + 0)
|
||||
#define IO_PORT_PP_MASK 0x0001
|
||||
|
||||
#define IO_PORT_LDOIN IO_PORTP_00
|
||||
|
||||
#define IO_MAX_NUM (IO_PORTP_00 + 1)
|
||||
|
||||
#define IO_PORT_DP (IO_GROUP_NUM * 14 + 0)
|
||||
#define IO_PORT_DM (IO_GROUP_NUM * 14 + 1)
|
||||
#define IO_PORT_USB_MASK 0x03
|
||||
#define IS_PORT_USB(x) (x <= IO_PORT_DM)//无usb赋0
|
||||
|
||||
//br35无pr
|
||||
// #define IO_PORT_PR_00 (IO_GROUP_NUM * 15 + 0)//pr固定15
|
||||
// #define IO_PORT_PR_01 (IO_GROUP_NUM * 15 + 1)
|
||||
// #define IO_PORT_PR_MASK 0x03
|
||||
|
||||
#define IO_PORT_MAX (IO_PORT_DM + 1)
|
||||
|
||||
#define P33_IO_OFFSET 0
|
||||
#define IO_CHGFL_DET (IO_PORT_MAX + P33_IO_OFFSET + 0)
|
||||
#define IO_VBGOK_DET (IO_PORT_MAX + P33_IO_OFFSET + 1)
|
||||
#define IO_VBTCH_DET (IO_PORT_MAX + P33_IO_OFFSET + 2)
|
||||
#define IO_LDOIN_DET (IO_PORT_MAX + P33_IO_OFFSET + 3)
|
||||
#define IO_VBATDT_DET (IO_PORT_MAX + P33_IO_OFFSET + 4)
|
||||
|
||||
#define PG_IO_OFFSET 5
|
||||
#define IO_LCD_PG (IO_PORT_MAX + PG_IO_OFFSET + 0)
|
||||
#define IO_MT_PG (IO_PORT_MAX + PG_IO_OFFSET + 1)
|
||||
|
||||
|
||||
|
||||
#define GPIOA (IO_GROUP_NUM * 0)
|
||||
#define GPIOB (IO_GROUP_NUM * 1)
|
||||
#define GPIOC (IO_GROUP_NUM * 2)
|
||||
// #define GPIOD (IO_GROUP_NUM * 3)//br35无PDx_OUT/IN
|
||||
// #define GPIOE (IO_GROUP_NUM * 4)//无
|
||||
#define GPIOF (IO_GROUP_NUM * 5)
|
||||
#define GPIOP (IO_GROUP_NUM * 13)
|
||||
#define GPIOUSB (IO_GROUP_NUM * 14)
|
||||
// #define GPIOR (IO_GROUP_NUM * 15) //br35 no pr
|
||||
#define GPIOP33 (IO_PORT_MAX + P33_IO_OFFSET)
|
||||
|
||||
enum gpio_port {
|
||||
PORTA = 0,
|
||||
PORTB = 1,
|
||||
PORTC = 2,
|
||||
PORTF = 5,
|
||||
PORTP = 13,
|
||||
PORTUSB = 14,
|
||||
// PORTR = 15, //br35 无pr
|
||||
};
|
||||
#define IS_PORT_ALL_PERIPH(PORT) (((PORT) == PORTA) || \
|
||||
((PORT) == PORTB) || \
|
||||
((PORT) == PORTC) || \
|
||||
((PORT) == PORTF) || \
|
||||
((PORT) == PORTP) || \
|
||||
((PORT) == PORTUSB))
|
||||
|
||||
enum port_op_mode {
|
||||
PORT_SET = 1,
|
||||
PORT_AND,
|
||||
PORT_OR,
|
||||
PORT_XOR,
|
||||
};
|
||||
|
||||
struct port_reg {
|
||||
volatile unsigned int in;
|
||||
volatile unsigned int out;
|
||||
volatile unsigned int dir;
|
||||
volatile unsigned int die;
|
||||
volatile unsigned int dieh;
|
||||
volatile unsigned int pu0;
|
||||
volatile unsigned int pu1;
|
||||
volatile unsigned int pd0;
|
||||
volatile unsigned int pd1;
|
||||
volatile unsigned int hd0;
|
||||
volatile unsigned int hd1;
|
||||
volatile unsigned int spl;
|
||||
volatile unsigned int con;
|
||||
volatile unsigned int out_bsr;
|
||||
volatile unsigned int dir_bsr;
|
||||
volatile unsigned int die_bsr;
|
||||
volatile unsigned int dieh_bsr;
|
||||
volatile unsigned int pu0_bsr;
|
||||
volatile unsigned int pu1_bsr;
|
||||
volatile unsigned int pd0_bsr;
|
||||
volatile unsigned int pd1_bsr;
|
||||
volatile unsigned int hd0_bsr;
|
||||
volatile unsigned int hd1_bsr;
|
||||
volatile unsigned int spl_bsr;
|
||||
volatile unsigned int con_bsr;
|
||||
};
|
||||
#define GPIO_PX_PU_REG_NUM 2
|
||||
#define GPIO_PX_PD_REG_NUM 2
|
||||
#define GPIO_PX_HD_REG_NUM 2
|
||||
#define GPIO_PX_DIEH_REG_NUM 1
|
||||
#define GPIO_PX_SPL_REG_NUM 1
|
||||
#define GPIO_PX_BSR_REG_NUM 1
|
||||
#define usb_reg port_reg
|
||||
#define GPIO_USB_PU_REG_NUM 1
|
||||
#define GPIO_USB_PD_REG_NUM 1
|
||||
#define GPIO_USB_HD_REG_NUM 0
|
||||
#define GPIO_USB_DIEH_REG_NUM 1
|
||||
#define GPIO_USB_SPL_REG_NUM 1
|
||||
#define GPIO_USB_BSR_REG_NUM 1
|
||||
//无PR
|
||||
// struct port_pr_reg {
|
||||
// volatile unsigned int in;
|
||||
// volatile unsigned int out;
|
||||
// volatile unsigned int dir;
|
||||
// volatile unsigned int die;
|
||||
// volatile unsigned int pu0;
|
||||
// // volatile unsigned int pu1;
|
||||
// volatile unsigned int pd0;
|
||||
// // volatile unsigned int pd1;
|
||||
// volatile unsigned int hd0;
|
||||
// // volatile unsigned int hd1;
|
||||
// };
|
||||
// #define GPIO_PR_PU_REG_NUM 0
|
||||
// #define GPIO_PR_PD_REG_NUM 0
|
||||
// #define GPIO_PR_HD_REG_NUM 0
|
||||
// #define GPIO_PR_DIEH_REG_NUM 0
|
||||
// #define GPIO_PR_SPL_REG_NUM 0
|
||||
|
||||
#define GPIO_PU_REG_NUM 2 //max_num
|
||||
#define GPIO_PD_REG_NUM 2 //max_num
|
||||
#define GPIO_HD_REG_NUM 2 //max_num
|
||||
|
||||
|
||||
//===================================================//
|
||||
// BR35 Crossbar API
|
||||
//===================================================//
|
||||
enum PFI_TABLE {
|
||||
PFI_GP_ICH0 = ((u32)(&(JL_IMAP->FI_GP_ICH0))),
|
||||
PFI_GP_ICH1 = ((u32)(&(JL_IMAP->FI_GP_ICH1))),
|
||||
PFI_GP_ICH2 = ((u32)(&(JL_IMAP->FI_GP_ICH2))),
|
||||
PFI_GP_ICH3 = ((u32)(&(JL_IMAP->FI_GP_ICH3))),
|
||||
PFI_GP_ICH4 = ((u32)(&(JL_IMAP->FI_GP_ICH4))),
|
||||
PFI_GP_ICH5 = ((u32)(&(JL_IMAP->FI_GP_ICH5))),
|
||||
|
||||
// PFI_SPI0_CLK = ((u32)(&(JL_IMAP->FI_SPI0_CLK))),
|
||||
// PFI_SPI0_DA0 = ((u32)(&(JL_IMAP->FI_SPI0_DA0))),
|
||||
// PFI_SPI0_DA1 = ((u32)(&(JL_IMAP->FI_SPI0_DA1))),
|
||||
// PFI_SPI0_DA2 = ((u32)(&(JL_IMAP->FI_SPI0_DA2))),
|
||||
// PFI_SPI0_DA3 = ((u32)(&(JL_IMAP->FI_SPI0_DA3))),
|
||||
PFI_SPI1_CLK = ((u32)(&(JL_IMAP->FI_SPI1_CLK))),
|
||||
PFI_SPI1_DA0 = ((u32)(&(JL_IMAP->FI_SPI1_DA0))),
|
||||
PFI_SPI1_DA1 = ((u32)(&(JL_IMAP->FI_SPI1_DA1))),
|
||||
PFI_SPI1_DA2 = ((u32)(&(JL_IMAP->FI_SPI1_DA2))),
|
||||
PFI_SPI1_DA3 = ((u32)(&(JL_IMAP->FI_SPI1_DA3))),
|
||||
PFI_SPI2_CLK = ((u32)(&(JL_IMAP->FI_SPI2_CLK))),
|
||||
PFI_SPI2_DA0 = ((u32)(&(JL_IMAP->FI_SPI2_DA0))),
|
||||
PFI_SPI2_DA1 = ((u32)(&(JL_IMAP->FI_SPI2_DA1))),
|
||||
PFI_SPI2_DA2 = ((u32)(&(JL_IMAP->FI_SPI2_DA2))),
|
||||
PFI_SPI2_DA3 = ((u32)(&(JL_IMAP->FI_SPI2_DA3))),
|
||||
|
||||
PFI_SD0_CMD = ((u32)(&(JL_IMAP->FI_SD0_CMD))),
|
||||
PFI_SD0_DA0 = ((u32)(&(JL_IMAP->FI_SD0_DA0))),
|
||||
PFI_SD0_DA1 = ((u32)(&(JL_IMAP->FI_SD0_DA1))),
|
||||
PFI_SD0_DA2 = ((u32)(&(JL_IMAP->FI_SD0_DA2))),
|
||||
PFI_SD0_DA3 = ((u32)(&(JL_IMAP->FI_SD0_DA3))),
|
||||
|
||||
PFI_IIC0_SCL = ((u32)(&(JL_IMAP->FI_IIC0_SCL))),
|
||||
PFI_IIC0_SDA = ((u32)(&(JL_IMAP->FI_IIC0_SDA))),
|
||||
PFI_UART0_RX = ((u32)(&(JL_IMAP->FI_UART0_RX))),
|
||||
PFI_UART1_RX = ((u32)(&(JL_IMAP->FI_UART1_RX))),
|
||||
// PFI_UART1_CTS = ((u32)(&(JL_IMAP->FI_UART1_CTS))),
|
||||
PFI_UART2_RX = ((u32)(&(JL_IMAP->FI_UART2_RX))),
|
||||
|
||||
// PFI_TDM_S_WCK = ((u32)(&(JL_IMAP->FI_TDM_S_WCK))),
|
||||
// PFI_TDM_S_BCK = ((u32)(&(JL_IMAP->FI_TDM_S_BCK))),
|
||||
// PFI_TDM_M_DA = ((u32)(&(JL_IMAP->FI_TDM_M_DA))),
|
||||
// PFI_RDEC0_DAT0 = ((u32)(&(JL_IMAP->FI_RDEC0_DAT0))),
|
||||
// PFI_RDEC0_DAT1 = ((u32)(&(JL_IMAP->FI_RDEC0_DAT1))),
|
||||
// PFI_RDEC1_DAT0 = ((u32)(&(JL_IMAP->FI_RDEC1_DAT0))),
|
||||
// PFI_RDEC1_DAT1 = ((u32)(&(JL_IMAP->FI_RDEC1_DAT1))),
|
||||
// PFI_RDEC2_DAT0 = ((u32)(&(JL_IMAP->FI_RDEC2_DAT0))),
|
||||
// PFI_RDEC2_DAT1 = ((u32)(&(JL_IMAP->FI_RDEC2_DAT1))),
|
||||
// PFI_ALNK0_MCLK = ((u32)(&(JL_IMAP->FI_ALNK0_MCLK))),
|
||||
// PFI_ALNK0_LRCK = ((u32)(&(JL_IMAP->FI_ALNK0_LRCK))),
|
||||
// PFI_ALNK0_SCLK = ((u32)(&(JL_IMAP->FI_ALNK0_SCLK))),
|
||||
// PFI_ALNK0_DAT0 = ((u32)(&(JL_IMAP->FI_ALNK0_DAT0))),
|
||||
// PFI_ALNK0_DAT1 = ((u32)(&(JL_IMAP->FI_ALNK0_DAT1))),
|
||||
// PFI_ALNK0_DAT2 = ((u32)(&(JL_IMAP->FI_ALNK0_DAT2))),
|
||||
// PFI_ALNK0_DAT3 = ((u32)(&(JL_IMAP->FI_ALNK0_DAT3))),
|
||||
// PFI_PLNK_DAT0 = ((u32)(&(JL_IMAP->FI_PLNK_DAT0))),
|
||||
// PFI_PLNK_DAT1 = ((u32)(&(JL_IMAP->FI_PLNK_DAT1))),
|
||||
// PFI_SPDIF_DIA = ((u32)(&(JL_IMAP->FI_SPDIF_DIA))),
|
||||
// PFI_SPDIF_DIB = ((u32)(&(JL_IMAP->FI_SPDIF_DIB))),
|
||||
// PFI_SPDIF_DIC = ((u32)(&(JL_IMAP->FI_SPDIF_DIC))),
|
||||
// PFI_SPDIF_DID = ((u32)(&(JL_IMAP->FI_SPDIF_DID))),
|
||||
// PFI_CAN_RX = ((u32)(&(JL_IMAP->FI_CAN_RX))),
|
||||
PFI_QDEC0_A = ((u32)(&(JL_IMAP->FI_QDEC0_A))),
|
||||
PFI_QDEC0_B = ((u32)(&(JL_IMAP->FI_QDEC0_B))),
|
||||
PFI_CHAIN_IN0 = ((u32)(&(JL_IMAP->FI_CHAIN_IN0))),
|
||||
PFI_CHAIN_IN1 = ((u32)(&(JL_IMAP->FI_CHAIN_IN1))),
|
||||
PFI_CHAIN_IN2 = ((u32)(&(JL_IMAP->FI_CHAIN_IN2))),
|
||||
PFI_CHAIN_IN3 = ((u32)(&(JL_IMAP->FI_CHAIN_IN3))),
|
||||
PFI_CHAIN_RST = ((u32)(&(JL_IMAP->FI_CHAIN_RST))),
|
||||
PFI_TOTAl = ((u32)(&(JL_IMAP->FI_TOTAL))),
|
||||
};
|
||||
|
||||
#define INPUT_GP_ICH_MAX 6
|
||||
#define OUTPUT_GP_OCH_MAX 8
|
||||
|
||||
enum OUTPUT_CH_SIGNAL {
|
||||
OUTPUT_CH_SIGNAL_TIMER0_PWM,//8
|
||||
OUTPUT_CH_SIGNAL_TIMER1_PWM,
|
||||
OUTPUT_CH_SIGNAL_TIMER2_PWM,
|
||||
OUTPUT_CH_SIGNAL_TIMER3_PWM,
|
||||
// OUTPUT_CH_SIGNAL_TIMER4_PWM,
|
||||
// OUTPUT_CH_SIGNAL_TIMER5_PWM,
|
||||
OUTPUT_CH_SIGNAL_GP_ICH0,
|
||||
OUTPUT_CH_SIGNAL_GP_ICH1,
|
||||
OUTPUT_CH_SIGNAL_UART1_RTS,
|
||||
OUTPUT_CH_SIGNAL_PLNK_CLK,
|
||||
OUTPUT_CH_SIGNAL_WL_AMPE,
|
||||
OUTPUT_CH_SIGNAL_WL_LNAE,
|
||||
OUTPUT_CH_SIGNAL_WLC_INT_ACTIVE,
|
||||
OUTPUT_CH_SIGNAL_WLC_INT_STATUS,
|
||||
OUTPUT_CH_SIGNAL_WLC_INT_FREQ,
|
||||
OUTPUT_CH_SIGNAL_AUD_DBG_CLKO,
|
||||
OUTPUT_CH_SIGNAL_AUD_DBG_DATO0,
|
||||
OUTPUT_CH_SIGNAL_AUD_DBG_DATO1,
|
||||
OUTPUT_CH_SIGNAL_AUD_DBG_DATO2,
|
||||
OUTPUT_CH_SIGNAL_AUD_DBG_DATO3,
|
||||
OUTPUT_CH_SIGNAL_AUD_DBG_DATO4,
|
||||
OUTPUT_CH_SIGNAL_CLOCK_OUT0,
|
||||
OUTPUT_CH_SIGNAL_CLOCK_OUT1,
|
||||
OUTPUT_CH_SIGNAL_CLOCK_OUT2,
|
||||
OUTPUT_CH_SIGNAL_P33_CLK_DBG,
|
||||
OUTPUT_CH_SIGNAL_P33_SIG_DBG0,
|
||||
OUTPUT_CH_SIGNAL_P33_SIG_DBG1,
|
||||
OUTPUT_CH_SIGNAL_USB_DBG_OUT,
|
||||
OUTPUT_CH_SIGNAL_P11_DBG_OUT,
|
||||
OUTPUT_CH_SIGNAL_WL_DBG_PORTx,//fix wl0~7对应och0~7
|
||||
|
||||
// OUTPUT_CH_SIGNAL_MCPWM0_H,
|
||||
// OUTPUT_CH_SIGNAL_MCPWM0_L,
|
||||
// OUTPUT_CH_SIGNAL_MCPWM1_H,
|
||||
// OUTPUT_CH_SIGNAL_MCPWM1_L,
|
||||
// OUTPUT_CH_SIGNAL_LEDC0_OUT,
|
||||
// OUTPUT_CH_SIGNAL_LEDC1_OUT,
|
||||
};
|
||||
|
||||
enum INPUT_CH_TYPE {
|
||||
INPUT_CH_TYPE_GP_ICH = 0,
|
||||
INPUT_CH_TYPE_TIME2_PWM = 6,
|
||||
INPUT_CH_TYPE_TIME3_PWM,
|
||||
INPUT_CH_TYPE_WL_AMPE,
|
||||
INPUT_CH_TYPE_WL_LNAE,
|
||||
INPUT_CH_TYPE_MAX,
|
||||
};
|
||||
|
||||
enum INPUT_CH_SIGNAL {
|
||||
//ICH_CON0
|
||||
INPUT_CH_SIGNAL_TIMER0_CIN = 0,//5
|
||||
INPUT_CH_SIGNAL_TIMER1_CIN,
|
||||
INPUT_CH_SIGNAL_TIMER2_CIN,
|
||||
INPUT_CH_SIGNAL_TIMER3_CIN,
|
||||
// INPUT_CH_SIGNAL_TIMER4_CIN,
|
||||
// INPUT_CH_SIGNAL_TIMER5_CIN,
|
||||
INPUT_CH_SIGNAL_TIMER0_CAPTURE,
|
||||
INPUT_CH_SIGNAL_TIMER1_CAPTURE,
|
||||
//ICH_CON1
|
||||
INPUT_CH_SIGNAL_TIMER2_CAPTURE,
|
||||
INPUT_CH_SIGNAL_TIMER3_CAPTURE,
|
||||
// INPUT_CH_SIGNAL_TIMER4_CAPTURE,
|
||||
// INPUT_CH_SIGNAL_TIMER5_CAPTURE,
|
||||
INPUT_CH_SIGNAL_MCPWM0_CK,
|
||||
INPUT_CH_SIGNAL_MCPWM1_CK,
|
||||
INPUT_CH_SIGNAL_MCPWM0_FP,
|
||||
INPUT_CH_SIGNAL_MCPWM1_FP,
|
||||
//ICH_CON2
|
||||
INPUT_CH_SIGNAL_UART1_CTS,
|
||||
INPUT_CH_SIGNAL_PLNK_IDAT0,
|
||||
INPUT_CH_SIGNAL_PLNK_IDAT1,
|
||||
INPUT_CH_SIGNAL_CAP,//CAP_MUX_OUT
|
||||
INPUT_CH_SIGNAL_CLK_PIN, //CLK_MUX_IN
|
||||
INPUT_CH_SIGNAL_EXT_CLK, //EXT_CLK_P
|
||||
// INPUT_CH_SIGNAL_IRFLT,
|
||||
//ICH_CON3
|
||||
INPUT_CH_SIGNAL_IMD_TE,
|
||||
INPUT_CH_SIGNAL_WLC_EXT_ACT,
|
||||
INPUT_CH_SIGNAL_AUD_DBG_DATI,
|
||||
INPUT_CH_SIGNAL_SPI1_CS,
|
||||
INPUT_CH_SIGNAL_SPI2_CS,
|
||||
INPUT_CH_SIGNAL_RESERVE0,
|
||||
//ICH_CON4
|
||||
// INPUT_CH_SIGNAL_QDEC_SIN0,
|
||||
// INPUT_CH_SIGNAL_QDEC_SIN1,
|
||||
};
|
||||
enum gpio_function {
|
||||
PORT_FUNC_NULL, //null
|
||||
//uart
|
||||
PORT_FUNC_UART0_TX, //out
|
||||
PORT_FUNC_UART0_RX,//in
|
||||
PORT_FUNC_UART1_TX, //out
|
||||
PORT_FUNC_UART1_RX,//in
|
||||
PORT_FUNC_UART2_TX, //out
|
||||
PORT_FUNC_UART2_RX,//in
|
||||
PORT_FUNC_UART1_RTS,//out
|
||||
PORT_FUNC_UART1_CTS,//in
|
||||
|
||||
//spi
|
||||
// PORT_FUNC_SPI0_CLK,
|
||||
// PORT_FUNC_SPI0_DA0,
|
||||
// PORT_FUNC_SPI0_DA1,
|
||||
// PORT_FUNC_SPI0_DA2,
|
||||
// PORT_FUNC_SPI0_DA3,
|
||||
PORT_FUNC_SPI1_CS,//ich slave
|
||||
PORT_FUNC_SPI1_CLK,
|
||||
PORT_FUNC_SPI1_DA0,
|
||||
PORT_FUNC_SPI1_DA1,
|
||||
PORT_FUNC_SPI1_DA2,
|
||||
PORT_FUNC_SPI1_DA3,
|
||||
PORT_FUNC_SPI2_CS,//ich slave
|
||||
PORT_FUNC_SPI2_CLK,
|
||||
PORT_FUNC_SPI2_DA0,
|
||||
PORT_FUNC_SPI2_DA1,
|
||||
PORT_FUNC_SPI2_DA2,
|
||||
PORT_FUNC_SPI2_DA3,
|
||||
|
||||
//iic
|
||||
PORT_FUNC_IIC_SCL,
|
||||
PORT_FUNC_IIC_SDA,
|
||||
|
||||
//sd
|
||||
PORT_FUNC_SD0_CLK,//out
|
||||
PORT_FUNC_SD0_CMD,
|
||||
PORT_FUNC_SD0_DA0,
|
||||
PORT_FUNC_SD0_DA1,
|
||||
PORT_FUNC_SD0_DA2,
|
||||
PORT_FUNC_SD0_DA3,
|
||||
|
||||
//timer
|
||||
PORT_FUNC_TIMER0_PWM,
|
||||
PORT_FUNC_TIMER1_PWM,
|
||||
PORT_FUNC_TIMER2_PWM,
|
||||
PORT_FUNC_TIMER3_PWM,
|
||||
// PORT_FUNC_TIMER4_PWM,
|
||||
// PORT_FUNC_TIMER5_PWM,
|
||||
PORT_FUNC_TIMER0_CAPTURE,
|
||||
PORT_FUNC_TIMER1_CAPTURE,
|
||||
PORT_FUNC_TIMER2_CAPTURE,
|
||||
PORT_FUNC_TIMER3_CAPTURE,
|
||||
// PORT_FUNC_TIMER4_CAPTURE,
|
||||
// PORT_FUNC_TIMER5_CAPTURE,
|
||||
|
||||
//mcpwm
|
||||
PORT_FUNC_MCPWM0_H,
|
||||
PORT_FUNC_MCPWM0_L,
|
||||
PORT_FUNC_MCPWM1_H,
|
||||
PORT_FUNC_MCPWM1_L,
|
||||
PORT_FUNC_MCPWM0_FP,
|
||||
PORT_FUNC_MCPWM1_FP,
|
||||
PORT_FUNC_MCPWM0_CK,
|
||||
PORT_FUNC_MCPWM1_CK,
|
||||
|
||||
//clk_out
|
||||
PORT_FUNC_OCH_CLOCK_OUT0,
|
||||
PORT_FUNC_OCH_CLOCK_OUT1,//PORT_FUNC_OCH_RESERVED0,//不连续
|
||||
PORT_FUNC_OCH_CLOCK_OUT2,
|
||||
// PORT_FUNC_OCH_CLOCK_OUT3,
|
||||
|
||||
//other
|
||||
PORT_FUNC_IRFLT_0, //实际只有1个IRFLT
|
||||
PORT_FUNC_IRFLT_1,
|
||||
PORT_FUNC_IRFLT_2,
|
||||
PORT_FUNC_IRFLT_3,
|
||||
|
||||
PORT_FUNC_CLK_PIN,//CLK_MUX_IN
|
||||
// PORT_FUNC_PORT_WKUP,
|
||||
PORT_FUNC_GPADC, //in
|
||||
PORT_FUNC_PWM_LED,
|
||||
|
||||
//plnk
|
||||
// PORT_FUNC_PLNK_SCLK,//out
|
||||
// PORT_FUNC_PLNK_DAT0,//in
|
||||
// PORT_FUNC_PLNK_DAT1,//in
|
||||
|
||||
//ledc
|
||||
// PORT_FUNC_LEDC0_OUT,
|
||||
// PORT_FUNC_LEDC1_OUT,
|
||||
|
||||
//rdec
|
||||
// PORT_FUNC_RDEC0_PORT0,
|
||||
// PORT_FUNC_RDEC0_PORT1,
|
||||
|
||||
//qdec
|
||||
PORT_FUNC_RDEC0_PORTA,
|
||||
PORT_FUNC_RDEC0_PORTB,
|
||||
//chain
|
||||
};
|
||||
/**************************************************/
|
||||
#define __struct(x) (struct x##_reg *)
|
||||
#define _struct(x) __struct(x)
|
||||
#ifdef GPIOA
|
||||
#define __PORTPA ((struct port_reg *)JL_PORTA)
|
||||
#endif
|
||||
#ifdef GPIOB
|
||||
#define __PORTPB ((struct port_reg *)JL_PORTB)
|
||||
#endif
|
||||
#ifdef GPIOC
|
||||
#define __PORTPC ((struct port_reg *)JL_PORTC)
|
||||
#endif
|
||||
#ifdef GPIOD
|
||||
#define __PORTPD ((struct port_reg *)JL_PORTD)
|
||||
#endif
|
||||
#ifdef GPIOE
|
||||
#define __PORTPE ((struct port_reg *)JL_PORTE)
|
||||
#endif
|
||||
#ifdef GPIOF
|
||||
#define __PORTPF ((struct port_reg *)JL_PORTF)
|
||||
#endif
|
||||
#ifdef GPIOG
|
||||
#define __PORTPG ((struct port_reg *)JL_PORTG)
|
||||
#endif
|
||||
#ifdef GPIOH
|
||||
#define __PORTPH ((struct port_reg *)JL_PORTH)
|
||||
#endif
|
||||
#ifdef GPIOP
|
||||
#define __PORTPP ((struct port_reg *)JL_PORTP)
|
||||
#endif
|
||||
#ifdef GPIOR
|
||||
#define __PORTPR ((struct port_pr_reg *)R3_PR_IO_P)
|
||||
#endif
|
||||
#ifdef GPIOUSB
|
||||
#define __PORTPU ((struct usb_reg *)JL_PORTUSB)
|
||||
#endif
|
||||
#define __portx(x,y) __PORT##x->y
|
||||
#define _portx(x,y) __portx(x,y)
|
||||
#define __toggle_port(x,y) __PORT##x->out ^= y;
|
||||
#define _toggle_port(port,pin) __toggle_port(port,pin)
|
||||
|
||||
//log:
|
||||
#define GPIO_LOG_FORMAT "0x%04x 0x%04x 0x%04x 0x%04x 0x%04x,0x%04x 0x%04x,0x%04x 0x%04x,0x%04x 0x%04x"
|
||||
#define GPIO_NO_SUPPORT_FUN "------"
|
||||
#define GPIO_LOG_PORT(x,y) JL_PORT##x->OUT&y,JL_PORT##x->DIR&y,JL_PORT##x->DIE&y,JL_PORT##x->DIEH&y,JL_PORT##x->PU0&y,JL_PORT##x->PU1&y,JL_PORT##x->PD0&y,JL_PORT##x->PD1&y,JL_PORT##x->HD0&y,JL_PORT##x->HD1&y,JL_PORT##x->SPL&y
|
||||
#ifdef GPIOP //no use
|
||||
#define GPIO_LOG_PORTP JL_PORTP->OUT,JL_PORTP->DIR,JL_PORTP->DIE,JL_PORTP->DIEH,JL_PORTP->PU0,JL_PORTP->PU1,JL_PORTP->PD0,JL_PORTP->PD1,JL_PORTP->HD0,JL_PORTP->HD1
|
||||
#endif
|
||||
#ifdef GPIOR
|
||||
#define GPIO_LOG_FORMAT_R "0x%04x 0x%04x 0x%04x %s 0x%04x,0x%04x 0x%04x,0x%04x 0x%04x,0x%04x %s"
|
||||
#define GPIO_LOG_PORTR R3_PR_OUT,R3_PR_DIR,R3_PR_DIE,GPIO_NO_SUPPORT_FUN,R3_PR_PU0,R3_PR_PU1,R3_PR_PD0,R3_PR_PD1,R3_PR_HD0,R3_PR_HD1,GPIO_NO_SUPPORT_FUN
|
||||
#endif
|
||||
#ifdef GPIOUSB
|
||||
#define GPIO_LOG_FORMAT_U "0x%04x 0x%04x 0x%04x 0x%04x 0x%04x,%s 0x%04x,%s %s,%s 0x%04x"
|
||||
#define GPIO_LOG_PORTU _portx(PU,out),_portx(PU,dir),_portx(PU,die),_portx(PU,dieh),_portx(PU,pu0),GPIO_NO_SUPPORT_FUN,_portx(PU,pd0),GPIO_NO_SUPPORT_FUN,GPIO_NO_SUPPORT_FUN,GPIO_NO_SUPPORT_FUN,_portx(PU,spl)
|
||||
#endif
|
||||
/*************************function*************************/
|
||||
struct port_reg *gpio2reg(u32 gpio);
|
||||
void usb_iomode(const u32 enable);
|
||||
|
||||
int gpio_hw_write(const u32 gpio, const u32 value);//return <0:error
|
||||
int gpio_hw_read(const u32 gpio);//return <0:error
|
||||
int get_gpio(const char *p);//return <0:error
|
||||
|
||||
/**************************************************************/
|
||||
/*********************multi pin interface***************************/
|
||||
//多io同一模式
|
||||
int gpio_hw_port_pin_judge(const enum gpio_port port, u32 pin);
|
||||
int gpio_hw_set_direction(const enum gpio_port port, u32 pin, const u32 value);
|
||||
int gpio_hw_direction_input(const enum gpio_port port, u32 pin);
|
||||
int gpio_hw_direction_output(const enum gpio_port port, u32 pin, const int value);/////////
|
||||
int gpio_hw_write_port(const enum gpio_port port, u32 pin, const u32 value);
|
||||
int gpio_hw_set_output_value(const enum gpio_port port, u32 pin, const u32 value);
|
||||
int gpio_hw_set_pull_up(const enum gpio_port port, u32 pin, const enum gpio_pullup_mode value);
|
||||
int gpio_hw_set_pull_down(const enum gpio_port port, u32 pin, const enum gpio_pulldown_mode value);//portabcdpr:pd0,pd1,usb:pd0
|
||||
int gpio_hw_set_drive_strength(const enum gpio_port port, u32 pin, const enum gpio_drive_strength value);
|
||||
int gpio_hw_set_die(const enum gpio_port port, u32 pin, const int value);
|
||||
int gpio_hw_set_dieh(const enum gpio_port port, u32 pin, const u32 value);
|
||||
int gpio_hw_set_spl(const enum gpio_port port, u32 pin, const u32 value);
|
||||
//read
|
||||
int gpio_hw_read_port(const enum gpio_port port, u32 pin);
|
||||
int gpio_hw_read_out_level(const enum gpio_port port, u32 pin);
|
||||
u32 gpio_hw_read_drive_strength(const enum gpio_port port, u32 pin);//return hd1:高16位, hd0:低16位
|
||||
|
||||
//多io不同模式
|
||||
int gpio_hw_op_dir(const enum gpio_port port, u32 pin, u32 value, const enum port_op_mode op);
|
||||
int gpio_hw_op_out(const enum gpio_port port, u32 pin, u32 value, const enum port_op_mode op);
|
||||
int gpio_hw_op_die(const enum gpio_port port, u32 pin, u32 value, const enum port_op_mode op);
|
||||
int gpio_hw_op_dieh(const enum gpio_port port, u32 pin, u32 value, const enum port_op_mode op);
|
||||
int gpio_hw_op_pu0(const enum gpio_port port, u32 pin, u32 value, const enum port_op_mode op);
|
||||
int gpio_hw_op_pu1(const enum gpio_port port, u32 pin, u32 value, const enum port_op_mode op);
|
||||
int gpio_hw_op_pd0(const enum gpio_port port, u32 pin, u32 value, const enum port_op_mode op);
|
||||
int gpio_hw_op_pd1(const enum gpio_port port, u32 pin, u32 value, const enum port_op_mode op);
|
||||
|
||||
//=================================================================================//
|
||||
//@brief: CrossBar 获取某IO的输出映射寄存器
|
||||
//=================================================================================//
|
||||
u32 *gpio2crossbar_outreg(u32 gpio);
|
||||
u32 gpio2crossbar_inport(u32 gpio);
|
||||
int gpio_set_fun_output_port(u32 gpio, u32 fun_index, u8 dir_ctl, u8 data_ctl);
|
||||
int gpio_disable_fun_output_port(u32 gpio);
|
||||
int gpio_set_fun_input_port(u32 gpio, enum PFI_TABLE pfun);
|
||||
int gpio_disable_fun_input_port(enum PFI_TABLE pfun);
|
||||
|
||||
//=================================================================================//
|
||||
//@brief: Output/input Channel输出设置 API, 将指定IO口设置为某个外设的输出
|
||||
//=================================================================================//
|
||||
int gpio_och_sel_output_signal(u32 gpio, enum OUTPUT_CH_SIGNAL signal);
|
||||
int gpio_och_disable_output_signal(u32 gpio, enum OUTPUT_CH_SIGNAL signal);
|
||||
int gpio_ich_sel_input_signal(u32 gpio, enum INPUT_CH_SIGNAL signal, enum INPUT_CH_TYPE type);
|
||||
int gpio_ich_disable_input_signal(u32 gpio, enum INPUT_CH_SIGNAL signal, enum INPUT_CH_TYPE type);
|
||||
|
||||
u32 gpio_get_ich_use_flag();
|
||||
//获取空闲的gp_ich
|
||||
//return: 0xff:error
|
||||
u8 gpio_get_unoccupied_gp_ich();
|
||||
//value:gp_ich号
|
||||
void gpio_release_gp_ich(u8 value);
|
||||
|
||||
u32 get_sfc_port(void);
|
||||
//打印指定组别指定pin的crossbar信息
|
||||
void gpio_crossbar_fo_dump(char px_name[], u8 max_px_out_num, u16 px_mask, u32 *omap_ptr);
|
||||
void gpio_crossbar_fi_dump(char px_name[], u8 max_px_in_num, u16 px_mask, u8 px_in);
|
||||
|
||||
#endif /*GPIO_H*/
|
||||
@@ -0,0 +1,95 @@
|
||||
#ifndef __GPTIMER_HW_H__
|
||||
#define __GPTIMER_HW_H__
|
||||
|
||||
//BR35
|
||||
#include "cpu.h"
|
||||
#include "gpio.h"
|
||||
#include "gptimer_hw_v5.h"
|
||||
|
||||
typedef JL_TIMER_TypeDef GPTIMER;
|
||||
#define GPTIMER0 JL_TIMER0
|
||||
#define GPTIMER1 JL_TIMER1
|
||||
#define GPTIMER2 JL_TIMER2
|
||||
#define GPTIMER3 JL_TIMER3
|
||||
#define TIMER_MAX_NUM 4
|
||||
#define TIMER_BASE_ADDR GPTIMER0
|
||||
#define TIMER_OFFSET (GPTIMER1 - GPTIMER0)
|
||||
|
||||
#define TIMER_CNT_SIZE 0xFFFF
|
||||
#define TIMER_PRD_SIZE 0xFFFF
|
||||
#define TIMER_PWM_SIZE 0xFFFF
|
||||
|
||||
#define IRQ_TIMEx_IDX_LIST IRQ_TIME0_IDX, \
|
||||
IRQ_TIME1_IDX, \
|
||||
IRQ_TIME2_IDX, \
|
||||
IRQ_TIME3_IDX, \
|
||||
|
||||
#define IRFLT_SRC_TABLE_LIST \
|
||||
0, /* lsb_clk */ \
|
||||
0, /* lsb_clk */ \
|
||||
12, /* std_12m */ \
|
||||
24, /* std_24m */ \
|
||||
|
||||
typedef enum gptimerx : u8 {
|
||||
TIMER0 = 0,
|
||||
TIMER1,
|
||||
TIMER2,
|
||||
TIMER3,
|
||||
TIMERx, //传入此参数时,内部自动分配一个空闲TIMER
|
||||
} timer_dev;
|
||||
|
||||
|
||||
//以下宏定义给系统 timer 驱动使用
|
||||
#define GPTIMER_PND_CLR (0b1<<14)
|
||||
|
||||
#define GPTIMER_CLK_SRC_LSB (0b0001<<10)
|
||||
#define GPTIMER_CLK_SRC_RC250K (0b0010<<10)
|
||||
#define GPTIMER_CLK_SRC_RC16M (0b0011<<10)
|
||||
#define GPTIMER_CLK_SRC_LRC (0b0100<<10)
|
||||
#define GPTIMER_CLK_SRC_STD12M (0b0101<<10)
|
||||
#define GPTIMER_CLK_SRC_STD24M (0b0110<<10)
|
||||
#define GPTIMER_CLK_SRC_STD48M (0b0111<<10)
|
||||
#define GPTIMER_CLK_SRC_CLKOUT2 (0b1000<<10)
|
||||
#define GPTIMER_CLK_SRC_PATCLK (0b1001<<10)
|
||||
#define GPTIMER_CLK_SRC_HSB (0b1010<<10)
|
||||
#define GPTIMER_CLK_SRC_WATCLK (0b1011<<10)
|
||||
|
||||
#define GPTIMER_CLK_DIV_1 (0b0000<<4)
|
||||
#define GPTIMER_CLK_DIV_4 (0b0001<<4)
|
||||
#define GPTIMER_CLK_DIV_16 (0b0010<<4)
|
||||
#define GPTIMER_CLK_DIV_64 (0b0011<<4)
|
||||
#define GPTIMER_CLK_DIV_2 (0b0100<<4)
|
||||
#define GPTIMER_CLK_DIV_8 (0b0101<<4)
|
||||
#define GPTIMER_CLK_DIV_32 (0b0110<<4)
|
||||
#define GPTIMER_CLK_DIV_128 (0b0111<<4)
|
||||
#define GPTIMER_CLK_DIV_256 (0b1000<<4)
|
||||
#define GPTIMER_CLK_DIV_1024 (0b1001<<4)
|
||||
#define GPTIMER_CLK_DIV_4096 (0b1010<<4)
|
||||
#define GPTIMER_CLK_DIV_16384 (0b1011<<4)
|
||||
#define GPTIMER_CLK_DIV_512 (0b1100<<4)
|
||||
#define GPTIMER_CLK_DIV_2048 (0b1101<<4)
|
||||
#define GPTIMER_CLK_DIV_8192 (0b1110<<4)
|
||||
#define GPTIMER_CLK_DIV_32768 (0b1111<<4)
|
||||
|
||||
#define GPTIMER_TIMER_MODE (0b1<<0)
|
||||
|
||||
#define GPTIMER_SYS GPTIMER3
|
||||
#define GPTIMER_SYS_IRQ_INDEX IRQ_TIME3_IDX
|
||||
#define GPTIMER_SYS_START() GPTIMER_SYS->CON |= GPTIMER_TIMER_MODE
|
||||
#define GPTIMER_SYS_PAUSE() GPTIMER_SYS->CON &= ~GPTIMER_TIMER_MODE
|
||||
#define GPTIMER_SYS_EN_CHECK() GPTIMER_SYS->CON & GPTIMER_TIMER_MODE
|
||||
#define GPTIMER_SYS_CLR_PND() GPTIMER_SYS->CON |= GPTIMER_PND_CLR
|
||||
|
||||
#define GPTIMER_SYS_INIT() do{GPTIMER_SYS->CON = GPTIMER_PND_CLR|GPTIMER_CLK_SRC_STD12M|GPTIMER_CLK_DIV_4; \
|
||||
GPTIMER_SYS->PRD = 0; \
|
||||
GPTIMER_SYS->CNT = 0;}while(0) \
|
||||
|
||||
#define GPTIMER_SYS_GET_CNT GPTIMER_SYS->CNT
|
||||
#define GPTIMER_SYS_SET_CNT(x) GPTIMER_SYS->CNT = (x)
|
||||
#define GPTIMER_SYS_GET_PRD GPTIMER_SYS->PRD
|
||||
#define GPTIMER_SYS_SET_PRD(x) GPTIMER_SYS->PRD = (x)-1
|
||||
#define GPTIMER_SYS_CLK_SRC 12 //MHz单位
|
||||
#define GPTIMER_SYS_CLK_DIV 2 // 右移两位 等效于 除以4
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,199 @@
|
||||
#ifndef __HWI_H__
|
||||
#define __HWI_H__
|
||||
|
||||
|
||||
//=================================================
|
||||
#define IRQ_EMUEXCPT_IDX 0
|
||||
#define IRQ_EXCEPTION_IDX 1
|
||||
#define IRQ_SYSCALL_IDX 2
|
||||
#define IRQ_TICK_TMR_IDX 3
|
||||
#define IRQ_TIME0_IDX 4
|
||||
#define IRQ_TIME1_IDX 5
|
||||
#define IRQ_TIME2_IDX 6
|
||||
#define IRQ_UART0_IDX 7
|
||||
#define IRQ_UART1_IDX 8
|
||||
|
||||
#define IRQ_SPI1_IDX 10
|
||||
#define IRQ_IIC0_IDX 11
|
||||
#define IRQ_PORT_IDX 12
|
||||
#define IRQ_GPADC_IDX 13
|
||||
#define IRQ_UART2_IDX 14
|
||||
#define IRQ_LRCT_IDX 15
|
||||
|
||||
#define IRQ_GPCNT0_IDX 16
|
||||
#define IRQ_QDEC0_IDX 17
|
||||
#define IRQ_SD0_IDX 18
|
||||
#define IRQ_USB_SOF_IDX 19
|
||||
#define IRQ_USB_CTRL_IDX 20
|
||||
|
||||
#define IRQ_TIME3_IDX 22
|
||||
#define IRQ_LED_IDX 23
|
||||
#define IRQ_SD0_BRK_IDX 24
|
||||
#define IRQ_MCPWM_TMR_IDX 25
|
||||
#define IRQ_MCPWM_CHX_IDX 26
|
||||
#define IRQ_PMU_TMR0_IDX 27
|
||||
#define IRQ_PMU_TMR1_IDX 28
|
||||
|
||||
#define IRQ_SPI2_IDX 31
|
||||
|
||||
#define IRQ_P33_IDX 33
|
||||
#define IRQ_PINR_IDX 34
|
||||
#define IRQ_PMU_SOFT0_IDX 35
|
||||
#define IRQ_PMU_SOFT1_IDX 36
|
||||
#define IRQ_PMU_SOFT2_IDX 37
|
||||
#define IRQ_PMU_SOFT3_IDX 38
|
||||
|
||||
#define IRQ_PMU_TMR2_IDX 40
|
||||
#define IRQ_PMU_TMR3_IDX 41
|
||||
|
||||
#define IRQ_SRC0_IDX 66
|
||||
#define IRQ_SPI0_IDX 68
|
||||
|
||||
#define IRQ_DCP_IDX 70
|
||||
|
||||
#define IRQ_DBI_IDX 72
|
||||
#define IRQ_JPG_IDX 73
|
||||
#define IRQ_GPU_IDX 74
|
||||
|
||||
#define IRQ_ADC_IDX 88
|
||||
#define IRQ_AUDIO_IDX 89
|
||||
|
||||
#define IRQ_BT_TIMEBASE_IDX 100
|
||||
#define IRQ_BLE_RX_IDX 101
|
||||
#define IRQ_BLE_EVENT_IDX 102
|
||||
#define IRQ_BT_CLKN_IDX 103
|
||||
#define IRQ_BREDR_IDX 104
|
||||
#define IRQ_BT_RXMCH 105
|
||||
#define IRQ_SYNC_IDX 106
|
||||
|
||||
#define IRQ_SOFT0_IDX 120
|
||||
#define IRQ_SOFT1_IDX 121
|
||||
#define IRQ_SOFT2_IDX 122
|
||||
#define IRQ_SOFT3_IDX 123
|
||||
#define IRQ_SOFT4_IDX 124
|
||||
#define IRQ_SOFT5_IDX 125
|
||||
#define IRQ_SOFT6_IDX 126
|
||||
#define IRQ_SOFT7_IDX 127
|
||||
|
||||
#define MAX_IRQ_ENTRY_NUM 128
|
||||
|
||||
//=================================================
|
||||
|
||||
//=================================================
|
||||
void interrupt_init();
|
||||
|
||||
/* --------------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief 中断注册函数
|
||||
*
|
||||
* @param index 中断号
|
||||
* @param priority 优先级，范围0-6可用
|
||||
* @param handler 中断服务函数
|
||||
* @param cpu_id 相应中断服务函数的CPU
|
||||
*/
|
||||
/* ----------------------------------------------------------------------------*/
|
||||
void request_irq(u8 index, u8 priority, void (*handler)(void), u8 cpu_id);
|
||||
|
||||
void unrequest_irq(u8 index);
|
||||
|
||||
void reg_set_ip(unsigned char index, unsigned char priority, u8 cpu_id);
|
||||
|
||||
/* --------------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief 设置不可屏蔽中断（不可屏蔽中断不区分优先级）
|
||||
* cpu多核同步默认使用0，其他使用1。
|
||||
*
|
||||
* @param index 中断号
|
||||
* @param priority 不可屏蔽优先级，范围 0、1 （CPU_IRQ_IPMASK_LEVEL == 6）
|
||||
* @param cpu_id 相应中断服务函数的CPU
|
||||
*/
|
||||
/* ----------------------------------------------------------------------------*/
|
||||
void irq_unmask_set(u8 index, u8 priority, u8 cpu_id);
|
||||
|
||||
/* --------------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief 取消不可屏蔽中断
|
||||
* cpu多核同步默认使用0，其他使用1。
|
||||
*
|
||||
* @param index 中断号
|
||||
* @param priority 不可屏蔽优先级，范围 0、1、2、3、4、5
|
||||
* @param cpu_id 相应中断服务函数的CPU
|
||||
*/
|
||||
/* ----------------------------------------------------------------------------*/
|
||||
void irq_unmask_unset(u8 index, u8 priority, u8 cpu_id);
|
||||
|
||||
void bit_clr_ie(unsigned char index);
|
||||
void bit_set_ie(unsigned char index);
|
||||
bool irq_read(u32 index);
|
||||
|
||||
#define irq_disable(x) bit_clr_ie(x)
|
||||
#define irq_enable(x) bit_set_ie(x)
|
||||
|
||||
void unmask_enter_critical(void);
|
||||
void unmask_exit_critical(void);
|
||||
|
||||
//---------------------------------------------//
|
||||
// low power waiting
|
||||
//---------------------------------------------//
|
||||
__attribute__((always_inline))
|
||||
static inline void lp_waiting(int *ptr, int pnd, int cpd, char inum)
|
||||
{
|
||||
#if 0
|
||||
q32DSP(core_num())->IWKUP_NUM = inum;
|
||||
while (!(*ptr & pnd)) {
|
||||
asm volatile("idle");
|
||||
}
|
||||
*ptr |= cpd;
|
||||
#else
|
||||
int con;
|
||||
q32DSP(core_num())->IWKUP_NUM = inum;
|
||||
asm volatile(
|
||||
" goto 2f \n\t"
|
||||
" 1: \n\t"
|
||||
" idle \n\t"
|
||||
" 2: \n\t"
|
||||
" %0 = [%1] \n\t"
|
||||
" rep 1 { \n\t" // disable_bpu
|
||||
" if((%0 & %2)==0) goto 1b \n\t"
|
||||
" } \n\t"
|
||||
:"=&r"(con)
|
||||
:"r"(ptr), "r"(pnd), "0"(con)
|
||||
:
|
||||
);
|
||||
*ptr = con | cpd;
|
||||
#endif
|
||||
}
|
||||
|
||||
//---------------------------------------------//
|
||||
// interrupt cli/sti
|
||||
//---------------------------------------------//
|
||||
|
||||
static inline int int_cli(void)
|
||||
{
|
||||
int msg;
|
||||
asm volatile("cli %0" : "=r"(msg) :);
|
||||
return msg;
|
||||
}
|
||||
|
||||
static inline void int_sti(int msg)
|
||||
{
|
||||
asm volatile("sti %0" :: "r"(msg));
|
||||
}
|
||||
|
||||
#ifdef IRQ_TIME_COUNT_EN
|
||||
void irq_handler_enter(int irq);
|
||||
|
||||
void irq_handler_exit(int irq);
|
||||
|
||||
void irq_handler_times_dump();
|
||||
#else
|
||||
|
||||
#define irq_handler_enter(irq) do { }while(0)
|
||||
#define irq_handler_exit(irq) do { }while(0)
|
||||
#define irq_handler_times_dump() do { }while(0)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,97 @@
|
||||
#ifndef __Q32DSP_ICACHE__
|
||||
#define __Q32DSP_ICACHE__
|
||||
|
||||
//*********************************************************************************//
|
||||
// Module name : icache.h //
|
||||
// Description : q32DSP icache control head file //
|
||||
// By Designer : zequan_liu //
|
||||
// Dat changed : //
|
||||
//*********************************************************************************//
|
||||
|
||||
// ------ ------ ------ ------ ------ ------
|
||||
// | c0 | | c1 | | c0 | | c1 | | c0 | | c1 |
|
||||
// ------ ------ ------ ------ ------ ------
|
||||
// | | | | | |
|
||||
// ------ ------ ------ ------ ------ ------
|
||||
// | L1 | | L1 | | L1 | | L1 | | L1 | | L1 |
|
||||
// ------ ------ ------ ------ ------ ------
|
||||
// |_______| |_______| |_______|
|
||||
// | | |
|
||||
// --------- --------- ---------
|
||||
// | flash | | L2i | | L2c |
|
||||
// --------- --------- ---------
|
||||
// | |
|
||||
// --------- ---------
|
||||
// | flash | | flash |
|
||||
// --------- ---------
|
||||
//
|
||||
// INCLUDE_L2I==0 INCLUDE_L2I==1 INCLUDE_L2I==0
|
||||
// INCLUDE_L2C==0 INCLUDE_L2C==0 INCLUDE_L2C==1
|
||||
|
||||
#define INCLUDE_ICU_RPT 0
|
||||
#define INCLUDE_ICU_EMU 0
|
||||
#define INCLUDE_L2I 0 // L2i & L2d separate
|
||||
#define INCLUDE_L2C 0 // L2i & L2d together
|
||||
|
||||
//------------------------------------------------------//
|
||||
// icache level 1 function
|
||||
//------------------------------------------------------//
|
||||
|
||||
void IcuEnable(void);
|
||||
void IcuDisable(void);
|
||||
void IcuInitial(void);
|
||||
void IcuWaitIdle(void);
|
||||
void IcuSetWayNum(unsigned int way);
|
||||
|
||||
void IcuFlushinvAll(void);
|
||||
void IcuFlushinvRegion(unsigned int *beg, unsigned int len); // note len!=0
|
||||
void IcuUnlockAll(void);
|
||||
void IcuUnlockRegion(unsigned int *beg, unsigned int len); // note len!=0
|
||||
void IcuLockRegion(unsigned int *beg, unsigned int len); // note len!=0
|
||||
void IcuPfetchRegion(unsigned int *beg, unsigned int len); // note len!=0
|
||||
|
||||
void IcuReportEnable(void);
|
||||
void IcuReportDisable(void);
|
||||
void IcuReportPrintf(void);
|
||||
void IcuReportClear(void);
|
||||
|
||||
void IcuEmuEnable(void);
|
||||
void IcuEmuDisable(void);
|
||||
void IcuEmuMessage(void);
|
||||
|
||||
//------------------------------------------------------//
|
||||
// icache level 2 function
|
||||
//------------------------------------------------------//
|
||||
|
||||
#if (INCLUDE_L2I)
|
||||
|
||||
void L2iEnable(void);
|
||||
void L2iDisable(void);
|
||||
void L2iInitial(void);
|
||||
void L2iSetWayNum(unsigned int way);
|
||||
|
||||
void L2iFlushinvAll(void);
|
||||
void L2iFlushinvRegion(unsigned int *beg, unsigned int len); // note len!=0
|
||||
void L2iUnlockAll(void);
|
||||
void L2iUnlockRegion(unsigned int *beg, unsigned int len); // note len!=0
|
||||
void L2iLockRegion(unsigned int *beg, unsigned int len); // note len!=0
|
||||
void L2iPfetchRegion(unsigned int *beg, unsigned int len); // note len!=0
|
||||
|
||||
void L2iReportEnable(void);
|
||||
void L2iReportDisable(void);
|
||||
void L2iReportPrintf(void);
|
||||
void L2iReportClear(void);
|
||||
|
||||
void L2iEmuEnable(void);
|
||||
void L2iEmuDisable(void);
|
||||
void L2iEmuMessage(void);
|
||||
|
||||
#endif
|
||||
|
||||
//*********************************************************************************//
|
||||
// //
|
||||
// end of this module //
|
||||
// //
|
||||
//*********************************************************************************//
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,21 @@
|
||||
#ifndef __IIC_HW_H__
|
||||
#define __IIC_HW_H__
|
||||
|
||||
#define MAX_HW_IIC_NUM 2
|
||||
#define P11_HW_IIC_NUM 1 //p11 iic使能,及锁使能
|
||||
// typedef enum {
|
||||
// HW_IIC_0,
|
||||
// // HW_IIC_1,
|
||||
// } hw_iic_dev;
|
||||
|
||||
enum {
|
||||
HW_IIC_0,
|
||||
#if defined(P11_HW_IIC_NUM)&&P11_HW_IIC_NUM
|
||||
HW_P11_IIC_0,//p11 init,pb
|
||||
#endif
|
||||
// HW_IIC_1,
|
||||
};
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,26 @@
|
||||
#ifndef ASM_INCLUDES_H
|
||||
#define ASM_INCLUDES_H
|
||||
|
||||
#include "asm/cpu.h"
|
||||
#include "asm/crc16.h"
|
||||
//#include "clock.h"
|
||||
#include "uart.h"
|
||||
#include "gpio.h"
|
||||
#include "asm/spiflash.h"
|
||||
#include "asm/csfr.h"
|
||||
#include "asm/power_interface.h"
|
||||
#include "asm/efuse.h"
|
||||
#include "asm/debug.h"
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,89 @@
|
||||
|
||||
//===============================================================================//
|
||||
//
|
||||
// input IO define
|
||||
//
|
||||
//===============================================================================//
|
||||
#define PA0_IN 1
|
||||
#define PA1_IN 2
|
||||
#define PA2_IN 3
|
||||
#define PA3_IN 4
|
||||
#define PA4_IN 5
|
||||
#define PA5_IN 6
|
||||
#define PA6_IN 7
|
||||
#define PA7_IN 8
|
||||
#define PA8_IN 9
|
||||
#define PA9_IN 10
|
||||
#define PA10_IN 11
|
||||
#define PA11_IN 12
|
||||
#define PA12_IN 13
|
||||
#define PA13_IN 14
|
||||
#define PB0_IN 15
|
||||
#define PB1_IN 16
|
||||
#define PB2_IN 17
|
||||
#define PB3_IN 18
|
||||
#define PB4_IN 19
|
||||
#define PB5_IN 20
|
||||
#define PB6_IN 21
|
||||
#define PB7_IN 22
|
||||
#define PB8_IN 23
|
||||
#define PC0_IN 24
|
||||
#define PC1_IN 25
|
||||
#define PC2_IN 26
|
||||
#define PC3_IN 27
|
||||
#define PC4_IN 28
|
||||
#define PC5_IN 29
|
||||
#define PC6_IN 30
|
||||
#define PC7_IN 31
|
||||
#define PC8_IN 32
|
||||
#define PC9_IN 33
|
||||
#define PC10_IN 34
|
||||
#define PC11_IN 35
|
||||
#define USBDP_IN 36
|
||||
#define USBDM_IN 37
|
||||
#define PP0_IN 38
|
||||
|
||||
//===============================================================================//
|
||||
//
|
||||
// function input select sfr
|
||||
//
|
||||
//===============================================================================//
|
||||
typedef struct {
|
||||
__RW __u8 FI_GP_ICH0;
|
||||
__RW __u8 FI_GP_ICH1;
|
||||
__RW __u8 FI_GP_ICH2;
|
||||
__RW __u8 FI_GP_ICH3;
|
||||
__RW __u8 FI_GP_ICH4;
|
||||
__RW __u8 FI_GP_ICH5;
|
||||
__RW __u8 FI_SD0_CMD;
|
||||
__RW __u8 FI_SD0_DA0;
|
||||
__RW __u8 FI_SD0_DA1;
|
||||
__RW __u8 FI_SD0_DA2;
|
||||
__RW __u8 FI_SD0_DA3;
|
||||
__RW __u8 FI_SPI1_CLK;
|
||||
__RW __u8 FI_SPI1_DA0;
|
||||
__RW __u8 FI_SPI1_DA1;
|
||||
__RW __u8 FI_SPI1_DA2;
|
||||
__RW __u8 FI_SPI1_DA3;
|
||||
__RW __u8 FI_SPI2_CLK;
|
||||
__RW __u8 FI_SPI2_DA0;
|
||||
__RW __u8 FI_SPI2_DA1;
|
||||
__RW __u8 FI_SPI2_DA2;
|
||||
__RW __u8 FI_SPI2_DA3;
|
||||
__RW __u8 FI_IIC0_SCL;
|
||||
__RW __u8 FI_IIC0_SDA;
|
||||
__RW __u8 FI_UART0_RX;
|
||||
__RW __u8 FI_UART1_RX;
|
||||
__RW __u8 FI_UART2_RX;
|
||||
__RW __u8 FI_QDEC0_A;
|
||||
__RW __u8 FI_QDEC0_B;
|
||||
__RW __u8 FI_CHAIN_IN0;
|
||||
__RW __u8 FI_CHAIN_IN1;
|
||||
__RW __u8 FI_CHAIN_IN2;
|
||||
__RW __u8 FI_CHAIN_IN3;
|
||||
__RW __u8 FI_CHAIN_RST;
|
||||
__RW __u8 FI_TOTAL;
|
||||
} JL_IMAP_TypeDef;
|
||||
|
||||
#define JL_IMAP_BASE (ls_base + map_adr(0x3a, 0x00))
|
||||
#define JL_IMAP ((JL_IMAP_TypeDef *)JL_IMAP_BASE)
|
||||
@@ -0,0 +1,92 @@
|
||||
|
||||
//===============================================================================//
|
||||
//
|
||||
// output function define
|
||||
//
|
||||
//===============================================================================//
|
||||
#define FO_GP_OCH0 ((0 << 2)|BIT(1))
|
||||
#define FO_GP_OCH1 ((1 << 2)|BIT(1))
|
||||
#define FO_GP_OCH2 ((2 << 2)|BIT(1))
|
||||
#define FO_GP_OCH3 ((3 << 2)|BIT(1))
|
||||
#define FO_GP_OCH4 ((4 << 2)|BIT(1))
|
||||
#define FO_GP_OCH5 ((5 << 2)|BIT(1))
|
||||
#define FO_GP_OCH6 ((6 << 2)|BIT(1))
|
||||
#define FO_GP_OCH7 ((7 << 2)|BIT(1))
|
||||
#define FO_SD0_CLK ((8 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SD0_CMD ((9 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SD0_DA0 ((10 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SD0_DA1 ((11 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SD0_DA2 ((12 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SD0_DA3 ((13 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SPI1_CLK ((14 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SPI1_DA0 ((15 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SPI1_DA1 ((16 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SPI1_DA2 ((17 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SPI1_DA3 ((18 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SPI2_CLK ((19 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SPI2_DA0 ((20 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SPI2_DA1 ((21 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SPI2_DA2 ((22 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SPI2_DA3 ((23 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_IIC0_SCL ((24 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_IIC0_SDA ((25 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_UART0_TX ((26 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_UART1_TX ((27 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_UART2_TX ((28 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_MCPWM0_H ((29 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_MCPWM1_H ((30 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_MCPWM0_L ((31 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_MCPWM1_L ((32 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_CHAIN_OUT0 ((33 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_CHAIN_OUT1 ((34 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_CHAIN_OUT2 ((35 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_CHAIN_OUT3 ((36 << 2)|BIT(1)|BIT(0))
|
||||
|
||||
//===============================================================================//
|
||||
//
|
||||
// IO output select sfr
|
||||
//
|
||||
//===============================================================================//
|
||||
typedef struct {
|
||||
__RW __u8 PA0_OUT;
|
||||
__RW __u8 PA1_OUT;
|
||||
__RW __u8 PA2_OUT;
|
||||
__RW __u8 PA3_OUT;
|
||||
__RW __u8 PA4_OUT;
|
||||
__RW __u8 PA5_OUT;
|
||||
__RW __u8 PA6_OUT;
|
||||
__RW __u8 PA7_OUT;
|
||||
__RW __u8 PA8_OUT;
|
||||
__RW __u8 PA9_OUT;
|
||||
__RW __u8 PA10_OUT;
|
||||
__RW __u8 PA11_OUT;
|
||||
__RW __u8 PA12_OUT;
|
||||
__RW __u8 PA13_OUT;
|
||||
__RW __u8 PB0_OUT;
|
||||
__RW __u8 PB1_OUT;
|
||||
__RW __u8 PB2_OUT;
|
||||
__RW __u8 PB3_OUT;
|
||||
__RW __u8 PB4_OUT;
|
||||
__RW __u8 PB5_OUT;
|
||||
__RW __u8 PB6_OUT;
|
||||
__RW __u8 PB7_OUT;
|
||||
__RW __u8 PB8_OUT;
|
||||
__RW __u8 PC0_OUT;
|
||||
__RW __u8 PC1_OUT;
|
||||
__RW __u8 PC2_OUT;
|
||||
__RW __u8 PC3_OUT;
|
||||
__RW __u8 PC4_OUT;
|
||||
__RW __u8 PC5_OUT;
|
||||
__RW __u8 PC6_OUT;
|
||||
__RW __u8 PC7_OUT;
|
||||
__RW __u8 PC8_OUT;
|
||||
__RW __u8 PC9_OUT;
|
||||
__RW __u8 PC10_OUT;
|
||||
__RW __u8 PC11_OUT;
|
||||
__RW __u8 USBDP_OUT;
|
||||
__RW __u8 USBDM_OUT;
|
||||
__RW __u8 PP0_OUT;
|
||||
} JL_OMAP_TypeDef;
|
||||
|
||||
#define JL_OMAP_BASE (ls_base + map_adr(0x36, 0x00))
|
||||
#define JL_OMAP ((JL_OMAP_TypeDef *)JL_OMAP_BASE)
|
||||
@@ -0,0 +1,231 @@
|
||||
#ifndef __KEY_DRV_IR_H__
|
||||
#define __KEY_DRV_IR_H__
|
||||
|
||||
#define IR_PORTA(x) (0x00 + x)
|
||||
#define IR_PORTB(x) (0x10 + x)
|
||||
#define IR_PORTC(x) (0x20 + x)
|
||||
#define IR_PORTD(x) (0x30 + x)
|
||||
#define IR_USBDP (0x3d)
|
||||
#define IR_USBDM (0x3e)
|
||||
|
||||
#define IR_IO IR_PORTA(9)
|
||||
|
||||
/*ir key define*/
|
||||
#define IR_00 0
|
||||
#define IR_01 1
|
||||
#define IR_02 2
|
||||
#define IR_03 3
|
||||
#define IR_04 4
|
||||
#define IR_05 5
|
||||
#define IR_06 6
|
||||
#define IR_07 7
|
||||
#define IR_08 8
|
||||
#define IR_09 9
|
||||
#define IR_10 10
|
||||
#define IR_11 11
|
||||
#define IR_12 12
|
||||
#define IR_13 13
|
||||
#define IR_14 14
|
||||
#define IR_15 15
|
||||
#define IR_16 16
|
||||
#define IR_17 17
|
||||
#define IR_18 18
|
||||
#define IR_19 19
|
||||
#define IR_20 20
|
||||
#define IR_21 21
|
||||
#define IR_22 22
|
||||
|
||||
//////////////////////////////////
|
||||
#define NKEY_00 0xff
|
||||
#define NKEY_01 0xff
|
||||
#define NKEY_02 0xff
|
||||
#define NKEY_03 0xff
|
||||
#define NKEY_04 0xff
|
||||
#define NKEY_05 0xff
|
||||
#define NKEY_06 0xff
|
||||
#define NKEY_07 0xff
|
||||
#define NKEY_08 0xff
|
||||
#define NKEY_09 0xff
|
||||
#define NKEY_0A 0xff
|
||||
#define NKEY_0B 0xff
|
||||
#define NKEY_0C 0xff
|
||||
#define NKEY_0D 0xff
|
||||
#define NKEY_0E 0xff
|
||||
#define NKEY_0F 0xff
|
||||
#define NKEY_10 0xff
|
||||
#define NKEY_11 0xff
|
||||
#define NKEY_12 0xff
|
||||
#define NKEY_13 0xff
|
||||
#define NKEY_14 0xff
|
||||
#define NKEY_15 0xff
|
||||
#define NKEY_16 0xff
|
||||
#define NKEY_17 0xff
|
||||
#define NKEY_18 0xff
|
||||
#define NKEY_19 0xff
|
||||
#define NKEY_1A 0xff
|
||||
#define NKEY_1B 0xff
|
||||
#define NKEY_1C 0xff
|
||||
#define NKEY_1D 0xff
|
||||
#define NKEY_1E 0xff
|
||||
#define NKEY_1F 0xff
|
||||
#define NKEY_20 0xff
|
||||
#define NKEY_21 0xff
|
||||
#define NKEY_22 0xff
|
||||
#define NKEY_23 0xff
|
||||
#define NKEY_24 0xff
|
||||
#define NKEY_25 0xff
|
||||
#define NKEY_26 0xff
|
||||
#define NKEY_27 0xff
|
||||
#define NKEY_28 0xff
|
||||
#define NKEY_29 0xff
|
||||
#define NKEY_2A 0xff
|
||||
#define NKEY_2B 0xff
|
||||
#define NKEY_2C 0xff
|
||||
#define NKEY_2D 0xff
|
||||
#define NKEY_2E 0xff
|
||||
#define NKEY_2F 0xff
|
||||
#define NKEY_30 0xff
|
||||
#define NKEY_31 0xff
|
||||
#define NKEY_32 0xff
|
||||
#define NKEY_33 0xff
|
||||
#define NKEY_34 0xff
|
||||
#define NKEY_35 0xff
|
||||
#define NKEY_36 0xff
|
||||
#define NKEY_37 0xff
|
||||
#define NKEY_38 0xff
|
||||
#define NKEY_39 0xff
|
||||
#define NKEY_3A 0xff
|
||||
#define NKEY_3B 0xff
|
||||
#define NKEY_3C 0xff
|
||||
#define NKEY_3D 0xff
|
||||
#define NKEY_3E 0xff
|
||||
#define NKEY_3F 0xff
|
||||
#define NKEY_40 0xff
|
||||
#define NKEY_41 0xff
|
||||
#define NKEY_42 0xff
|
||||
#define NKEY_43 0xff
|
||||
#define NKEY_44 0xff
|
||||
#define NKEY_45 0xff
|
||||
#define NKEY_46 0xff
|
||||
#define NKEY_47 0xff
|
||||
#define NKEY_48 0xff
|
||||
#define NKEY_49 0xff
|
||||
#define NKEY_4A 0xff
|
||||
#define NKEY_4B 0xff
|
||||
#define NKEY_4C 0xff
|
||||
#define NKEY_4D 0xff
|
||||
#define NKEY_4E 0xff
|
||||
#define NKEY_4F 0xff
|
||||
#define NKEY_50 0xff
|
||||
#define NKEY_51 0xff
|
||||
#define NKEY_52 0xff
|
||||
#define NKEY_53 0xff
|
||||
#define NKEY_54 0xff
|
||||
#define NKEY_55 0xff
|
||||
#define NKEY_56 0xff
|
||||
#define NKEY_57 0xff
|
||||
#define NKEY_58 0xff
|
||||
#define NKEY_59 0xff
|
||||
#define NKEY_5A 0xff
|
||||
#define NKEY_5B 0xff
|
||||
#define NKEY_5C 0xff
|
||||
#define NKEY_5D 0xff
|
||||
#define NKEY_5E 0xff
|
||||
#define NKEY_5F 0xff
|
||||
#define NKEY_60 0xff
|
||||
#define NKEY_61 0xff
|
||||
#define NKEY_62 0xff
|
||||
#define NKEY_63 0xff
|
||||
#define NKEY_64 0xff
|
||||
#define NKEY_65 0xff
|
||||
#define NKEY_66 0xff
|
||||
#define NKEY_67 0xff
|
||||
#define NKEY_68 0xff
|
||||
#define NKEY_69 0xff
|
||||
#define NKEY_6A 0xff
|
||||
#define NKEY_6B 0xff
|
||||
#define NKEY_6C 0xff
|
||||
#define NKEY_6D 0xff
|
||||
#define NKEY_6E 0xff
|
||||
#define NKEY_6F 0xff
|
||||
#define NKEY_70 0xff
|
||||
#define NKEY_71 0xff
|
||||
#define NKEY_72 0xff
|
||||
#define NKEY_73 0xff
|
||||
#define NKEY_74 0xff
|
||||
#define NKEY_75 0xff
|
||||
#define NKEY_76 0xff
|
||||
#define NKEY_77 0xff
|
||||
#define NKEY_78 0xff
|
||||
#define NKEY_79 0xff
|
||||
#define NKEY_7A 0xff
|
||||
#define NKEY_7B 0xff
|
||||
#define NKEY_7C 0xff
|
||||
#define NKEY_7D 0xff
|
||||
#define NKEY_7E 0xff
|
||||
#define NKEY_7F 0xff
|
||||
#define NKEY_80 0xff
|
||||
#define NKEY_81 0xff
|
||||
#define NKEY_82 0xff
|
||||
#define NKEY_83 0xff
|
||||
#define NKEY_84 0xff
|
||||
#define NKEY_85 0xff
|
||||
#define NKEY_86 0xff
|
||||
#define NKEY_87 0xff
|
||||
#define NKEY_88 0xff
|
||||
#define NKEY_89 0xff
|
||||
#define NKEY_8A 0xff
|
||||
#define NKEY_8B 0xff
|
||||
#define NKEY_8C 0xff
|
||||
#define NKEY_8D 0xff
|
||||
#define NKEY_8E 0xff
|
||||
#define NKEY_8F 0xff
|
||||
#define NKEY_90 0xff
|
||||
#define NKEY_91 0xff
|
||||
#define NKEY_92 0xff
|
||||
#define NKEY_93 0xff
|
||||
#define NKEY_94 0xff
|
||||
#define NKEY_95 0xff
|
||||
|
||||
|
||||
typedef struct _IR_CODE {
|
||||
u16 wData; //<键值
|
||||
u16 wUserCode; //<用户码
|
||||
u16 timer_pad;
|
||||
u8 bState; //<接收状态
|
||||
u8 boverflow; //<红外信号超时
|
||||
} IR_CODE;
|
||||
|
||||
enum timer_sel {
|
||||
TIMER0,
|
||||
TIMER1,
|
||||
TIMER2,
|
||||
TIMER3,
|
||||
TIMER4,
|
||||
TIMER5,
|
||||
};
|
||||
|
||||
struct irflt_platform_data {
|
||||
u8 irflt_io;
|
||||
u8 timer;
|
||||
};
|
||||
|
||||
#define IRFLT_PLATFORM_DATA_BEGIN(data) \
|
||||
static const struct irflt_platform_data data = {
|
||||
|
||||
#define IRFLT_PLATFORM_DATA_END() \
|
||||
};
|
||||
|
||||
|
||||
extern const struct device_operations irflt_dev_ops;
|
||||
|
||||
void set_ir_clk(void);
|
||||
void ir_input_io_sel(u8 port);
|
||||
void ir_output_timer_sel();
|
||||
void ir_timeout_set(void);
|
||||
void irflt_config();
|
||||
void log_irflt_info();
|
||||
u8 get_irflt_value(void);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,16 @@
|
||||
#ifndef CPU_IRQ_H
|
||||
#define CPU_IRQ_H
|
||||
|
||||
|
||||
#include "asm/hwi.h"
|
||||
|
||||
#define ___interrupt __attribute__((interrupt("")))
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,145 @@
|
||||
#ifndef _LP_TOUCH_KEY_API_
|
||||
#define _LP_TOUCH_KEY_API_
|
||||
|
||||
#include "typedef.h"
|
||||
#include "asm/lpctmu_hw.h"
|
||||
|
||||
|
||||
enum CTMU_P2M_EVENT {
|
||||
CTMU_P2M_CH0_RES_EVENT = 0x50,
|
||||
CTMU_P2M_CH0_SHORT_KEY_EVENT,
|
||||
CTMU_P2M_CH0_LONG_KEY_EVENT,
|
||||
CTMU_P2M_CH0_HOLD_KEY_EVENT,
|
||||
CTMU_P2M_CH0_FALLING_EVENT,
|
||||
CTMU_P2M_CH0_RAISING_EVENT,
|
||||
|
||||
CTMU_P2M_CH1_RES_EVENT = 0x58,
|
||||
CTMU_P2M_CH1_SHORT_KEY_EVENT,
|
||||
CTMU_P2M_CH1_LONG_KEY_EVENT,
|
||||
CTMU_P2M_CH1_HOLD_KEY_EVENT,
|
||||
CTMU_P2M_CH1_FALLING_EVENT,
|
||||
CTMU_P2M_CH1_RAISING_EVENT,
|
||||
|
||||
CTMU_P2M_CH2_RES_EVENT = 0x60,
|
||||
CTMU_P2M_CH2_SHORT_KEY_EVENT,
|
||||
CTMU_P2M_CH2_LONG_KEY_EVENT,
|
||||
CTMU_P2M_CH2_HOLD_KEY_EVENT,
|
||||
CTMU_P2M_CH2_FALLING_EVENT,
|
||||
CTMU_P2M_CH2_RAISING_EVENT,
|
||||
|
||||
CTMU_P2M_CH3_RES_EVENT = 0x68,
|
||||
CTMU_P2M_CH3_SHORT_KEY_EVENT,
|
||||
CTMU_P2M_CH3_LONG_KEY_EVENT,
|
||||
CTMU_P2M_CH3_HOLD_KEY_EVENT,
|
||||
CTMU_P2M_CH3_FALLING_EVENT,
|
||||
CTMU_P2M_CH3_RAISING_EVENT,
|
||||
|
||||
CTMU_P2M_CH4_RES_EVENT = 0x70,
|
||||
CTMU_P2M_CH4_SHORT_KEY_EVENT,
|
||||
CTMU_P2M_CH4_LONG_KEY_EVENT,
|
||||
CTMU_P2M_CH4_HOLD_KEY_EVENT,
|
||||
CTMU_P2M_CH4_FALLING_EVENT,
|
||||
CTMU_P2M_CH4_RAISING_EVENT,
|
||||
|
||||
CTMU_P2M_EARTCH_IN_EVENT = 0x78,
|
||||
CTMU_P2M_EARTCH_OUT_EVENT,
|
||||
};
|
||||
|
||||
|
||||
enum LP_TOUCH_SOFTOFF_MODE {
|
||||
LP_TOUCH_SOFTOFF_MODE_LEGACY = 0, //普通关机
|
||||
LP_TOUCH_SOFTOFF_MODE_ADVANCE = 1, //带触摸关机
|
||||
};
|
||||
|
||||
enum touch_key_type {
|
||||
TOUCH_KEY_NULL,
|
||||
TOUCH_KEY_SHORT_CLICK,
|
||||
TOUCH_KEY_LONG_CLICK,
|
||||
TOUCH_KEY_HOLD_CLICK,
|
||||
};
|
||||
|
||||
|
||||
enum {
|
||||
TOUCH_KEY_EVENT_SLIDE_UP,
|
||||
TOUCH_KEY_EVENT_SLIDE_DOWN,
|
||||
TOUCH_KEY_EVENT_SLIDE_LEFT,
|
||||
TOUCH_KEY_EVENT_SLIDE_RIGHT,
|
||||
TOUCH_KEY_EVENT_MAX,
|
||||
};
|
||||
|
||||
|
||||
struct lp_touch_key_cfg {
|
||||
u8 enable;
|
||||
u8 wakeup_en;
|
||||
u8 key_value;
|
||||
u8 range_sensity;
|
||||
u16 algo_range_min;
|
||||
u16 algo_range_max;
|
||||
u16 algo_cfg0;
|
||||
u16 algo_cfg1;
|
||||
u16 algo_cfg2;
|
||||
};
|
||||
|
||||
struct lp_touch_key_platform_data {
|
||||
|
||||
u8 eartch_en;
|
||||
u8 eartch_ch;
|
||||
u8 eartch_ref_ch;
|
||||
u8 eartch_inear_ok;
|
||||
u8 eartch_last_state;
|
||||
u8 eartch_trim_flag;
|
||||
u16 eartch_trim_value;
|
||||
u16 eartch_soft_inear_val;
|
||||
u16 eartch_soft_outear_val;
|
||||
|
||||
|
||||
u8 slide_mode_en;
|
||||
u8 slide_mode_key_value;
|
||||
|
||||
u8 ldo_wkp_reset;
|
||||
u8 charge_online_reset;
|
||||
u8 charge_mode_keep_touch;
|
||||
u8 charge_enter_algo_reset;
|
||||
u8 charge_exit_algo_reset;
|
||||
|
||||
u8 click_cnt[LPCTMU_CHANNEL_SIZE];
|
||||
u8 last_key[LPCTMU_CHANNEL_SIZE];
|
||||
|
||||
u8 key_ch_msg_lock;
|
||||
u16 key_ch_msg_lock_timer;
|
||||
|
||||
u16 short_timer[LPCTMU_CHANNEL_SIZE];
|
||||
u16 long_timer[LPCTMU_CHANNEL_SIZE];
|
||||
u16 hold_timer[LPCTMU_CHANNEL_SIZE];
|
||||
|
||||
u16 short_click_check_time;
|
||||
u16 long_click_check_time;
|
||||
u16 hold_click_check_time;
|
||||
|
||||
u8 long_press_reset_enable;
|
||||
u16 long_press_reset_time;
|
||||
u16 softoff_wakeup_time;
|
||||
|
||||
struct lp_touch_key_cfg key[LPCTMU_CHANNEL_SIZE];
|
||||
|
||||
struct lpctmu_platform_data *lpctmu_cfg;
|
||||
};
|
||||
|
||||
|
||||
u32 lp_touch_key_power_on_status();
|
||||
|
||||
u32 lp_touch_key_alog_range_display(u8 *display_buf);
|
||||
|
||||
void lp_touch_key_init(struct lp_touch_key_platform_data *config);
|
||||
|
||||
void lp_touch_key_disable(void);
|
||||
|
||||
void lp_touch_key_enable(void);
|
||||
|
||||
void lp_touch_key_charge_mode_enter();
|
||||
|
||||
void lp_touch_key_charge_mode_exit();
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,20 @@
|
||||
#ifndef __LP_TOUCH_KEY_RANGE_ALGO_H__
|
||||
#define __LP_TOUCH_KEY_RANGE_ALGO_H__
|
||||
|
||||
|
||||
#include "typedef.h"
|
||||
|
||||
|
||||
void TouchRangeAlgo_Init(u8 ch, u16 min, u16 max);
|
||||
void TouchRangeAlgo_Update(u8 ch, u16 x);
|
||||
void TouchRangeAlgo_Reset(u8 ch, u16 min, u16 max);
|
||||
|
||||
u16 TouchRangeAlgo_GetRange(u8 ch, u8 *valid);
|
||||
void TouchRangeAlgo_SetRange(u8 ch, u16 range);
|
||||
|
||||
s32 TouchRangeAlgo_GetSigma(u8 ch);
|
||||
void TouchRangeAlgo_SetSigma(u8 ch, s32 sigma);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,14 @@
|
||||
#ifndef __LP_TOUCH_KEY_TOOL__
|
||||
#define __LP_TOUCH_KEY_TOOL__
|
||||
|
||||
#include "typedef.h"
|
||||
|
||||
|
||||
//spp
|
||||
int lp_touch_key_online_debug_init(void);
|
||||
int lp_touch_key_online_debug_send(u8 ch, u16 val);
|
||||
int lp_touch_key_online_debug_key_event_handle(u8 ch_index, void *e);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,77 @@
|
||||
#ifndef _LPCTMU_HW_H_
|
||||
#define _LPCTMU_HW_H_
|
||||
|
||||
#include "typedef.h"
|
||||
|
||||
|
||||
#define LPCTMU_CHANNEL_SIZE 5
|
||||
|
||||
|
||||
enum CTMU_M2P_CMD {
|
||||
REQUEST_LPCTMU_IRQ = 0x50,
|
||||
REQUEST_LPTMR_IRQ,
|
||||
RESET_IDENTIFY_ALGO,
|
||||
};
|
||||
|
||||
enum bt_arb_wl2ext_act {
|
||||
RF_PLL_EN = 1,
|
||||
RF_PLL_RN,
|
||||
RF_RX_LDO,
|
||||
RF_RX_EN,
|
||||
RF_TX_LDO,
|
||||
RF_TX_EN,
|
||||
EF_RX_TX_EN_XOR,
|
||||
};
|
||||
|
||||
enum lpctmu_ext_stop_sel {
|
||||
BT_SIG_ACT0,
|
||||
BT_SIG_ACT1,
|
||||
BT_SIG_ACT0_ACT1_XOR,
|
||||
BT_SIG_ACT0_ACT1_AND,
|
||||
};
|
||||
|
||||
struct lpctmu_ch_cfg {
|
||||
u8 enable;
|
||||
u8 wakeup_en;
|
||||
};
|
||||
|
||||
struct lpctmu_platform_data {
|
||||
u8 ext_stop_ch_en;
|
||||
u8 ext_stop_sel;
|
||||
u8 sample_window_time; //采样窗口时间 ms
|
||||
u8 sample_scan_time; //多久采样一次 ms
|
||||
u8 lowpower_sample_scan_time; //软关机下多久采样一次 ms
|
||||
u16 aim_vol_delta;
|
||||
u16 aim_charge_khz;
|
||||
struct lpctmu_ch_cfg ch[LPCTMU_CHANNEL_SIZE];
|
||||
};
|
||||
|
||||
#define LPCTMU_PLATFORM_DATA_BEGIN(data) \
|
||||
static struct lpctmu_platform_data data = {
|
||||
|
||||
#define LPCTMU_PLATFORM_DATA_END() \
|
||||
};
|
||||
|
||||
|
||||
void lpctmu_send_m2p_cmd(enum CTMU_M2P_CMD cmd);
|
||||
|
||||
void lpctmu_set_ana_hv_level(u8 level);
|
||||
|
||||
u8 lpctmu_get_ana_hv_level(void);
|
||||
|
||||
void lpctmu_set_ana_cur_level(u8 ch, u8 cur_level);
|
||||
|
||||
u8 lpctmu_get_ana_cur_level(u8 ch);
|
||||
|
||||
void lpctmu_init(struct lpctmu_platform_data *pdata);
|
||||
|
||||
void lpctmu_disable(void);
|
||||
|
||||
void lpctmu_enable(void);
|
||||
|
||||
u8 lpctmu_is_sf_keep(void);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@@ -0,0 +1,130 @@
|
||||
#ifndef _MCPWM_H_
|
||||
#define _MCPWM_H_
|
||||
|
||||
#include "typedef.h"
|
||||
|
||||
#define MCPWM_NUM_MAX 8
|
||||
#define MCPWM_CH_MAX 2
|
||||
#define MCPWM_TMR_BASE_ADDR (&JL_MCPWM->TMR0_CON)
|
||||
#define MCPWM_TMR_OFFSET (&JL_MCPWM->TMR1_CON - &JL_MCPWM->TMR0_CON)
|
||||
#define MCPWM_CH_BASE_ADDR (&JL_MCPWM->CH0_CON0)
|
||||
#define MCPWM_CH_OFFSET (&JL_MCPWM->CH1_CON0 - &JL_MCPWM->CH0_CON0)
|
||||
|
||||
//TMRx_CON reg
|
||||
#define MCPWM_TMR_INCF 15
|
||||
// #define MCPWM_TMR_RESERVE 14
|
||||
#define MCPWM_TMR_UFPND 13
|
||||
#define MCPWM_TMR_OFPN 12
|
||||
#define MCPWM_TMR_UFCLR 11
|
||||
#define MCPWM_TMR_OFCLR 10
|
||||
#define MCPWM_TMR_UFIE 9
|
||||
#define MCPWM_TMR_OFTE 8
|
||||
#define MCPWM_TMR_CKSRC 7
|
||||
#define MCPWM_TMR_CKPS 3 //4bit
|
||||
// #define MCPWM_TMR_RESERVE 2
|
||||
#define MCPWM_TMR_MODE 0 //2bit
|
||||
|
||||
//CHx_CON0 reg
|
||||
#define MCPWM_CH_DTCKPS 12 //4bit
|
||||
#define MCPWM_CH_DTPR 7 //5bit
|
||||
#define MCPWM_CH_DTEN 6
|
||||
#define MCPWM_CH_L_INV 5
|
||||
#define MCPWM_CH_H_INV 4
|
||||
#define MCPWM_CH_L_EN 3
|
||||
#define MCPWM_CH_H_EN 2
|
||||
#define MCPWM_CH_CMP_LD 0 //2bit
|
||||
|
||||
//CHx_CON1 reg
|
||||
#define MCPWM_CH_FPND 15
|
||||
#define MCPWM_CH_FCLR 14
|
||||
// #define MCPWM_CH_RESERVE 12 //2bit
|
||||
#define MCPWM_CH_INTEN 11
|
||||
#define MCPWM_CH_TMRSEL 8 //3bit
|
||||
// #define MCPWM_CH_reserve 5 //3bit
|
||||
#define MCPWM_CH_FPINEN 4
|
||||
#define MCPWM_CH_FPINAUTO 3
|
||||
#define MCPWM_CH_FPINSEL 0 //3bit
|
||||
|
||||
//FPIN_CON reg
|
||||
#define MCPWM_FPIN_EDGE 16 //8bit
|
||||
#define MCPWM_FPIN_FLT_EN 8 //8bit
|
||||
// #define MCPWM_CH_reserve 6 //2bit
|
||||
#define MCPWM_FPIN_FLT_PR 8 //5bit
|
||||
|
||||
//MCPWM_CON reg
|
||||
#define MCPWM_CON_CLK_EN 16
|
||||
#define MCPWM_CON_TMR_EN 8 //8bit
|
||||
#define MCPWM_CON_PWM_EN 0 //8bit2
|
||||
|
||||
|
||||
/* pwm通道选择 */
|
||||
typedef enum {
|
||||
MCPWM_CH0 = 0,
|
||||
MCPWM_CH1,
|
||||
} mcpwm_ch_type;
|
||||
|
||||
/* 对齐方式选择 */
|
||||
typedef enum {
|
||||
MCPWM_EDGE_ALIGNED, ///< 边沿对齐模式
|
||||
MCPWM_CENTER_ALIGNED, ///< 中心对齐模式
|
||||
} mcpwm_aligned_mode_type;
|
||||
|
||||
/* 故障保护触发边沿 */
|
||||
typedef enum {
|
||||
MCPWM_EDGE_FAILL = 0, //下降沿触发
|
||||
MCPWM_EDGE_RISE, //上升沿触发
|
||||
MCPWM_EDGE_DEFAULT = 0xff, //默认会忽略
|
||||
} mcpwm_edge;
|
||||
|
||||
/* MCPWM通道寄存器 */
|
||||
typedef struct _mcpwm_ch_reg {
|
||||
volatile u32 ch_con0;
|
||||
volatile u32 ch_con1;
|
||||
volatile u32 ch_cmph;
|
||||
volatile u32 ch_cmpl;
|
||||
} MCPWM_CHx_REG;
|
||||
|
||||
/* MCPWM TIMER寄存器 */
|
||||
typedef struct _mcpwm_timer_reg {
|
||||
volatile u32 tmr_con;
|
||||
volatile u32 tmr_cnt;
|
||||
volatile u32 tmr_pr;
|
||||
} MCPWM_TIMERx_REG;
|
||||
|
||||
|
||||
/* 初始化要用的参数结构体 */
|
||||
typedef void (*mcpwm_detect_irq_callback)(u32 ch); //回调函数
|
||||
struct mcpwm_config {
|
||||
mcpwm_ch_type ch; ///< 选择pwm通道号
|
||||
mcpwm_aligned_mode_type aligned_mode; ///< PWM对齐方式选择
|
||||
u32 frequency; ///< 初始共同频率，CH0, CH, CH2,,,,,,
|
||||
u16 duty; ///< 初始占空比，0~10000 对应 0%~100% 。每个通道可以有不同的占空比。互补模式的占空比体现在高引脚的波形上。
|
||||
u16 h_pin; ///< 一个通道的H引脚。
|
||||
u16 l_pin; ///< 一个通道的L引脚，不需要则填-1
|
||||
u8 complementary_en; ///< 该通道的两个引脚输出的波形。0: 同步， 1: 互补，互补波形的占空比体现在H引脚上
|
||||
u16 detect_port;
|
||||
mcpwm_edge edge;
|
||||
mcpwm_detect_irq_callback irq_cb;
|
||||
u16 irq_priority; //默认值优先级1
|
||||
};
|
||||
|
||||
struct mcpwm_info_t {
|
||||
MCPWM_CHx_REG *ch_reg;
|
||||
MCPWM_TIMERx_REG *timer_reg;
|
||||
struct mcpwm_config cfg;
|
||||
};
|
||||
|
||||
|
||||
int mcpwm_init(struct mcpwm_config *mcpwm_cfg);
|
||||
void mcpwm_deinit(int mcpwm_cfg_id);
|
||||
void mcpwm_start(int mcpwm_cfg_id);
|
||||
void mcpwm_pause(int mcpwm_cfg_id);
|
||||
void mcpwm_resume(int mcpwm_cfg_id);
|
||||
void mcpwm_set_frequency(int mcpwm_cfg_id, mcpwm_aligned_mode_type align, u32 frequency);
|
||||
void mcpwm_set_duty(int mcpwm_cfg_id, u16 duty);
|
||||
void mcpwm_fpnd_clr(u32 ch);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@@ -0,0 +1,29 @@
|
||||
#ifndef _PLCNT_DRV_H_
|
||||
#define _PLCNT_DRV_H_
|
||||
|
||||
|
||||
#define PLCNT_KEY_CH_MAX 3
|
||||
|
||||
struct touch_key_port {
|
||||
u16 press_delta; //按下判决的阈值
|
||||
u8 port; //触摸按键IO
|
||||
u8 key_value; //按键返回值
|
||||
};
|
||||
|
||||
struct touch_key_platform_data {
|
||||
u8 num; //触摸按键个数
|
||||
const struct touch_key_port *port_list;
|
||||
};
|
||||
|
||||
|
||||
/* =========== pclcnt API ============= */
|
||||
//plcnt 初始化
|
||||
int plcnt_init(void *_data);
|
||||
|
||||
//获取plcnt按键状态
|
||||
u8 get_plcnt_value(void);
|
||||
|
||||
|
||||
#endif /* _PLCNT_DRV_H_ */
|
||||
|
||||
|
||||
@@ -0,0 +1,34 @@
|
||||
#ifndef _IPC_SPIN_LOCK_H_
|
||||
#define _IPC_SPIN_LOCK_H_
|
||||
|
||||
#include "typedef.h"
|
||||
#include "gpio.h"
|
||||
|
||||
enum ipc_spin_lock_event {
|
||||
IPC_SPIN_LOCK_EVENT_USER0 = 0,//自定义事件名
|
||||
IPC_SPIN_LOCK_EVENT_USER1,
|
||||
IPC_SPIN_LOCK_EVENT_USER2,
|
||||
IPC_SPIN_LOCK_EVENT_USER3,
|
||||
IPC_SPIN_LOCK_EVENT_USER4,
|
||||
IPC_SPIN_LOCK_EVENT_USER5,
|
||||
IPC_SPIN_LOCK_EVENT_USER6,
|
||||
IPC_SPIN_LOCK_EVENT_USER7,
|
||||
IPC_SPIN_LOCK_EVENT_USER8,
|
||||
IPC_SPIN_LOCK_EVENT_USER9,
|
||||
IPC_SPIN_LOCK_EVENT_USER10,
|
||||
IPC_SPIN_LOCK_EVENT_USER11,
|
||||
IPC_SPIN_LOCK_EVENT_CBUF, //12
|
||||
IPC_SPIN_LOCK_EVENT_UART, //13
|
||||
IPC_SPIN_LOCK_EVENT_PMU, //14
|
||||
IPC_SPIN_LOCK_EVENT_P11_IIC,//15
|
||||
IPC_SPIN_LOCK_EVENT_MAX,
|
||||
|
||||
|
||||
};
|
||||
|
||||
void ipc_spin_lock_init();
|
||||
|
||||
void ipc_spin_lock(enum ipc_spin_lock_event event);//0~15
|
||||
void ipc_spin_unlock(enum ipc_spin_lock_event event);//0~15
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,311 @@
|
||||
#ifndef __LP_IPC_H__
|
||||
#define __LP_IPC_H__
|
||||
|
||||
//=================================消息格式========================================
|
||||
|
||||
//消息buf大小
|
||||
#define MAX_POOL 512
|
||||
|
||||
//消息类型
|
||||
enum {
|
||||
MSG_ACK = 0,
|
||||
MSG_TEST = 1,
|
||||
MSG_COMMOM = 2,
|
||||
MSG_CTMU = 3,
|
||||
MSG_SENSOR = 4,
|
||||
MSG_VAD = 5,
|
||||
MSG_RTC = 6,
|
||||
MSG_APP = 7,
|
||||
};
|
||||
|
||||
|
||||
|
||||
//消息函数返回值
|
||||
enum {
|
||||
MSG_NO_ERROR = 0, //读取/发送消息成功
|
||||
MSG_NO_MSG = -1, //未读取到消息
|
||||
MSG_BUF_ERROR = -2, //读/写消息格式不对
|
||||
MSG_BUF_READ_OVER = -3, //读消息溢出，传的参数长度不对
|
||||
MSG_BUF_WRITE_OVER = -4, //写消息会溢出
|
||||
};
|
||||
|
||||
//消息头格式
|
||||
#define MSG_HEADER_BYTE_LEN 4
|
||||
#define MSG_HEADER_BIT_LEN (MSG_HEADER_BYTE_LEN*8)
|
||||
#define MSG_HEADER_ALL_BIT ((1L<<MSG_HEADER_BIT_LEN) - 1)
|
||||
|
||||
#define MSG_INDEX_BIT 15
|
||||
#define MSG_ACK_BIT 1
|
||||
|
||||
#define MSG_TYPE_BIT_LEN 8
|
||||
#define MSG_PARAM_BIT_LEN (MSG_HEADER_BYTE_LEN*8-MSG_TYPE_BIT_LEN-MSG_INDEX_BIT-MSG_ACK_BIT)
|
||||
|
||||
struct lp_msg_head {
|
||||
u32 type :
|
||||
MSG_TYPE_BIT_LEN;
|
||||
u32 ack :
|
||||
MSG_ACK_BIT;
|
||||
u32 index :
|
||||
MSG_INDEX_BIT;
|
||||
u32 len :
|
||||
MSG_PARAM_BIT_LEN;
|
||||
} __attribute__((packed));
|
||||
|
||||
//消息队列
|
||||
typedef struct LP_Q {
|
||||
u16 in; //写位置
|
||||
u16 out; //读位置
|
||||
u16 count; //有效数据
|
||||
u16 size; //buf大小
|
||||
u32 start; //buf起址
|
||||
u32 ack_flag; //应答标记
|
||||
} LP_Q;
|
||||
|
||||
enum {
|
||||
LP_BUF_NO_ERR = 0,
|
||||
LP_BUF_READ_NOT_ENOUGH_DATA = -1, //buf里数据不够读
|
||||
LP_BUF_READ_NO_DATA = -2, //buf里面没有数据
|
||||
LP_BUF_WRITE_OVER = -3, //写数据超过了buf大小
|
||||
};
|
||||
|
||||
//用户消息对应处理
|
||||
struct lp_msg_handler {
|
||||
void (*handler)(void *, u8 *, u32);
|
||||
void *priv;
|
||||
u8 type;
|
||||
} __attribute__((packed));
|
||||
|
||||
//===========================================================================//
|
||||
// P2M MESSAGE TABLE //
|
||||
//===========================================================================//
|
||||
#define P11_RAM_ACCESS(x) (*(volatile u8 *)(x))
|
||||
#define M2P_MESSAGE_ACCESS(x) P11_RAM_ACCESS(M2P_MESSAGE_RAM_BEGIN + x)
|
||||
#define P2M_MESSAGE_ACCESS(x) P11_RAM_ACCESS(P2M_MESSAGE_RAM_BEGIN + x)
|
||||
|
||||
//==================power=============================
|
||||
#define P2M_WKUP_SRC P2M_MESSAGE_ACCESS(0)
|
||||
#define P2M_WKUP_P_PND P2M_MESSAGE_ACCESS(1)
|
||||
#define P2M_WKUP_N_PND P2M_MESSAGE_ACCESS(2)
|
||||
#define P2M_AWKUP_P_PND P2M_MESSAGE_ACCESS(3)
|
||||
#define P2M_AWKUP_N_PND P2M_MESSAGE_ACCESS(4)
|
||||
#define P2M_WKUP_RTC P2M_MESSAGE_ACCESS(5)
|
||||
|
||||
//==================system===========================
|
||||
#define P2M_MESSAGE_BANK_ADR_L P2M_MESSAGE_ACCESS(15)
|
||||
#define P2M_MESSAGE_BANK_ADR_H P2M_MESSAGE_ACCESS(16)
|
||||
#define P2M_MESSAGE_BANK_INDEX P2M_MESSAGE_ACCESS(17)
|
||||
#define P2M_MESSAGE_BANK_ACK P2M_MESSAGE_ACCESS(18)
|
||||
#define P2M_P11_HEAP_BEGIN_ADDR_L P2M_MESSAGE_ACCESS(19)
|
||||
#define P2M_P11_HEAP_BEGIN_ADDR_H P2M_MESSAGE_ACCESS(20)
|
||||
#define P2M_P11_HEAP_SIZE_L P2M_MESSAGE_ACCESS(21)
|
||||
#define P2M_P11_HEAP_SIZE_H P2M_MESSAGE_ACCESS(22)
|
||||
#define P2M_REPLY_SYNC_CMD P2M_MESSAGE_ACCESS(23)
|
||||
#define P2M_CBUF_ADDR0 P2M_MESSAGE_ACCESS(24)
|
||||
#define P2M_CBUF_ADDR1 P2M_MESSAGE_ACCESS(25)
|
||||
#define P2M_CBUF_ADDR2 P2M_MESSAGE_ACCESS(26)
|
||||
#define P2M_CBUF_ADDR3 P2M_MESSAGE_ACCESS(27)
|
||||
#define P2M_CBUF1_ADDR0 P2M_MESSAGE_ACCESS(28)
|
||||
#define P2M_CBUF1_ADDR1 P2M_MESSAGE_ACCESS(29)
|
||||
#define P2M_CBUF1_ADDR2 P2M_MESSAGE_ACCESS(30)
|
||||
#define P2M_CBUF1_ADDR3 P2M_MESSAGE_ACCESS(31)
|
||||
|
||||
//==================clock===========================
|
||||
#define P2M_BTOSC_OK P2M_MESSAGE_ACCESS(35)
|
||||
|
||||
//==================lpctmu===========================
|
||||
#define P2M_CTMU_CMD_ACK P2M_MESSAGE_ACCESS(39)
|
||||
#define P2M_CTMU_KEY_EVENT P2M_MESSAGE_ACCESS(40)
|
||||
#define P2M_CTMU_KEY_CNT P2M_MESSAGE_ACCESS(41)
|
||||
#define P2M_CTMU_KEY_STATE P2M_MESSAGE_ACCESS(42)
|
||||
#define P2M_CTMU_EARTCH_EVENT P2M_MESSAGE_ACCESS(43)
|
||||
|
||||
#define P2M_MASSAGE_CTMU_CH0_L_RES 44
|
||||
#define P2M_MASSAGE_CTMU_CH0_H_RES 45
|
||||
#define P2M_CTMU_CH0_L_RES P2M_MESSAGE_ACCESS(44)
|
||||
#define P2M_CTMU_CH0_H_RES P2M_MESSAGE_ACCESS(45)
|
||||
#define P2M_CTMU_CH1_L_RES P2M_MESSAGE_ACCESS(46)
|
||||
#define P2M_CTMU_CH1_H_RES P2M_MESSAGE_ACCESS(47)
|
||||
#define P2M_CTMU_CH2_L_RES P2M_MESSAGE_ACCESS(48)
|
||||
#define P2M_CTMU_CH2_H_RES P2M_MESSAGE_ACCESS(49)
|
||||
#define P2M_CTMU_CH3_L_RES P2M_MESSAGE_ACCESS(50)
|
||||
#define P2M_CTMU_CH3_H_RES P2M_MESSAGE_ACCESS(51)
|
||||
#define P2M_CTMU_CH4_L_RES P2M_MESSAGE_ACCESS(52)
|
||||
#define P2M_CTMU_CH4_H_RES P2M_MESSAGE_ACCESS(53)
|
||||
|
||||
#define P2M_CTMU_EARTCH_L_IIR_VALUE P2M_MESSAGE_ACCESS(54)
|
||||
#define P2M_CTMU_EARTCH_H_IIR_VALUE P2M_MESSAGE_ACCESS(55)
|
||||
#define P2M_CTMU_EARTCH_L_DIFF_VALUE P2M_MESSAGE_ACCESS(56)
|
||||
#define P2M_CTMU_EARTCH_H_DIFF_VALUE P2M_MESSAGE_ACCESS(57)
|
||||
|
||||
|
||||
|
||||
//===========================================================================//
|
||||
// M2P MESSAGE TABLE //
|
||||
//===========================================================================//
|
||||
//==================power=============================
|
||||
#define M2P_LRC_PRD M2P_MESSAGE_ACCESS(0)
|
||||
#define M2P_WDVDD M2P_MESSAGE_ACCESS(1)
|
||||
#define M2P_LRC_FEQ0 M2P_MESSAGE_ACCESS(2)
|
||||
#define M2P_LRC_FEQ1 M2P_MESSAGE_ACCESS(3)
|
||||
#define M2P_LRC_FEQ2 M2P_MESSAGE_ACCESS(4)
|
||||
#define M2P_LRC_FEQ3 M2P_MESSAGE_ACCESS(5)
|
||||
#define M2P_VDDIO_KEEP M2P_MESSAGE_ACCESS(6)
|
||||
#define M2P_LRC_KEEP M2P_MESSAGE_ACCESS(7)
|
||||
#define M2P_RCH_FEQ_L M2P_MESSAGE_ACCESS(8)
|
||||
#define M2P_RCH_FEQ_H M2P_MESSAGE_ACCESS(9)
|
||||
#define M2P_MEM_CONTROL M2P_MESSAGE_ACCESS(10)
|
||||
#define M2P_BTOSC_KEEP M2P_MESSAGE_ACCESS(11)
|
||||
#define M2P_CTMU_KEEP M2P_MESSAGE_ACCESS(12)
|
||||
#define M2P_RTC_KEEP M2P_MESSAGE_ACCESS(13)
|
||||
#define M2P_SF_MODE M2P_MESSAGE_ACCESS(14)
|
||||
#define M2P_DCV_MODE M2P_MESSAGE_ACCESS(15)
|
||||
#define M2P_LIGHT_PDOWN_DVDD_VOL M2P_MESSAGE_ACCESS(16)
|
||||
#define M2P_LRC24M_MODE M2P_MESSAGE_ACCESS(17)
|
||||
|
||||
//==================system===========================
|
||||
#define M2P_SYNC_CMD M2P_MESSAGE_ACCESS(25)
|
||||
#define M2P_WDT_SYNC M2P_MESSAGE_ACCESS(26)
|
||||
|
||||
//==================clock===========================
|
||||
#define M2P_LRC24M_CFG0 M2P_MESSAGE_ACCESS(35)
|
||||
#define M2P_LRC24M_CFG1 M2P_MESSAGE_ACCESS(36)
|
||||
#define M2P_BTOSC_CFG0 M2P_MESSAGE_ACCESS(37)
|
||||
#define M2P_BTOSC_CFG1 M2P_MESSAGE_ACCESS(38)
|
||||
|
||||
#define M2P_LRC24M_FEQ0 M2P_MESSAGE_ACCESS(39)
|
||||
#define M2P_LRC24M_FEQ1 M2P_MESSAGE_ACCESS(40)
|
||||
#define M2P_LRC24M_FEQ2 M2P_MESSAGE_ACCESS(41)
|
||||
#define M2P_LRC24M_FEQ3 M2P_MESSAGE_ACCESS(42)
|
||||
|
||||
//==================lpctmu===========================
|
||||
/*触摸所有通道配置*/
|
||||
#define M2P_CTMU_CMD M2P_MESSAGE_ACCESS(50)
|
||||
#define M2P_CTMU_CH_ENABLE M2P_MESSAGE_ACCESS(51)
|
||||
#define M2P_CTMU_CH_WAKEUP_EN M2P_MESSAGE_ACCESS(52)
|
||||
#define M2P_CTMU_CH_DEBUG M2P_MESSAGE_ACCESS(53)
|
||||
#define M2P_CTMU_CH_CFG M2P_MESSAGE_ACCESS(54)
|
||||
#define M2P_CTMU_EARTCH_CH M2P_MESSAGE_ACCESS(55)
|
||||
|
||||
|
||||
#define M2P_CTMU_SCAN_TIME M2P_MESSAGE_ACCESS(56)
|
||||
#define M2P_CTMU_LOWPOER_SCAN_TIME M2P_MESSAGE_ACCESS(57)
|
||||
#define M2P_CTMU_LONG_KEY_EVENT_TIMEL M2P_MESSAGE_ACCESS(58)
|
||||
#define M2P_CTMU_LONG_KEY_EVENT_TIMEH M2P_MESSAGE_ACCESS(59)
|
||||
#define M2P_CTMU_HOLD_KEY_EVENT_TIMEL M2P_MESSAGE_ACCESS(60)
|
||||
#define M2P_CTMU_HOLD_KEY_EVENT_TIMEH M2P_MESSAGE_ACCESS(61)
|
||||
#define M2P_CTMU_SOFTOFF_WAKEUP_TIMEL M2P_MESSAGE_ACCESS(62)
|
||||
#define M2P_CTMU_SOFTOFF_WAKEUP_TIMEH M2P_MESSAGE_ACCESS(63)
|
||||
#define M2P_CTMU_LONG_PRESS_RESET_TIMEL M2P_MESSAGE_ACCESS(64)//长按复位
|
||||
#define M2P_CTMU_LONG_PRESS_RESET_TIMEH M2P_MESSAGE_ACCESS(65)//长按复位
|
||||
|
||||
#define M2P_CTMU_INEAR_VALUE_L M2P_MESSAGE_ACCESS(66)
|
||||
#define M2P_CTMU_INEAR_VALUE_H M2P_MESSAGE_ACCESS(67)
|
||||
#define M2P_CTMU_OUTEAR_VALUE_L M2P_MESSAGE_ACCESS(68)
|
||||
#define M2P_CTMU_OUTEAR_VALUE_H M2P_MESSAGE_ACCESS(69)
|
||||
#define M2P_CTMU_EARTCH_TRIM_VALUE_L M2P_MESSAGE_ACCESS(70)
|
||||
#define M2P_CTMU_EARTCH_TRIM_VALUE_H M2P_MESSAGE_ACCESS(71)
|
||||
|
||||
#define M2P_MASSAGE_CTMU_CH0_CFG0L 72
|
||||
#define M2P_MASSAGE_CTMU_CH0_CFG0H 73
|
||||
#define M2P_MASSAGE_CTMU_CH0_CFG1L 74
|
||||
#define M2P_MASSAGE_CTMU_CH0_CFG1H 75
|
||||
#define M2P_MASSAGE_CTMU_CH0_CFG2L 76
|
||||
#define M2P_MASSAGE_CTMU_CH0_CFG2H 77
|
||||
|
||||
#define M2P_CTMU_CH0_CFG0L M2P_MESSAGE_ACCESS((M2P_MASSAGE_CTMU_CH0_CFG0L + 0 * 8))
|
||||
#define M2P_CTMU_CH0_CFG0H M2P_MESSAGE_ACCESS((M2P_MASSAGE_CTMU_CH0_CFG0H + 0 * 8))
|
||||
#define M2P_CTMU_CH0_CFG1L M2P_MESSAGE_ACCESS((M2P_MASSAGE_CTMU_CH0_CFG1L + 0 * 8))
|
||||
#define M2P_CTMU_CH0_CFG1H M2P_MESSAGE_ACCESS((M2P_MASSAGE_CTMU_CH0_CFG1H + 0 * 8))
|
||||
#define M2P_CTMU_CH0_CFG2L M2P_MESSAGE_ACCESS((M2P_MASSAGE_CTMU_CH0_CFG2L + 0 * 8))
|
||||
#define M2P_CTMU_CH0_CFG2H M2P_MESSAGE_ACCESS((M2P_MASSAGE_CTMU_CH0_CFG2H + 0 * 8))
|
||||
|
||||
#define M2P_CTMU_CH1_CFG0L M2P_MESSAGE_ACCESS((M2P_MASSAGE_CTMU_CH0_CFG0L + 1 * 8))
|
||||
#define M2P_CTMU_CH1_CFG0H M2P_MESSAGE_ACCESS((M2P_MASSAGE_CTMU_CH0_CFG0H + 1 * 8))
|
||||
#define M2P_CTMU_CH1_CFG1L M2P_MESSAGE_ACCESS((M2P_MASSAGE_CTMU_CH0_CFG1L + 1 * 8))
|
||||
#define M2P_CTMU_CH1_CFG1H M2P_MESSAGE_ACCESS((M2P_MASSAGE_CTMU_CH0_CFG1H + 1 * 8))
|
||||
#define M2P_CTMU_CH1_CFG2L M2P_MESSAGE_ACCESS((M2P_MASSAGE_CTMU_CH0_CFG2L + 1 * 8))
|
||||
#define M2P_CTMU_CH1_CFG2H M2P_MESSAGE_ACCESS((M2P_MASSAGE_CTMU_CH0_CFG2H + 1 * 8))
|
||||
|
||||
#define M2P_CTMU_CH2_CFG0L M2P_MESSAGE_ACCESS((M2P_MASSAGE_CTMU_CH0_CFG0L + 2 * 8))
|
||||
#define M2P_CTMU_CH2_CFG0H M2P_MESSAGE_ACCESS((M2P_MASSAGE_CTMU_CH0_CFG0H + 2 * 8))
|
||||
#define M2P_CTMU_CH2_CFG1L M2P_MESSAGE_ACCESS((M2P_MASSAGE_CTMU_CH0_CFG1L + 2 * 8))
|
||||
#define M2P_CTMU_CH2_CFG1H M2P_MESSAGE_ACCESS((M2P_MASSAGE_CTMU_CH0_CFG1H + 2 * 8))
|
||||
#define M2P_CTMU_CH2_CFG2L M2P_MESSAGE_ACCESS((M2P_MASSAGE_CTMU_CH0_CFG2L + 2 * 8))
|
||||
#define M2P_CTMU_CH2_CFG2H M2P_MESSAGE_ACCESS((M2P_MASSAGE_CTMU_CH0_CFG2H + 2 * 8))
|
||||
|
||||
#define M2P_CTMU_CH3_CFG0L M2P_MESSAGE_ACCESS((M2P_MASSAGE_CTMU_CH0_CFG0L + 3 * 8))
|
||||
#define M2P_CTMU_CH3_CFG0H M2P_MESSAGE_ACCESS((M2P_MASSAGE_CTMU_CH0_CFG0H + 3 * 8))
|
||||
#define M2P_CTMU_CH3_CFG1L M2P_MESSAGE_ACCESS((M2P_MASSAGE_CTMU_CH0_CFG1L + 3 * 8))
|
||||
#define M2P_CTMU_CH3_CFG1H M2P_MESSAGE_ACCESS((M2P_MASSAGE_CTMU_CH0_CFG1H + 3 * 8))
|
||||
#define M2P_CTMU_CH3_CFG2L M2P_MESSAGE_ACCESS((M2P_MASSAGE_CTMU_CH0_CFG2L + 3 * 8))
|
||||
#define M2P_CTMU_CH3_CFG2H M2P_MESSAGE_ACCESS((M2P_MASSAGE_CTMU_CH0_CFG2H + 3 * 8))
|
||||
|
||||
#define M2P_CTMU_CH4_CFG0L M2P_MESSAGE_ACCESS((M2P_MASSAGE_CTMU_CH0_CFG0L + 4 * 8))
|
||||
#define M2P_CTMU_CH4_CFG0H M2P_MESSAGE_ACCESS((M2P_MASSAGE_CTMU_CH0_CFG0H + 4 * 8))
|
||||
#define M2P_CTMU_CH4_CFG1L M2P_MESSAGE_ACCESS((M2P_MASSAGE_CTMU_CH0_CFG1L + 4 * 8))
|
||||
#define M2P_CTMU_CH4_CFG1H M2P_MESSAGE_ACCESS((M2P_MASSAGE_CTMU_CH0_CFG1H + 4 * 8))
|
||||
#define M2P_CTMU_CH4_CFG2L M2P_MESSAGE_ACCESS((M2P_MASSAGE_CTMU_CH0_CFG2L + 4 * 8))
|
||||
#define M2P_CTMU_CH4_CFG2H M2P_MESSAGE_ACCESS((M2P_MASSAGE_CTMU_CH0_CFG2H + 4 * 8))//0x56
|
||||
|
||||
/*
|
||||
* Must Sync to P11 code
|
||||
*/
|
||||
enum {
|
||||
M2P_LP_INDEX = 0,
|
||||
M2P_PF_INDEX,
|
||||
M2P_LLP_INDEX,
|
||||
M2P_P33_INDEX,
|
||||
M2P_SF_INDEX,
|
||||
M2P_CTMU_INDEX,
|
||||
M2P_CCMD_INDEX, //common cmd
|
||||
M2P_VAD_INDEX,
|
||||
M2P_USER_INDEX,
|
||||
M2P_WDT_INDEX,
|
||||
M2P_SYNC_INDEX,
|
||||
M2P_APP_INDEX,
|
||||
|
||||
};
|
||||
|
||||
enum {
|
||||
P2M_LP_INDEX = 0,
|
||||
P2M_PF_INDEX,
|
||||
P2M_LLP_INDEX,
|
||||
P2M_WK_INDEX,
|
||||
P2M_WDT_INDEX,
|
||||
P2M_LP_INDEX2,
|
||||
P2M_CTMU_INDEX,
|
||||
P2M_CTMU_POWUP,
|
||||
P2M_REPLY_CCMD_INDEX, //reply common cmd
|
||||
P2M_VAD_INDEX,
|
||||
P2M_USER_INDEX,
|
||||
P2M_BANK_INDEX,
|
||||
P2M_REPLY_SYNC_INDEX,
|
||||
P2M_APP_INDEX,
|
||||
};
|
||||
|
||||
enum {
|
||||
CLOSE_P33_INTERRUPT = 1,
|
||||
OPEN_P33_INTERRUPT,
|
||||
LOWPOWER_PREPARE,
|
||||
M2P_SPIN_LOCK,
|
||||
M2P_SPIN_UNLOCK,
|
||||
P2M_SPIN_LOCK,
|
||||
P2M_SPIN_UNLOCK,
|
||||
|
||||
};
|
||||
|
||||
#include "m2p_msg.h"
|
||||
#include "p2m_msg.h"
|
||||
|
||||
|
||||
void msys_to_p11_sync_cmd(u8 cmd);
|
||||
|
||||
void lp_ipc_init();
|
||||
|
||||
void lp_lock();
|
||||
|
||||
void lp_unlock();
|
||||
|
||||
void config_post_ack_flag(u32 enable);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,36 @@
|
||||
#ifndef __M2P_MSG_H__
|
||||
#define __M2P_MSG_H__
|
||||
|
||||
#define REGISTER_M2P_MSG_HANDLER(pri, _type, fn) \
|
||||
const struct lp_msg_handler _##fn SEC_USED(.m2p_msg_handler)= { \
|
||||
.handler = fn, \
|
||||
.priv = pri, \
|
||||
.type = _type, \
|
||||
}
|
||||
|
||||
extern struct lp_msg_handler m2p_msg_handler_begin[];
|
||||
extern struct lp_msg_handler m2p_msg_handler_end[];
|
||||
|
||||
#define list_for_each_m2p_msg_handler(p) \
|
||||
for (p = m2p_msg_handler_begin; p < m2p_msg_handler_end; p++)
|
||||
|
||||
int m2p_get_msg(struct lp_msg_head *head, void *msg, u32 len);
|
||||
int m2p_post_msg(u32 type, u32 ack, const void *msg, u32 len);
|
||||
|
||||
void msys_to_p11_sys_cmd(u8 cmd);
|
||||
|
||||
int m2p_msg_hdl();
|
||||
|
||||
u32 msys_ack_p11(u32 index);
|
||||
|
||||
|
||||
/*
|
||||
* function:主系统向P11发送消息，往消息池丢数据
|
||||
*
|
||||
* param name: null
|
||||
* param argc：参数个数
|
||||
*/
|
||||
|
||||
int task_post_msg2p11(char *name, int argc, ...);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,24 @@
|
||||
#ifndef __P11_API_H__
|
||||
#define __P11_API_H__
|
||||
|
||||
#define P11_P2M_INT_IE P11_SYSTEM->P2M_INT_IE
|
||||
#define P11_M2P_INT_IE P11_SYSTEM->M2P_INT_IE
|
||||
#define P11_M2P_INT_SET P11_SYSTEM->M2P_INT_SET
|
||||
#define P11_P2M_INT_SET P11_SYSTEM->P2M_INT_SET
|
||||
#define P11_P2M_INT_CLR P11_SYSTEM->P2M_INT_CLR
|
||||
#define P11_P2M_INT_PND P11_SYSTEM->P2M_INT_PND
|
||||
|
||||
enum P11_SYS_CLK_TABLE {
|
||||
P11_SYS_CLK_RC16M = 0,
|
||||
P11_SYS_CLK_RC250K,
|
||||
P11_SYS_CLK_LRC_OSC,
|
||||
P11_SYS_CLK_BTOSC_24M,
|
||||
P11_SYS_CLK_BTOSC_48M,
|
||||
P11_SYS_CLK_LRC24M,
|
||||
P11_SYS_CLK_CLK_X2,
|
||||
P11_SYS_CLK_TEST,
|
||||
};
|
||||
|
||||
void p11_sys_clk_sel(u32 sel);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,180 @@
|
||||
//*********************************************************************************//
|
||||
// Module name : csfr.h //
|
||||
// Description : q32small core sfr define //
|
||||
// By Designer : zequan_liu //
|
||||
// Dat changed : //
|
||||
//*********************************************************************************//
|
||||
|
||||
#ifndef __P11_Q32S_CSFR__
|
||||
#define __P11_Q32S_CSFR__
|
||||
|
||||
#define __RW volatile // read write
|
||||
#define __RO volatile const // only read
|
||||
#define __WO volatile // only write
|
||||
|
||||
#define __u8 unsigned int // u8 to u32 special for struct
|
||||
#define __u16 unsigned int // u16 to u32 special for struct
|
||||
#define __u32 unsigned int
|
||||
|
||||
#define CPU_CORE_NUM 1
|
||||
|
||||
//---------------------------------------------//
|
||||
// q32small define
|
||||
//---------------------------------------------//
|
||||
|
||||
#ifdef PMU_SYSTEM
|
||||
#define p11_q32s_sfr_base 0x00a000
|
||||
#define p11_q32s_sfr_offset 0x000000 // multi_core used
|
||||
#else
|
||||
#define p11_q32s_sfr_base 0xf2a000
|
||||
#define p11_q32s_sfr_offset 0x000000 // multi_core used
|
||||
#endif
|
||||
|
||||
#define p11_q32s_cpu_base (p11_q32s_sfr_base + 0x00)
|
||||
#define p11_q32s_mpu_base (p11_q32s_sfr_base + 0x80)
|
||||
|
||||
#define p11_q32s(n) ((JL_TypeDef_p11_q32s *)(p11_q32s_sfr_base + p11_q32s_sfr_offset*n))
|
||||
#define p11_q32s_mpu(n) ((JL_TypeDef_p11_q32s_MPU *)(p11_q32s_mpu_base + p11_q32s_sfr_offset*n))
|
||||
|
||||
//---------------------------------------------//
|
||||
// q32small core sfr
|
||||
//---------------------------------------------//
|
||||
|
||||
typedef struct {
|
||||
/* 00 */ __RO __u32 DR00;
|
||||
/* 01 */ __RO __u32 DR01;
|
||||
/* 02 */ __RO __u32 DR02;
|
||||
/* 03 */ __RO __u32 DR03;
|
||||
/* 04 */ __RO __u32 DR04;
|
||||
/* 05 */ __RO __u32 DR05;
|
||||
/* 06 */ __RO __u32 DR06;
|
||||
/* 07 */ __RO __u32 DR07;
|
||||
/* 08 */ __RO __u32 DR08;
|
||||
/* 09 */ __RO __u32 DR09;
|
||||
/* 0a */ __RO __u32 DR10;
|
||||
/* 0b */ __RO __u32 DR11;
|
||||
/* 0c */ __RO __u32 DR12;
|
||||
/* 0d */ __RO __u32 DR13;
|
||||
/* 0e */ __RO __u32 DR14;
|
||||
/* 0f */ __RO __u32 DR15;
|
||||
|
||||
/* 10 */ __RO __u32 RETI;
|
||||
/* 11 */ __RO __u32 RETE;
|
||||
/* 12 */ __RO __u32 RETX;
|
||||
/* 13 */ __RO __u32 RETS;
|
||||
/* 14 */ __RO __u32 SR04;
|
||||
/* 15 */ __RO __u32 PSR;
|
||||
/* 16 */ __RO __u32 CNUM;
|
||||
/* 17 */ __RO __u32 SR07;
|
||||
/* 18 */ __RO __u32 SR08;
|
||||
/* 19 */ __RO __u32 SR09;
|
||||
/* 1a */ __RO __u32 SR10;
|
||||
/* 1b */ __RO __u32 ICFG;
|
||||
/* 1c */ __RO __u32 USP;
|
||||
/* 1d */ __RO __u32 SSP;
|
||||
/* 1e */ __RO __u32 SP;
|
||||
/* 1f */ __RO __u32 PCRS;
|
||||
|
||||
/* 20 */ __RW __u32 BPCON;
|
||||
/* 21 */ __RW __u32 BSP;
|
||||
/* 22 */ __RW __u32 BP0;
|
||||
/* 23 */ __RW __u32 BP1;
|
||||
/* 24 */ __RW __u32 BP2;
|
||||
/* 25 */ __RW __u32 BP3;
|
||||
/* 26 */ __WO __u32 CMD_PAUSE;
|
||||
/* */ __RO __u32 REV_30_26[0x30 - 0x26 - 1];
|
||||
|
||||
/* 30 */ __RW __u32 PMU_CON0;
|
||||
/* 31 */ __RW __u32 PMU_CON1;
|
||||
/* 32 */ __RW __u32 RST_ADDR;
|
||||
/* */ __RO __u32 REV_3b_30[0x3b - 0x32 - 1];
|
||||
/* 3b */ __RW __u8 TTMR_CON;
|
||||
/* 3c */ __RW __u32 TTMR_CNT;
|
||||
/* 3d */ __RW __u32 TTMR_PRD;
|
||||
/* 3e */ __RW __u32 BANK_CON;
|
||||
/* 3f */ __RW __u32 BANK_NUM;
|
||||
|
||||
/* 40 */ __RW __u32 ICFG00;
|
||||
/* 41 */ __RW __u32 ICFG01;
|
||||
/* 42 */ __RW __u32 ICFG02;
|
||||
/* 43 */ __RW __u32 ICFG03;
|
||||
/* 44 */ __RW __u32 ICFG04;
|
||||
/* 45 */ __RW __u32 ICFG05;
|
||||
/* 46 */ __RW __u32 ICFG06;
|
||||
/* 47 */ __RW __u32 ICFG07;
|
||||
/* 48 */ __RW __u32 ICFG08;
|
||||
/* 49 */ __RW __u32 ICFG09;
|
||||
/* 4a */ __RW __u32 ICFG10;
|
||||
/* 4b */ __RW __u32 ICFG11;
|
||||
/* 4c */ __RW __u32 ICFG12;
|
||||
/* 4d */ __RW __u32 ICFG13;
|
||||
/* 4e */ __RW __u32 ICFG14;
|
||||
/* 4f */ __RW __u32 ICFG15;
|
||||
|
||||
/* 50 */ __RW __u32 ICFG16;
|
||||
/* 51 */ __RW __u32 ICFG17;
|
||||
/* 52 */ __RW __u32 ICFG18;
|
||||
/* 53 */ __RW __u32 ICFG19;
|
||||
/* 54 */ __RW __u32 ICFG20;
|
||||
/* 55 */ __RW __u32 ICFG21;
|
||||
/* 56 */ __RW __u32 ICFG22;
|
||||
/* 57 */ __RW __u32 ICFG23;
|
||||
/* 58 */ __RW __u32 ICFG24;
|
||||
/* 59 */ __RW __u32 ICFG25;
|
||||
/* 5a */ __RW __u32 ICFG26;
|
||||
/* 5b */ __RW __u32 ICFG27;
|
||||
/* 5c */ __RW __u32 ICFG28;
|
||||
/* 5d */ __RW __u32 ICFG29;
|
||||
/* 5e */ __RW __u32 ICFG30;
|
||||
/* 5f */ __RW __u32 ICFG31;
|
||||
|
||||
/* 60 */ __RO __u32 IPND0;
|
||||
/* 61 */ __RO __u32 IPND1;
|
||||
/* 62 */ __RO __u32 IPND2;
|
||||
/* 63 */ __RO __u32 IPND3;
|
||||
/* 64 */ __RO __u32 IPND4;
|
||||
/* 65 */ __RO __u32 IPND5;
|
||||
/* 66 */ __RO __u32 IPND6;
|
||||
/* 67 */ __RO __u32 IPND7;
|
||||
/* 68 */ __WO __u32 ILAT_SET;
|
||||
/* 69 */ __WO __u32 ILAT_CLR;
|
||||
/* 6a */ __RW __u32 IPMASK;
|
||||
/* 6b */ __RW __u32 GIEMASK;
|
||||
/* 6c */ __RW __u32 IWKUP_NUM;
|
||||
/* */ __RO __u32 REV_70_6c[0x70 - 0x6c - 1];
|
||||
|
||||
/* 70 */ __RW __u32 ETM_CON;
|
||||
/* 71 */ __RO __u32 ETM_PC0;
|
||||
/* 72 */ __RO __u32 ETM_PC1;
|
||||
/* 73 */ __RO __u32 ETM_PC2;
|
||||
/* 74 */ __RO __u32 ETM_PC3;
|
||||
/* 75 */ __RW __u32 WP0_ADRH;
|
||||
/* 76 */ __RW __u32 WP0_ADRL;
|
||||
/* 77 */ __RW __u32 WP0_DATH;
|
||||
/* 78 */ __RW __u32 WP0_DATL;
|
||||
/* 79 */ __RW __u32 WP0_PC;
|
||||
|
||||
/* */ __RO __u32 REV_80_79[0x80 - 0x79 - 1];
|
||||
/* 80 */ __RW __u32 EMU_CON;
|
||||
/* 81 */ __RW __u32 EMU_MSG;
|
||||
/* 82 */ __RO __u32 EMU_SSP_H;
|
||||
/* 83 */ __RO __u32 EMU_SSP_L;
|
||||
/* 84 */ __RO __u32 EMU_USP_H;
|
||||
/* 85 */ __RO __u32 EMU_USP_L;
|
||||
} JL_TypeDef_p11_q32s;
|
||||
|
||||
#undef __RW
|
||||
#undef __RO
|
||||
#undef __WO
|
||||
|
||||
#undef __u8
|
||||
#undef __u16
|
||||
#undef __u32
|
||||
|
||||
#endif
|
||||
|
||||
//*********************************************************************************//
|
||||
// //
|
||||
// end of this module //
|
||||
// //
|
||||
//*********************************************************************************//
|
||||
@@ -0,0 +1,34 @@
|
||||
//===============================================================================//
|
||||
//
|
||||
// input IO define
|
||||
//
|
||||
//===============================================================================//
|
||||
#define P11_PB0_IN 1
|
||||
#define P11_PB1_IN 2
|
||||
#define P11_PB2_IN 3
|
||||
#define P11_PB3_IN 4
|
||||
#define P11_PB4_IN 5
|
||||
#define P11_PB5_IN 6
|
||||
#define P11_PB6_IN 7
|
||||
#define P11_PB7_IN 8
|
||||
#define P11_PB8_IN 9
|
||||
|
||||
//===============================================================================//
|
||||
//
|
||||
// function input select sfr
|
||||
//
|
||||
//===============================================================================//
|
||||
typedef struct {
|
||||
__RW __u8 P11_FI_GP_ICH0;
|
||||
__RW __u8 P11_FI_GP_ICH1;
|
||||
__RW __u8 P11_FI_GP_ICH2;
|
||||
__RW __u8 P11_FI_UART0_RX;
|
||||
__RW __u8 P11_FI_UART1_RX;
|
||||
__RW __u8 P11_FI_SPI_DI;
|
||||
__RW __u8 P11_FI_IIC_SCL;
|
||||
__RW __u8 P11_FI_IIC_SDA;
|
||||
} P11_IMAP_TypeDef;
|
||||
|
||||
#define P11_IMAP_BASE (p11_sfr_base + map_adr(0x17, 0x00))
|
||||
#define P11_IMAP ((P11_IMAP_TypeDef *)P11_IMAP_BASE)
|
||||
|
||||
@@ -0,0 +1,35 @@
|
||||
//===============================================================================//
|
||||
//
|
||||
// output function define
|
||||
//
|
||||
//===============================================================================//
|
||||
#define P11_FO_GP_OCH0 ((0 << 2)|BIT(1))
|
||||
#define P11_FO_GP_OCH1 ((1 << 2)|BIT(1))
|
||||
#define P11_FO_GP_OCH2 ((2 << 2)|BIT(1))
|
||||
#define P11_FO_UART0_TX ((3 << 2)|BIT(1)|BIT(0))
|
||||
#define P11_FO_UART1_TX ((4 << 2)|BIT(1)|BIT(0))
|
||||
#define P11_FO_SPI_CLK ((5 << 2)|BIT(1)|BIT(0))
|
||||
#define P11_FO_SPI_DO ((6 << 2)|BIT(1)|BIT(0))
|
||||
#define P11_FO_IIC_SCL ((7 << 2)|BIT(1)|BIT(0))
|
||||
#define P11_FO_IIC_SDA ((8 << 2)|BIT(1)|BIT(0))
|
||||
|
||||
//===============================================================================//
|
||||
//
|
||||
// IO output select sfr
|
||||
//
|
||||
//===============================================================================//
|
||||
typedef struct {
|
||||
__RW __u8 P11_PB0_OUT;
|
||||
__RW __u8 P11_PB1_OUT;
|
||||
__RW __u8 P11_PB2_OUT;
|
||||
__RW __u8 P11_PB3_OUT;
|
||||
__RW __u8 P11_PB4_OUT;
|
||||
__RW __u8 P11_PB5_OUT;
|
||||
__RW __u8 P11_PB6_OUT;
|
||||
__RW __u8 P11_PB7_OUT;
|
||||
__RW __u8 P11_PB8_OUT;
|
||||
} P11_OMAP_TypeDef;
|
||||
|
||||
#define P11_OMAP_BASE (p11_sfr_base + map_adr(0x16, 0x00))
|
||||
#define P11_OMAP ((P11_OMAP_TypeDef *)P11_OMAP_BASE)
|
||||
|
||||
@@ -0,0 +1,39 @@
|
||||
#ifndef __P11_MMAP_H__
|
||||
#define __P11_MMAP_H__
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
#ifdef PMU_SYSTEM
|
||||
#define P11_RAM_BASE 0
|
||||
#else
|
||||
#define P11_RAM_BASE 0xF20000
|
||||
#endif
|
||||
#define P11_RAM_BEGIN (P11_RAM_BASE)
|
||||
#define P11_RAM_SIZE (0x8000)
|
||||
#define P11_RAM_END (P11_RAM_BASE+P11_RAM_SIZE)
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
#define MSYS_POFF_RAM_END P11_RAM_END
|
||||
#define MSYS_POFF_RAM_SIZE 0x20
|
||||
#define MSYS_POFF_RAM_BEGIN (MSYS_POFF_RAM_END - MSYS_POFF_RAM_SIZE)
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
#define M2P_MESSAGE_END MSYS_POFF_RAM_BEGIN
|
||||
#define M2P_MESSAGE_SIZE 0xe0
|
||||
#define M2P_MESSAGE_RAM_BEGIN (M2P_MESSAGE_END - M2P_MESSAGE_SIZE)
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
#define P2M_MESSAGE_END M2P_MESSAGE_RAM_BEGIN
|
||||
#define P2M_MESSAGE_SIZE 0x40
|
||||
#define P2M_MESSAGE_RAM_BEGIN (P2M_MESSAGE_END - P2M_MESSAGE_SIZE)
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
#define P11_RAM0_END P2M_MESSAGE_RAM_BEGIN
|
||||
#define P11_RAM0_BEGIN (P11_RAM_BASE+P11_ISR_SIZE)
|
||||
#define P11_RAM0_SIZE (P11_RAM0_END - P11_RAM0_BEGIN)
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
#define P11_ISR_END P11_RAM0_BEGIN
|
||||
#define P11_ISR_SIZE 0x80
|
||||
#define P11_ISR_BEGIN P11_RAM_BASE
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,331 @@
|
||||
#ifndef __P11_SFR_H__
|
||||
#define __P11_SFR_H__
|
||||
|
||||
//===============================================================================//
|
||||
//
|
||||
// sfr define
|
||||
//
|
||||
//===============================================================================//
|
||||
|
||||
#ifdef PMU_SYSTEM
|
||||
#define p11_base 0x000000
|
||||
#define p11_ram_base p11_base
|
||||
#define p11_sfr_base 0x00a000
|
||||
#else
|
||||
#define p11_base 0xf20000
|
||||
#define p11_ram_base p11_base
|
||||
#define p11_sfr_base 0xf2a000
|
||||
#endif
|
||||
|
||||
#define __RW volatile // read write
|
||||
#define __RO volatile const // only read
|
||||
#define __WO volatile // only write
|
||||
|
||||
#define __u8 unsigned int // u8 to u32 special for struct
|
||||
#define __u16 unsigned int // u16 to u32 special for struct
|
||||
#define __u32 unsigned int
|
||||
|
||||
#define __s8(x) char(x); char(reserved_1_##x); char(reserved_2_##x); char(reserved_3_##x)
|
||||
#define __s16(x) short(x); short(reserved_1_##x)
|
||||
#define __s32(x) int(x)
|
||||
|
||||
#define map_adr(grp, adr) ((64 * grp + adr) * 4) // grp(0x0-0xff), adr(0x0-0x3f)
|
||||
#define P11_ACCESS(x) (*(volatile u32 *)(p11_base + x))
|
||||
#define P11_RAM(x) (*(volatile u32 *)(p11_ram_base + x))
|
||||
|
||||
//===============================================================================//
|
||||
//
|
||||
// sfr address define
|
||||
//
|
||||
//===============================================================================//
|
||||
|
||||
//............. 0x0000 - 0x03ff............ for cpu
|
||||
|
||||
// #include ../core/csfr.h
|
||||
|
||||
//............. 0x0400 - 0x04ff............ for clock
|
||||
typedef struct {
|
||||
__RW __u32 PWR_CON;
|
||||
__RW __u32 RST_SRC;
|
||||
__RW __u32 WKUP_EN;
|
||||
__RW __u32 WKUP_SRC;
|
||||
__RW __u32 SYS_DIV;
|
||||
__RW __u32 CLK_CON0;
|
||||
__RW __u32 CLK_CON1;
|
||||
__RW __u32 CLK_CON2;
|
||||
__RW __u32 XOSC_CFG0;
|
||||
__RW __u32 XOSC_CFG1;
|
||||
__RW __u32 LRC24M_CFG0;
|
||||
__RW __u32 CLKCFG_CFG0;
|
||||
} P11_CLOCK_TypeDef;
|
||||
|
||||
#define P11_CLOCK_BASE (p11_sfr_base + map_adr(0x04, 0x00))
|
||||
#define P11_CLOCK ((P11_CLOCK_TypeDef *)P11_CLOCK_BASE)
|
||||
|
||||
#define P11_PWR_CON P11_CLOCK->PWR_CON
|
||||
#define P11_CLK_CON0 P11_CLOCK->CLK_CON0
|
||||
|
||||
|
||||
//............. 0x0600 - 0x06ff............ for system
|
||||
typedef struct {
|
||||
__RW __u32 P2M_INT_IE;
|
||||
__RW __u32 P2M_INT_SET;
|
||||
__RW __u32 P2M_INT_CLR;
|
||||
__RO __u32 P2M_INT_PND;
|
||||
__RW __u32 P2M_CLK_CON0;
|
||||
__RW __u32 M2P_INT_IE;
|
||||
__RW __u32 M2P_INT_SET;
|
||||
__RW __u32 M2P_INT_CLR;
|
||||
__RO __u32 M2P_INT_PND;
|
||||
__RW __u32 P11_SYS_CON0;
|
||||
__RW __u32 P11_SYS_CON1;
|
||||
__RW __u32 PMU_KEY;
|
||||
} P11_SYSTEM_TypeDef;
|
||||
|
||||
#define P11_SYSTEM_BASE (p11_sfr_base + map_adr(0x06, 0x00))
|
||||
#define P11_SYSTEM ((P11_SYSTEM_TypeDef *)P11_SYSTEM_BASE)
|
||||
|
||||
//............. 0x0700 - 0x07ff............ for mbist
|
||||
typedef struct {
|
||||
__RW __u32 CON;
|
||||
__RW __u32 SEL;
|
||||
__RW __u32 BEG;
|
||||
__RW __u32 END;
|
||||
__RW __u32 DAT_VLD0;
|
||||
__RW __u32 DAT_VLD1;
|
||||
__RW __u32 DAT_VLD2;
|
||||
__RW __u32 DAT_VLD3;
|
||||
__RO __u32 ROM_CRC;
|
||||
__RW __u32 MCFG0_RF1P;
|
||||
__RW __u32 MCFG0_RF2P;
|
||||
__RW __u32 MCFG0_RM1P;
|
||||
__RW __u32 MCFG0_RM2P;
|
||||
__RW __u32 MCFG0_VROM;
|
||||
__RW __u32 MCFG0_CON[3];
|
||||
} P11_MBIST_TypeDef;
|
||||
|
||||
#define P11_MBIST_BASE (p11_sfr_base + map_adr(0x07, 0x00))
|
||||
#define P11_MBIST ((P11_MBIST_TypeDef *)P11_MBIST_BASE)
|
||||
|
||||
//............. 0x0800 - 0x08ff............ for watch dog
|
||||
typedef struct {
|
||||
__RW __u32 CON;
|
||||
__RW __u32 KEY;
|
||||
__RW __u32 DUMMY;
|
||||
} P11_WDT_TypeDef;
|
||||
|
||||
#define P11_WDT_BASE (p11_sfr_base + map_adr(0x08, 0x00))
|
||||
#define P11_WDT ((P11_WDT_TypeDef *)P11_WDT_BASE)
|
||||
|
||||
#define P11_SIM_END P11_WDT->DUMMY
|
||||
|
||||
//............. 0x0900 - 0x0cff............ for lp timer
|
||||
typedef struct {
|
||||
__RW __u32 CON0;
|
||||
__RW __u32 CON1;
|
||||
__RW __u32 CON2;
|
||||
__RW __u32 PRD;
|
||||
__RW __u32 RSC;
|
||||
__RO __u32 CNT;
|
||||
} P11_LPTMR_TypeDef;
|
||||
|
||||
#define P11_LPTMR0_BASE (p11_sfr_base + map_adr(0x09, 0x00))
|
||||
#define P11_LPTMR1_BASE (p11_sfr_base + map_adr(0x0a, 0x00))
|
||||
#define P11_LPTMR2_BASE (p11_sfr_base + map_adr(0x0b, 0x00))
|
||||
#define P11_LPTMR3_BASE (p11_sfr_base + map_adr(0x0c, 0x00))
|
||||
|
||||
#define P11_LPTMR0 ((P11_LPTMR_TypeDef *)P11_LPTMR0_BASE)
|
||||
#define P11_LPTMR1 ((P11_LPTMR_TypeDef *)P11_LPTMR1_BASE)
|
||||
#define P11_LPTMR2 ((P11_LPTMR_TypeDef *)P11_LPTMR2_BASE)
|
||||
#define P11_LPTMR3 ((P11_LPTMR_TypeDef *)P11_LPTMR3_BASE)
|
||||
|
||||
//............. 0x0d00 - 0x0dff............ for irflt
|
||||
typedef struct {
|
||||
__RW __u32 CON;
|
||||
} P11_IRFLT_TypeDef;
|
||||
|
||||
#define P11_IRFLT_BASE (p11_sfr_base + map_adr(0x0d, 0x00))
|
||||
#define P11_IRFLT ((P11_IRFLT_TypeDef *)P11_IRFLT_BASE)
|
||||
|
||||
//............. 0x0e00 - 0x0eff............ for spi
|
||||
typedef struct {
|
||||
__RW __u32 CON;
|
||||
__RW __u32 BAUD;
|
||||
__RW __u32 BUF;
|
||||
__WO __u32 ADR;
|
||||
__RW __u32 CNT;
|
||||
__RW __u32 CON1;
|
||||
} P11_SPI_TypeDef;
|
||||
|
||||
#define P11_SPI_BASE (p11_sfr_base + map_adr(0x0e, 0x00))
|
||||
#define P11_SPI ((P11_SPI_TypeDef *)P11_SPI_BASE)
|
||||
|
||||
//............. 0x0f00 - 0x10ff............ for uart
|
||||
typedef struct {
|
||||
__RW __u16 CON0;
|
||||
__RW __u16 CON1;
|
||||
__RW __u16 CON2;
|
||||
__RW __u16 BAUD;
|
||||
__RW __u8 BUF;
|
||||
__RW __u32 OTCNT;
|
||||
//__RW __u32 TXADR;
|
||||
//__WO __u16 TXCNT;
|
||||
//__RW __u32 RXSADR;
|
||||
//__RW __u32 RXEADR;
|
||||
//__RW __u32 RXCNT;
|
||||
//__RO __u16 HRXCNT;
|
||||
//__RO __u16 RX_ERR_CNT;
|
||||
} P11_UART_TypeDef;
|
||||
|
||||
#define P11_UART0_BASE (p11_sfr_base + map_adr(0x0f, 0x00))
|
||||
#define P11_UART1_BASE (p11_sfr_base + map_adr(0x10, 0x00))
|
||||
|
||||
#define P11_UART0 ((P11_UART_TypeDef *)P11_UART0_BASE)
|
||||
#define P11_UART1 ((P11_UART_TypeDef *)P11_UART1_BASE)
|
||||
|
||||
//............. 0x1100 - 0x11ff............ for iic
|
||||
typedef struct {
|
||||
__RW __u32 CON ;
|
||||
__RW __u32 PND ;
|
||||
__RW __u32 TX_BUF ;
|
||||
__RW __u32 TASK ;
|
||||
__RO __u32 RX_BUF ;
|
||||
__RW __u32 ADDR ;
|
||||
__RW __u32 BAUD ;
|
||||
__RW __u32 TSU ;
|
||||
__RW __u32 THD ;
|
||||
__RO __u32 DBG ;
|
||||
} P11_IIC_TypeDef;
|
||||
|
||||
#define P11_IIC_BASE (p11_sfr_base + map_adr(0x11, 0x00))
|
||||
#define P11_IIC ((P11_IIC_TypeDef *)P11_IIC_BASE)
|
||||
|
||||
//............. 0x1200 - 0x12ff............ for port
|
||||
typedef struct {
|
||||
__RW __u32 OCH_CON0 ;
|
||||
__RW __u32 ICH_CON0 ;
|
||||
__RW __u32 P33_PORT ;
|
||||
__RW __u32 PB_SEL ;
|
||||
__RO __u32 PB_IN ;
|
||||
__RW __u32 PB_OUT ;
|
||||
__RW __u32 PB_DIR ;
|
||||
__RW __u32 PB_DIE ;
|
||||
__RW __u32 PB_DIEH ;
|
||||
__RW __u32 PB_PU0 ;
|
||||
__RW __u32 PB_PU1 ;
|
||||
__RW __u32 PB_PD0 ;
|
||||
__RW __u32 PB_PD1 ;
|
||||
__RW __u32 PB_HD0 ;
|
||||
__RW __u32 PB_HD1 ;
|
||||
__RW __u32 PB_SPL ;
|
||||
} P11_PORT_TypeDef;
|
||||
|
||||
#define P11_PORT_BASE (p11_sfr_base + map_adr(0x12, 0x00))
|
||||
#define P11_PORT ((P11_PORT_TypeDef *)P11_PORT_BASE)
|
||||
|
||||
//............. 0x1300 - 0x14ff............ for lp ctmu
|
||||
typedef struct {
|
||||
__RW __u32 CON0 ;
|
||||
__RW __u32 CHEN ;
|
||||
__RW __u32 CNUM ;
|
||||
__RW __u32 PPRD ;
|
||||
__RW __u32 DPRD ;
|
||||
__RW __u32 ECON ;
|
||||
__RW __u32 EXEN ;
|
||||
__RW __u32 CHIS ;
|
||||
__RW __u32 CLKC ;
|
||||
__WO __u32 WCON ;
|
||||
__RW __u32 ANA0 ;
|
||||
__RW __u32 ANA1 ;
|
||||
__RO __u32 RES ;
|
||||
__RW __u32 DMA_START_ADR;
|
||||
__RW __u32 DMA_HALF_ADR;
|
||||
__RW __u32 DMA_END_ADR;
|
||||
__RW __u32 DMA_CON;
|
||||
__RW __u32 MSG_CON;
|
||||
__RO __u32 DMA_WADR;
|
||||
__RW __u32 SLEEP_CON;
|
||||
} P11_LPCTM_TypeDef;
|
||||
|
||||
#define P11_LPCTM0_BASE (p11_sfr_base + map_adr(0x13, 0x00))
|
||||
#define P11_LPCTM0 ((P11_LPCTM_TypeDef *)P11_LPCTM0_BASE)
|
||||
|
||||
// #define P11_LPCTM1_BASE (p11_sfr_base + map_adr(0x14, 0x00))
|
||||
// #define P11_LPCTM1 ((P11_LPCTM_TypeDef *)P11_LPCTM1_BASE)
|
||||
|
||||
|
||||
//............. 0x1500 - 0x15ff............ for lpvad
|
||||
typedef struct {
|
||||
__RW __u32 VAD_CON;
|
||||
__RW __u32 VAD_ACON0;
|
||||
__RW __u32 VAD_ACON1;
|
||||
__RW __u32 AVAD_CON;
|
||||
__RW __u32 AVAD_DATA;
|
||||
__RW __u32 DVAD_CON0;
|
||||
__RW __u32 DVAD_CON1;
|
||||
__RW __u32 DMA_BADR;
|
||||
__RW __u32 DMA_LEN;
|
||||
__RW __u32 DMA_HPTR;
|
||||
__RW __u32 DMA_SPTR;
|
||||
__RW __u32 DMA_SPN;
|
||||
__RW __u32 DMA_SHN;
|
||||
} P11_LPVAD_TypeDef;
|
||||
|
||||
#define P11_LPVAD_BASE (p11_sfr_base + map_adr(0x15, 0x00))
|
||||
#define P11_LPVAD ((P11_LPVAD_TypeDef *)P11_LPVAD_BASE)
|
||||
|
||||
//............. 0x1600 - 0x17ff............ for crossbar
|
||||
#include "p11_io_omap.h"
|
||||
#include "p11_io_imap.h"
|
||||
|
||||
//............. 0x1800 - 0x19ff............ for gp timer
|
||||
typedef struct {
|
||||
__RW __u32 CON;
|
||||
__RW __u32 CNT;
|
||||
__RW __u32 PRD;
|
||||
__RW __u32 PWM;
|
||||
__RW __u32 IRFLT;
|
||||
} P11_GPTMR_TypeDef;
|
||||
|
||||
#define P11_GPTMR0_BASE (p11_sfr_base + map_adr(0x18, 0x00))
|
||||
#define P11_GPTMR1_BASE (p11_sfr_base + map_adr(0x18, 0x05))
|
||||
|
||||
#define P11_GPTMR0 ((P11_GPTMR_TypeDef *)P11_GPTMR0_BASE)
|
||||
#define P11_GPTMR1 ((P11_GPTMR_TypeDef *)P11_GPTMR1_BASE)
|
||||
|
||||
//............. 0x1a00 - 0x1aff............ for NFC
|
||||
typedef struct {
|
||||
__RW __u32 CON0;
|
||||
__RW __u32 CON1;
|
||||
__RW __u32 CON2;
|
||||
__RW __u32 CON3;
|
||||
__RW __u32 BUF0;
|
||||
__RW __u32 BUF1;
|
||||
__RW __u32 BUF2;
|
||||
__RW __u32 BUF3;
|
||||
} P11_NFC_TypeDef;
|
||||
|
||||
#define P11_NFC_BASE (p11_sfr_base + map_adr(0x1a, 0x00))
|
||||
#define P11_NFC ((P11_NFC_TypeDef *)P11_NFC_BASE)
|
||||
|
||||
|
||||
//............. 0x1b00 - 0x1bff............ for RESLOCK
|
||||
typedef struct {
|
||||
__RW __u32 LOCK[16];
|
||||
} P11_RESLOCK_TypeDef;
|
||||
|
||||
#define P11_RESLOCK_BASE (p11_sfr_base + map_adr(0x1b,0x00))
|
||||
#define P11_RESLOCK ((P11_RESLOCK_TypeDef *)P11_RESLOCK_BASE)
|
||||
|
||||
|
||||
//............. 0x1c00 - 0x1cff............ for lp_gpcnt0
|
||||
typedef struct {
|
||||
__RW __u32 CON;
|
||||
__RO __u32 NUM;
|
||||
} P11_GPCNT_TypeDef;
|
||||
|
||||
#define P11_GPCNT0_BASE (p11_sfr_base + map_adr(0x1c, 0x00))
|
||||
#define P11_GPCNT0 ((P11_GPCNT_TypeDef *)P11_GPCNT0_BASE)
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,25 @@
|
||||
#ifndef __P2M_MSG_H__
|
||||
#define __P2M_MSG_H__
|
||||
|
||||
|
||||
#define REGISTER_P2M_MSG_HANDLER(pri, _type, fn) \
|
||||
const struct lp_msg_handler _##fn SEC_USED(.p2m_msg_handler)= { \
|
||||
.handler = fn, \
|
||||
.priv = pri,\
|
||||
.type = _type, \
|
||||
}
|
||||
|
||||
extern struct lp_msg_handler p2m_msg_handler_begin[];
|
||||
extern struct lp_msg_handler p2m_msg_handler_end[];
|
||||
|
||||
#define list_for_each_p2m_msg_handler(p) \
|
||||
for (p = p2m_msg_handler_begin; p < p2m_msg_handler_end; p++)
|
||||
|
||||
int p2m_get_msg(struct lp_msg_head *head, void *msg, u32 len);
|
||||
int p2m_post_msg(u32 type, u32 ack, const void *msg, u32 len);
|
||||
|
||||
int p2m_msg_hdl();
|
||||
|
||||
u32 set_p2m_ack_flag(u32 index);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,74 @@
|
||||
#ifndef __CHARGE_HW_H__
|
||||
#define __CHARGE_HW_H__
|
||||
/************************P3_ANA_MFIX*****************************/
|
||||
#define PMU_MFIXI_SET_1(en) p33_fast_access(P3_ANA_MFIX, BIT(1), en)
|
||||
|
||||
/************************P3_CHG_CON0*****************************/
|
||||
#define CHARGE_EN(en) p33_fast_access(P3_CHG_CON0, BIT(0), en)
|
||||
|
||||
#define CHGGO_EN(en) p33_fast_access(P3_CHG_CON0, BIT(1), en)
|
||||
|
||||
#define IS_CHARGE_EN() ((P33_CON_GET(P3_CHG_CON0) & BIT(0)) ? 1: 0 )
|
||||
|
||||
#define CHG_HV_MODE(mode) p33_fast_access(P3_CHG_CON0, BIT(2), mode)
|
||||
|
||||
#define CHG_TRICKLE_EN(en) p33_fast_access(P3_CHG_CON0, BIT(3), en)
|
||||
|
||||
#define CHG_CCLOOP_EN(en) p33_fast_access(P3_CHG_CON0, BIT(4), en)
|
||||
|
||||
#define CHG_VILOOP_EN(en) p33_fast_access(P3_CHG_CON0, BIT(5), en)
|
||||
|
||||
#define CHG_VILOOP2_EN(en) p33_fast_access(P3_CHG_CON0, BIT(6), en)
|
||||
|
||||
#define CHG_VINLOOP_SLT(sel) p33_fast_access(P3_CHG_CON0, BIT(7), sel)
|
||||
|
||||
/************************P3_CHG_CON1*****************************/
|
||||
#define CHARGE_mA_SEL(a) P33_CON_SET(P3_CHG_CON1, 0, 4, a)
|
||||
|
||||
/************************P3_CHG_CON2*****************************/
|
||||
#define CHARGE_FULL_V_SEL(a) P33_CON_SET(P3_CHG_CON2, 4, 4, a)
|
||||
|
||||
/************************P3_CHG_CON3*****************************/
|
||||
#define CHARGE_FOLLOWC_SLT(en) p33_fast_access(P3_CHG_CON3, BIT(3), en)
|
||||
|
||||
enum {
|
||||
CHARGE_DET_VOL_365V,
|
||||
CHARGE_DET_VOL_375V,
|
||||
CHARGE_DET_VOL_385V,
|
||||
CHARGE_DET_VOL_395V,
|
||||
};
|
||||
#define CHARGE_DET_VOL(a) P33_CON_SET(P3_CHG_CON3, 1, 2, a)
|
||||
|
||||
#define CHARGE_DET_EN(en) p33_fast_access(P3_CHG_CON3, BIT(0), en)
|
||||
|
||||
/************************P3_CHG_CON4*****************************/
|
||||
#define CHGI_TRIM_SEL(a) P33_CON_SET(P3_CHG_CON4, 0, 4, a)
|
||||
|
||||
/************************P3_VPWR_CON0*****************************/
|
||||
#define L5V_IO_MODE(a) p33_fast_access(P3_VPWR_CON0, BIT(2), a)
|
||||
|
||||
#define IS_L5V_LOAD_EN() ((P33_CON_GET(P3_VPWR_CON0) & BIT(0)) ? 1: 0)
|
||||
|
||||
#define L5V_LOAD_EN(a) p33_fast_access(P3_VPWR_CON0, BIT(0), a)
|
||||
|
||||
/************************P3_VPWR_CON1*****************************/
|
||||
#define L5V_RES_DET_S_SEL(a) P33_CON_SET(P3_VPWR_CON1, 0, 2, a)
|
||||
|
||||
#define GET_L5V_RES_DET_S_SEL() (P33_CON_GET(P3_VPWR_CON1) & 0x03)
|
||||
|
||||
/************************P3_AWKUP_LEVEL*****************************/
|
||||
#define VBAT_DET_FILTER_GET() ((P33_CON_GET(P3_AWKUP_LEVEL) & BIT(2)) ? 1: 0)
|
||||
|
||||
#define LVCMP_DET_FILTER_GET() ((P33_CON_GET(P3_AWKUP_LEVEL) & BIT(1)) ? 1: 0)
|
||||
|
||||
#define LDO5V_DET_FILTER_GET() ((P33_CON_GET(P3_AWKUP_LEVEL) & BIT(0)) ? 1: 0)
|
||||
|
||||
/************************P3_ANA_READ*****************************/
|
||||
#define VBAT_DET_GET() ((P33_CON_GET(P3_ANA_READ) & BIT(0)) ? 1: 0 )
|
||||
|
||||
#define LVCMP_DET_GET() ((P33_CON_GET(P3_ANA_READ) & BIT(1)) ? 1: 0 )
|
||||
|
||||
#define LDO5V_DET_GET() ((P33_CON_GET(P3_ANA_READ) & BIT(2)) ? 1: 0 )
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,70 @@
|
||||
#ifndef __P33_ACCESS_H__
|
||||
#define __P33_ACCESS_H__
|
||||
|
||||
//
|
||||
//
|
||||
// for p33 access
|
||||
//
|
||||
//
|
||||
//
|
||||
/**************************************************************/
|
||||
|
||||
//ROM
|
||||
u8 p33_buf(u8 buf);
|
||||
|
||||
#define p33_xor_1byte(addr, data0) (*((volatile u8 *)&addr + 0x300*4) = data0); asm volatile ("csync")
|
||||
//#define p33_xor_1byte(addr, data0) (*((volatile u8 *)&addr + 0x300*4) = data0)
|
||||
// #define p33_xor_1byte(addr, data0) addr ^= (data0)
|
||||
|
||||
#define p33_or_1byte(addr, data0) (*((volatile u8 *)&addr + 0x200*4) = data0); asm volatile ("csync")
|
||||
//#define p33_or_1byte(addr, data0) (*((volatile u8 *)&addr + 0x200*4) = data0)
|
||||
// #define p33_or_1byte(addr, data0) addr |= (data0)
|
||||
|
||||
#define p33_and_1byte(addr, data0) (*((volatile u8 *)&addr + 0x100*4) = (data0)); asm volatile ("csync")
|
||||
//#define p33_and_1byte(addr, data0) (*((volatile u8 *)&addr + 0x100*4) = (data0))
|
||||
//#define p33_and_1byte(addr, data0) addr &= (data0)
|
||||
|
||||
// void p33_tx_1byte(u16 addr, u8 data0);
|
||||
#define p33_tx_1byte(addr, data0) addr = data0
|
||||
|
||||
// u8 p33_rx_1byte(u16 addr);
|
||||
#define p33_rx_1byte(addr) addr
|
||||
|
||||
#define P33_CON_SET(sfr, start, len, data) (sfr = (sfr & ~((~(0xff << (len))) << (start))) | \
|
||||
(((data) & (~(0xff << (len)))) << (start)))
|
||||
|
||||
#define P33_CON_GET(sfr) (sfr)
|
||||
|
||||
#if 1
|
||||
|
||||
#define p33_fast_access(reg, data, en) \
|
||||
{ \
|
||||
if (en) { \
|
||||
p33_or_1byte(reg, (data)); \
|
||||
} else { \
|
||||
p33_and_1byte(reg, (u8)~(data)); \
|
||||
} \
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
#define p33_fast_access(reg, data, en) \
|
||||
{ \
|
||||
if (en) { \
|
||||
reg |= (data); \
|
||||
} else { \
|
||||
reg &= ~(data); \
|
||||
} \
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,248 @@
|
||||
#ifndef __P33_API_H__
|
||||
#define __P33_API_H__
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
// vol
|
||||
//
|
||||
//
|
||||
//
|
||||
/****************************************************************/
|
||||
|
||||
enum DVDD_VOL {
|
||||
DVDD_VOL_0840MV = 0,
|
||||
DVDD_VOL_0870MV,
|
||||
DVDD_VOL_0900MV,
|
||||
DVDD_VOL_0930MV,
|
||||
DVDD_VOL_0960MV,
|
||||
DVDD_VOL_0990MV,
|
||||
DVDD_VOL_1020MV,
|
||||
DVDD_VOL_1050MV,
|
||||
DVDD_VOL_1080MV,
|
||||
DVDD_VOL_1110MV,
|
||||
DVDD_VOL_1140MV,
|
||||
DVDD_VOL_1170MV,
|
||||
DVDD_VOL_1200MV,
|
||||
DVDD_VOL_1230MV,
|
||||
DVDD_VOL_1260MV,
|
||||
DVDD_VOL_1290MV,
|
||||
};
|
||||
|
||||
/*enum DVDD2_VOL {*/
|
||||
/*};*/
|
||||
|
||||
/*enum RVDD_VOL {*/
|
||||
/*};*/
|
||||
|
||||
/*enum RVDD2_VOL {*/
|
||||
/*};*/
|
||||
|
||||
/*enum BTVDD_VOL {*/
|
||||
/*};*/
|
||||
|
||||
enum DCVDD_VOL {
|
||||
DCVDD_VOL_1000MV = 0,
|
||||
DCVDD_VOL_1050MV,
|
||||
DCVDD_VOL_1100MV,
|
||||
DCVDD_VOL_1150MV,
|
||||
DCVDD_VOL_1200MV,
|
||||
DCVDD_VOL_1250MV,
|
||||
DCVDD_VOL_1300MV,
|
||||
DCVDD_VOL_1350MV,
|
||||
DCVDD_VOL_1400MV,
|
||||
DCVDD_VOL_1450MV,
|
||||
DCVDD_VOL_1500MV,
|
||||
DCVDD_VOL_1550MV,
|
||||
DCVDD_VOL_1600MV,
|
||||
};
|
||||
|
||||
enum VDDIOM_VOL {
|
||||
VDDIOM_VOL_21V = 0,
|
||||
VDDIOM_VOL_22V,
|
||||
VDDIOM_VOL_23V,
|
||||
VDDIOM_VOL_24V,
|
||||
VDDIOM_VOL_25V,
|
||||
VDDIOM_VOL_26V,
|
||||
VDDIOM_VOL_27V,
|
||||
VDDIOM_VOL_28V,
|
||||
VDDIOM_VOL_29V,
|
||||
VDDIOM_VOL_30V,
|
||||
VDDIOM_VOL_31V,
|
||||
VDDIOM_VOL_32V,
|
||||
VDDIOM_VOL_33V,
|
||||
VDDIOM_VOL_34V,
|
||||
VDDIOM_VOL_35V,
|
||||
VDDIOM_VOL_36V,
|
||||
};
|
||||
|
||||
enum VDDIOW_VOL {
|
||||
VDDIOW_VOL_21V = 0,
|
||||
VDDIOW_VOL_22V,
|
||||
VDDIOW_VOL_23V,
|
||||
VDDIOW_VOL_24V,
|
||||
VDDIOW_VOL_25V,
|
||||
VDDIOW_VOL_26V,
|
||||
VDDIOW_VOL_27V,
|
||||
VDDIOW_VOL_28V,
|
||||
VDDIOW_VOL_29V,
|
||||
VDDIOW_VOL_30V,
|
||||
VDDIOW_VOL_31V,
|
||||
VDDIOW_VOL_32V,
|
||||
VDDIOW_VOL_33V,
|
||||
VDDIOW_VOL_34V,
|
||||
VDDIOW_VOL_35V,
|
||||
VDDIOW_VOL_36V,
|
||||
};
|
||||
|
||||
enum WVDD_VOL {
|
||||
WVDD_VOL_0500MV = 0,
|
||||
WVDD_VOL_0550MV,
|
||||
WVDD_VOL_0600MV,
|
||||
WVDD_VOL_0650MV,
|
||||
WVDD_VOL_0700MV,
|
||||
WVDD_VOL_0750MV,
|
||||
WVDD_VOL_0800MV,
|
||||
WVDD_VOL_0850MV,
|
||||
WVDD_VOL_0900MV,
|
||||
WVDD_VOL_0950MV,
|
||||
WVDD_VOL_1000MV,
|
||||
WVDD_VOL_1050MV,
|
||||
WVDD_VOL_1100MV,
|
||||
WVDD_VOL_1150MV,
|
||||
WVDD_VOL_1200MV,
|
||||
WVDD_VOL_1250MV,
|
||||
};
|
||||
|
||||
enum PVDD_VOL {
|
||||
PVDD_VOL_0500MV = 0,
|
||||
PVDD_VOL_0550MV,
|
||||
PVDD_VOL_0600MV,
|
||||
PVDD_VOL_0650MV,
|
||||
PVDD_VOL_0700MV,
|
||||
PVDD_VOL_0750MV,
|
||||
PVDD_VOL_0800MV,
|
||||
PVDD_VOL_0850MV,
|
||||
PVDD_VOL_0900MV,
|
||||
PVDD_VOL_0950MV,
|
||||
PVDD_VOL_1000MV,
|
||||
PVDD_VOL_1050MV,
|
||||
PVDD_VOL_1100MV,
|
||||
PVDD_VOL_1150MV,
|
||||
PVDD_VOL_1200MV,
|
||||
PVDD_VOL_1250MV,
|
||||
};
|
||||
|
||||
void dvdd_vol_sel(enum DVDD_VOL vol);
|
||||
enum DVDD_VOL get_dvdd_vol_sel();
|
||||
/*void dvdd2_vol_sel(enum DVDD2_VOL vol);*/
|
||||
/*enum DVDD2_VOL get_dvdd2_vol_sel();*/
|
||||
|
||||
/*void rvdd_vol_sel(enum RVDD_VOL vol);*/
|
||||
/*enum RVDD_VOL get_rvdd_vol_sel();*/
|
||||
/*void rvdd2_vol_sel(enum RVDD2_VOL vol);*/
|
||||
/*enum RVDD2_VOL get_rvdd2_vol_sel();*/
|
||||
|
||||
void dcvdd_vol_sel(enum DCVDD_VOL vol);
|
||||
enum DCVDD_VOL get_dcvdd_vol_sel();
|
||||
|
||||
/*void btvdd_vol_sel(enum BTVDD_VOL vol);*/
|
||||
/*enum BTVDD_VOL get_btvdd_vol_sel();*/
|
||||
|
||||
void pvdd_config(u32 lev, u32 low_lev, u32 output);
|
||||
void pvdd_output(u32 output);
|
||||
|
||||
void vddiom_vol_sel(enum VDDIOM_VOL vol);
|
||||
enum VDDIOM_VOL get_vddiom_vol_sel();
|
||||
void vddiow_vol_sel(enum VDDIOW_VOL vol);
|
||||
enum VDDIOW_VOL get_vddiow_vol_sel();
|
||||
|
||||
//
|
||||
//
|
||||
// lvd
|
||||
//
|
||||
//
|
||||
//
|
||||
/****************************************************************/
|
||||
typedef enum {
|
||||
LVD_RESET_MODE, //复位模式
|
||||
LVD_EXCEPTION_MODE, //异常模式，进入异常中断
|
||||
LVD_WAKEUP_MODE, //唤醒模式，进入唤醒中断，callback参数为回调函数
|
||||
} LVD_MODE;
|
||||
|
||||
typedef enum {
|
||||
VLVD_SEL_166V = 0,
|
||||
VLVD_SEL_177V,
|
||||
VLVD_SEL_188V,
|
||||
VLVD_SEL_199V,
|
||||
VLVD_SEL_210V,
|
||||
VLVD_SEL_221V,
|
||||
VLVD_SEL_232V,
|
||||
VLVD_SEL_243V,
|
||||
VLVD_SEL_254V,
|
||||
VLVD_SEL_265V,
|
||||
VLVD_SEL_276V,
|
||||
VLVD_SEL_287V,
|
||||
VLVD_SEL_298V,
|
||||
VLVD_SEL_309V,
|
||||
VLVD_SEL_320V,
|
||||
VLVD_SEL_331V,
|
||||
} LVD_VOL;
|
||||
|
||||
void lvd_en(u8 en);
|
||||
void lvd_config(LVD_VOL vol, u8 expin_en, LVD_MODE mode, void (*callback));
|
||||
|
||||
//
|
||||
//
|
||||
// pinr
|
||||
//
|
||||
//
|
||||
//
|
||||
//******************************************************************
|
||||
void gpio_longpress_pin0_reset_config(u32 pin, u32 level, u32 time, u32 release, u32 pull_enable);
|
||||
void gpio_longpress_pin1_reset_config(u32 pin, u32 level, u32 time, u32 release);
|
||||
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
// dcdc
|
||||
//
|
||||
//
|
||||
//
|
||||
//******************************************************************
|
||||
enum POWER_MODE {
|
||||
//LDO模式
|
||||
PWR_LDO15,
|
||||
//DCDC模式
|
||||
PWR_DCDC15,
|
||||
};
|
||||
|
||||
enum POWER_DCDC_TYPE {
|
||||
PWR_DCDC12 = 2,
|
||||
PWR_DCDC18_DCDC12 = 6,
|
||||
PWR_DCDC18_DCDC12_DCDC09 = 7,
|
||||
};
|
||||
|
||||
enum {
|
||||
DCDC09 = 1,
|
||||
DCDC12 = 2,
|
||||
DCDC18 = 4,
|
||||
};
|
||||
|
||||
void power_set_dcdc_type(enum POWER_DCDC_TYPE type);
|
||||
void power_set_mode(enum POWER_MODE mode);
|
||||
|
||||
|
||||
enum DVD_SHORT_DCV_MODE {
|
||||
DVDD_SHORT_DCVDDDIS = 0,
|
||||
DVDD_SHORT_DCVDD_EN,
|
||||
};
|
||||
void dcvdd_level_cfg(u8 dcvdd_level_set);
|
||||
void dvdd_short_dcvdd(enum DVD_SHORT_DCV_MODE short_mode, u8 dcvdd_level_set);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,157 @@
|
||||
/**@file p33_app.h
|
||||
* @brief hw sfr layer
|
||||
* @details
|
||||
* @author app / ic
|
||||
* @date 2021-10-13
|
||||
* @version V1.0
|
||||
* @copyright Copyright(c)2010-2031 JIELI
|
||||
*/
|
||||
#ifndef __P33_HW_H__
|
||||
#define __P33_HW_H__
|
||||
|
||||
//
|
||||
//
|
||||
// for p33_analog
|
||||
//
|
||||
//
|
||||
//
|
||||
/************************P3_PSW_CON0*****************************/
|
||||
#define DVD2SVD_SHORT_EN(en) p33_fast_access(P3_PSW_CON0, BIT(6), en)
|
||||
|
||||
//#define SVD2RVD2_SHORT_EN(en) p33_fast_access(P3_PSW_CON0, BIT(5), en)
|
||||
//
|
||||
//#define SVD2RVD_SHORT_EN(en) p33_fast_access(P3_PSW_CON0, BIT(4), en)
|
||||
//#define RVDD2_CAP_EN(en) p33_fast_access(P3_PSW_CON0, BIT(3), en)
|
||||
//#define RVD2_EN(en) p33_fast_access(P3_PSW_CON0, BIT(2), en)
|
||||
//
|
||||
//#define RVDD_CAP_EN(en) p33_fast_access(P3_PSW_CON0, BIT(1), en)
|
||||
//
|
||||
//#define RVD_EN(en) p33_fast_access(P3_PSW_CON0, BIT(0), en)
|
||||
|
||||
#define NVD2IO_SHORT_EN(en) p33_fast_access(P3_PSW_CON1, BIT(7), en)
|
||||
|
||||
//#define DVDD2_IFULL_EN(en) p33_fast_access(P3_PSW_CON1, BIT(6), en)
|
||||
//#define DVDD2_BYPASS_EN(en) p33_fast_access(P3_PSW_CON1, BIT(5), en)
|
||||
//#define DVDD2_EN(en) p33_fast_access(P3_PSW_CON1, BIT(4), en)
|
||||
//
|
||||
//#define RVDD2_BYPASS_EN(en) p33_fast_access(P3_PSW_CON1, BIT(3), en)
|
||||
//
|
||||
//#define RVDD_BYPASS_EN(en) p33_fast_access(P3_PSW_CON1, BIT(2), en)
|
||||
#define WVD2SVD_SHORT_EN(en) p33_fast_access(P3_PSW_CON1, BIT(1), en)
|
||||
#define WVDD_EN(en) p33_fast_access(P3_PSW_CON1, BIT(0), en)
|
||||
#define WVDD_PDOWN_ENTER() P33_CON_SET(P3_PSW_CON1, 0, 2, 0x03); P33_CON_SET(P3_PSW_CON0, 4, 3, 0x7)
|
||||
|
||||
#define WVDD_POFF_ENTER() P33_CON_SET(P3_PSW_CON1, 0, 2, 0x03); P33_CON_SET(P3_PSW_CON0, 4, 3, 0x1)
|
||||
|
||||
#define WVDD_PDOWN_POFF_EXIT() P33_CON_SET(P3_PSW_CON0, 4, 3, 0x07); P33_CON_SET(P3_PSW_CON1, 1, 1, 0x00)
|
||||
|
||||
/************************P3_PSW_CON2*****************************/
|
||||
//SS: soft start of VPQS
|
||||
//#define VQPS_SS_EN(en) p33_fast_access(P3_PSW_CON2, BIT(1), en)
|
||||
//
|
||||
//#define VQPS_EN(en) p33_fast_access(P3_PSW_CON2, BIT(0), en)
|
||||
|
||||
/************************P3_ANA_CON*****************************/
|
||||
//#define EVDD_IFULL_EN(en) p33_fast_access(P3_ANA_CON, BIT(0), en)
|
||||
|
||||
//DS: decrease undershoot and overshoot
|
||||
//#define DVD_DS_EN(en) p33_fast_access(P3_ANA_CON, BIT(1), en)
|
||||
|
||||
//#define RVD_DS_EN(en) p33_fast_access(P3_ANA_CON, BIT(2), en)
|
||||
|
||||
/************************P3_VBG_CON0*****************************/
|
||||
#define MVBG_SEL(sel) P33_CON_SET(P3_VBG_CON0, 0, 4, sel)
|
||||
|
||||
#define WVBG_SEL(sel) P33_CON_SET(P3_VBG_CON1, 4, 4, sel)
|
||||
|
||||
/************************P3_CLK_CON0*****************************/
|
||||
#define LRC24M_GATE_EN(a) p33_fast_access(P3_CLK_CON0, BIT(6), a)
|
||||
#define WDT_CLK_SEL(sel) P33_CON_SET(P3_CLK_CON0, 5, 1, sel)
|
||||
#define SOFF_RC250K_GATE(en) p33_fast_access(P3_CLK_CON0, BIT(4), en)
|
||||
#define D2SH_EN(a) p33_fast_access(P3_CLK_CON0, BIT(3), a)
|
||||
#define RCLK_SEL(sel) P33_CON_SET(P3_CLK_CON0, 2, 1, sel)
|
||||
#define RC_200K_SW_EN(a) p33_fast_access(P3_CLK_CON0, BIT(1), a)
|
||||
#define RC_250K_SW_EN(a) p33_fast_access(P3_CLK_CON0, BIT(0), a)
|
||||
|
||||
/************************P3_VLD_KEEP*****************************/
|
||||
#define RTC_WKUP_KEEP(a) p33_fast_access(P3_VLD_KEEP, BIT(1), a)
|
||||
|
||||
#define P33_WKUP_P11_EN(a) p33_fast_access(P3_VLD_KEEP, BIT(2), a)
|
||||
|
||||
#define VLD_KEEP_WDT_EXPT(en) p33_fast_access(P3_VLD_KEEP, BIT(6), en)
|
||||
|
||||
//
|
||||
//
|
||||
// for pmu flow
|
||||
//
|
||||
//
|
||||
//
|
||||
/************************P3_P11_CPU*****************************/
|
||||
#define P11_CPU_BRANCH_POWEROFF(en) p33_fast_access(P3_P11_CPU, BIT(1), en)
|
||||
|
||||
#define P11_CPU_RELEASE(en) p33_fast_access(P3_P11_CPU, BIT(0), en)
|
||||
|
||||
/************************P3_LP_CTL*****************************/
|
||||
//控制p11的低功耗
|
||||
#define LP_FLOW_EN(en) p33_fast_access(P3_LP_CTL, BIT(0), en)
|
||||
|
||||
#define LP_FLOW_CPND() p33_fast_access(P3_LP_CTL, BIT(6), 1)
|
||||
|
||||
#define POWER_ON_END() ((P33_CON_GET(P3_LP_CTL) & BIT(5)) ? 1: 0 )
|
||||
|
||||
/************************P3_ANA_FLOW0*****************************/
|
||||
#define DVD_EN(en) p33_fast_access(P3_ANA_FLOW0, BIT(0), en)
|
||||
|
||||
#define DCVD_TO_DIG_EN(en) p33_fast_access(P3_ANA_FLOW0, BIT(0)|BIT(1), en)
|
||||
|
||||
#define DCVD_LDO_EN(en) p33_fast_access(P3_ANA_FLOW0, BIT(2), en)
|
||||
|
||||
#define PAVD_LDO_EN(en) p33_fast_access(P3_ANA_FLOW0, BIT(3), en)
|
||||
|
||||
#define GET_DCDC12_STA() ((P33_CON_GET(P3_BUCK2_CON1) & (BIT(0))) ? 1:0)
|
||||
#define GET_LDO12_STA() ((P33_CON_GET(P3_ANA_FLOW0) & (BIT(2))) ? 1:0)
|
||||
#define GET_DCVD_STA() (GET_DCDC12_STA()|GET_LDO12_STA())
|
||||
|
||||
#define GET_PAVD_LDO_EN() ((P33_CON_GET(P3_ANA_FLOW0) & BIT(3)) ? 1:0)
|
||||
|
||||
#define PVDD_EN(en) p33_fast_access(P3_ANA_FLOW0, BIT(4), en)
|
||||
|
||||
#define MVIO_EN(en) p33_fast_access(P3_ANA_FLOW0, BIT(5), en)
|
||||
|
||||
#define VIN_EN(en) p33_fast_access(P3_ANA_FLOW0, BIT(6), en)
|
||||
|
||||
#define PW_GATE_EN(en) p33_fast_access(P3_ANA_FLOW0, BIT(5)|BIT(6), en)
|
||||
|
||||
#define MBG_EN(en) p33_fast_access(P3_ANA_FLOW0, BIT(7), en)
|
||||
|
||||
#define MVIO_PVDD_MVBG_ONLY() p33_tx_1byte(P3_ANA_FLOW0, BIT(4) | BIT(5) | BIT(6) | BIT(7))
|
||||
|
||||
#define PVDD_MVBG_ONLY() p33_tx_1byte(P3_ANA_FLOW0, BIT(4) | BIT(7))
|
||||
|
||||
#define PVDD_ONLY() p33_tx_1byte(P3_ANA_FLOW0, BIT(4))
|
||||
|
||||
/************************P3_ANA_FLOW1*****************************/
|
||||
#define WVIO_SHORT_EN(en) p33_fast_access(P3_ANA_FLOW1, BIT(5), en)
|
||||
|
||||
#define MIOV_VLMT_EN(en) p33_fast_access(P3_ANA_FLOW1, BIT(4), en)
|
||||
|
||||
#define MIOV_IFULL_EN(en) p33_fast_access(P3_ANA_FLOW1, BIT(3), en)
|
||||
|
||||
#define PAVD_IFULL_EN(en) p33_fast_access(P3_ANA_FLOW1, BIT(2), en)
|
||||
|
||||
#define DCVD_IFULL_EN(en) p33_fast_access(P3_ANA_FLOW1, BIT(1), en)
|
||||
|
||||
|
||||
#define DVD_IFULL_EN(en) p33_fast_access(P3_ANA_FLOW1, BIT(0), en)
|
||||
|
||||
|
||||
/************************P3_ANA_FLOW2*****************************/
|
||||
#define NVD2PVD_WSHORT_EN(en) p33_fast_access(P3_ANA_FLOW2, BIT(1), en)
|
||||
|
||||
#define NVD2PVD_SHORT_EN(en) p33_fast_access(P3_ANA_FLOW2, BIT(0), en)
|
||||
|
||||
|
||||
/************************P3_NVRAM_PWR*****************************/
|
||||
#define NVRAM_PWR_MODE(sel) P33_CON_SET(P3_NVRAM_PWR, 4, 2, sel)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,336 @@
|
||||
#ifndef __P33_SFR_H__
|
||||
#define __P33_SFR_H__
|
||||
#ifdef PMU_SYSTEM
|
||||
#define P33_ACCESS(x) (*(volatile u32 *)(0xc000 + x*4))
|
||||
#else
|
||||
#define P33_ACCESS(x) (*(volatile u32 *)(0xf20000 + 0xc000 + x*4))
|
||||
#endif
|
||||
|
||||
#ifdef PMU_SYSTEM
|
||||
#define RTC_ACCESS(x) (*(volatile u32 *)(0xd000 + x*4))
|
||||
#else
|
||||
#define RTC_ACCESS(x) (*(volatile u32 *)(0xf20000 + 0xd000 + x*4))
|
||||
#endif
|
||||
|
||||
//===========
|
||||
//===============================================================================//
|
||||
//
|
||||
//
|
||||
//
|
||||
//===============================================================================//
|
||||
//............. 0x0000 - 0x000f............
|
||||
#define P3_VLMT_CON P33_ACCESS(0x01)
|
||||
#define P3_POR_CON P33_ACCESS(0x02)
|
||||
#define P3_VLVD_CON0 P33_ACCESS(0x03)
|
||||
#define P3_VLVD_CON1 P33_ACCESS(0x04)
|
||||
#define P3_VLVD_FLT P33_ACCESS(0x05)
|
||||
#define P3_WDT_CON P33_ACCESS(0x06)
|
||||
#define P3_OCP_CON0 P33_ACCESS(0x07)
|
||||
|
||||
#define P3_ANA_FLOW0 P33_ACCESS(0x08)
|
||||
#define P3_ANA_FLOW1 P33_ACCESS(0x09)
|
||||
#define P3_ANA_FLOW2 P33_ACCESS(0x0a)
|
||||
|
||||
#define P3_ANA_KEEP0 P33_ACCESS(0x0c)
|
||||
#define P3_ANA_KEEP1 P33_ACCESS(0x0d)
|
||||
#define P3_ANA_KEEP2 P33_ACCESS(0x0e)
|
||||
|
||||
//............. 0X0010 - 0X001F.........for analog others
|
||||
#define P3_OSL_CON P33_ACCESS(0x10)
|
||||
#define P3_RST_FLAG P33_ACCESS(0x11)
|
||||
#define P3_VBAT_TYPE P33_ACCESS(0x12)
|
||||
#define P3_LRC_CON0 P33_ACCESS(0x13)
|
||||
#define P3_LRC_CON1 P33_ACCESS(0x14)
|
||||
#define P3_RST_CON0 P33_ACCESS(0x15)
|
||||
#define P3_RST_CON1 P33_ACCESS(0x16)
|
||||
#define P3_RST_CON2 P33_ACCESS(0x17)
|
||||
#define P3_VLD_KEEP P33_ACCESS(0x18)
|
||||
#define P3_CLK_CON0 P33_ACCESS(0x19)
|
||||
#define P3_ANA_READ P33_ACCESS(0x1a)
|
||||
#define P3_CHG_CON0 P33_ACCESS(0x1b)
|
||||
#define P3_CHG_CON1 P33_ACCESS(0x1c)
|
||||
#define P3_CHG_CON2 P33_ACCESS(0x1d)
|
||||
#define P3_CHG_CON3 P33_ACCESS(0x1e)
|
||||
#define P3_CHG_CON4 P33_ACCESS(0x1f)
|
||||
|
||||
//............. 0X0020 - 0X002F............ for buck circuit
|
||||
//#define P3_BUCK1_CON0 P33_ACCESS(0x20)
|
||||
//#define P3_BUCK1_CON1 P33_ACCESS(0x21)
|
||||
//#define P3_BUCK1_CON2 P33_ACCESS(0x22)
|
||||
//#define P3_BUCK1_CON3 P33_ACCESS(0x23)
|
||||
//#define P3_BUCK1_CON4 P33_ACCESS(0x24)
|
||||
//#define P3_BUCK1_CON5 P33_ACCESS(0x25)
|
||||
//#define P3_BUCK1_CON6 P33_ACCESS(0x26)
|
||||
//#define P3_BUCK1_CON7 P33_ACCESS(0x27)
|
||||
#define P3_BUCK2_CON0 P33_ACCESS(0x20)
|
||||
#define P3_BUCK2_CON1 P33_ACCESS(0x21)
|
||||
#define P3_BUCK2_CON2 P33_ACCESS(0x22)
|
||||
#define P3_BUCK2_CON3 P33_ACCESS(0x23)
|
||||
#define P3_BUCK2_CON4 P33_ACCESS(0x24)
|
||||
#define P3_BUCK2_CON5 P33_ACCESS(0x25)
|
||||
#define P3_BUCK2_CON6 P33_ACCESS(0x26)
|
||||
#define P3_BUCK2_CON7 P33_ACCESS(0x27)
|
||||
//#define P3_BUCK3_CON0 P33_ACCESS(0x28)
|
||||
//#define P3_BUCK3_CON1 P33_ACCESS(0x29)
|
||||
//#define P3_BUCK3_CON2 P33_ACCESS(0x2a)
|
||||
//#define P3_BUCK3_CON3 P33_ACCESS(0x2b)
|
||||
//#define P3_BUCK3_CON4 P33_ACCESS(0x2c)
|
||||
//#define P3_BUCK3_CON5 P33_ACCESS(0x2d)
|
||||
//#define P3_BUCK3_CON6 P33_ACCESS(0x2e)
|
||||
//#define P3_BUCK3_CON7 P33_ACCESS(0x2f)
|
||||
|
||||
//............. 0X0030 - 0X003F............ for PMU manager
|
||||
#define P3_SFLAG0 P33_ACCESS(0x30)
|
||||
#define P3_SFLAG1 P33_ACCESS(0x31)
|
||||
#define P3_SFLAG2 P33_ACCESS(0x32)
|
||||
#define P3_SFLAG3 P33_ACCESS(0x33)
|
||||
#define P3_SFLAG4 P33_ACCESS(0x34)
|
||||
#define P3_SFLAG5 P33_ACCESS(0x35)
|
||||
#define P3_SFLAG6 P33_ACCESS(0x36)
|
||||
#define P3_SFLAG7 P33_ACCESS(0x37)
|
||||
#define P3_SFLAG8 P33_ACCESS(0x38)
|
||||
#define P3_SFLAG9 P33_ACCESS(0x39)
|
||||
#define P3_SFLAGA P33_ACCESS(0x3a)
|
||||
#define P3_SFLAGB P33_ACCESS(0x3b)
|
||||
|
||||
//............. 0X0040 - 0X004F............ for
|
||||
#define P3_IVS_RD P33_ACCESS(0x40)
|
||||
#define P3_IVS_SET P33_ACCESS(0x41)
|
||||
#define P3_IVS_CLR P33_ACCESS(0x42)
|
||||
#define P3_PVDD0_AUTO P33_ACCESS(0x43)
|
||||
#define P3_PVDD1_AUTO P33_ACCESS(0x44)
|
||||
#define P3_WKUP_DLY P33_ACCESS(0x45)
|
||||
|
||||
#define P3_PCNT_FLT P33_ACCESS(0x48)
|
||||
#define P3_PCNT_CON P33_ACCESS(0x49)
|
||||
#define P3_PCNT_SET0 P33_ACCESS(0x4a)
|
||||
#define P3_PCNT_SET1 P33_ACCESS(0x4b)
|
||||
#define P3_PCNT_DAT0 P33_ACCESS(0x4c)
|
||||
#define P3_PCNT_DAT1 P33_ACCESS(0x4d)
|
||||
|
||||
#define P3_P11_CPU P33_ACCESS(0x4f)
|
||||
|
||||
//............. 0X0050 - 0X005F............ for port wake up
|
||||
#define P3_WKUP_FLT_EN0 P33_ACCESS(0x50)
|
||||
#define P3_WKUP_P_IE0 P33_ACCESS(0x51)
|
||||
#define P3_WKUP_N_IE0 P33_ACCESS(0x52)
|
||||
#define P3_WKUP_LEVEL0 P33_ACCESS(0x53)
|
||||
#define P3_WKUP_P_CPND0 P33_ACCESS(0x54)
|
||||
#define P3_WKUP_N_CPND0 P33_ACCESS(0x55)
|
||||
#define P3_WKUP_P_PND0 P33_ACCESS(0x56)
|
||||
#define P3_WKUP_N_PND0 P33_ACCESS(0x57)
|
||||
#define P3_WKUP_FLT_EN1 P33_ACCESS(0x58)
|
||||
#define P3_WKUP_P_IE1 P33_ACCESS(0x59)
|
||||
#define P3_WKUP_N_IE1 P33_ACCESS(0x5a)
|
||||
#define P3_WKUP_LEVEL1 P33_ACCESS(0x5b)
|
||||
#define P3_WKUP_P_CPND1 P33_ACCESS(0x5c)
|
||||
#define P3_WKUP_N_CPND1 P33_ACCESS(0x5d)
|
||||
#define P3_WKUP_P_PND1 P33_ACCESS(0x5e)
|
||||
#define P3_WKUP_N_PND1 P33_ACCESS(0x5f)
|
||||
|
||||
//............. 0X0060 - 0X006F............ for analog wake up
|
||||
#define P3_AWKUP_FLT_EN P33_ACCESS(0x60)
|
||||
#define P3_AWKUP_P_IE P33_ACCESS(0x61)
|
||||
#define P3_AWKUP_N_IE P33_ACCESS(0x62)
|
||||
#define P3_AWKUP_LEVEL P33_ACCESS(0x63)
|
||||
#define P3_AWKUP_P_PND P33_ACCESS(0x64)
|
||||
#define P3_AWKUP_N_PND P33_ACCESS(0x65)
|
||||
#define P3_AWKUP_P_CPND P33_ACCESS(0x66)
|
||||
#define P3_AWKUP_N_CPND P33_ACCESS(0x67)
|
||||
#define P3_WKUP_CLK_SEL P33_ACCESS(0x68)
|
||||
#define P3_AWKUP_CLK_SEL P33_ACCESS(0x69)
|
||||
#define P3_SYS_PWR0 P33_ACCESS(0x6a)
|
||||
#define P3_SYS_PWR1 P33_ACCESS(0x6b)
|
||||
#define P3_SYS_PWR2 P33_ACCESS(0x6c)
|
||||
#define P3_SYS_PWR3 P33_ACCESS(0x6d)
|
||||
#define P3_SYS_PWR4 P33_ACCESS(0x6e)
|
||||
#define P3_SYS_PWR5 P33_ACCESS(0x6f)
|
||||
|
||||
//............. 0X0070 - 0X007F............ for
|
||||
#define P3_PGDR_CON0 P33_ACCESS(0x70)
|
||||
#define P3_PGDR_CON1 P33_ACCESS(0x71)
|
||||
#define P3_PGSD_CON P33_ACCESS(0x72)
|
||||
|
||||
#define P3_LP_CTL P33_ACCESS(0x74)
|
||||
#define P3_LP_CFG P33_ACCESS(0x75)
|
||||
#define P3_NVRAM_PWR P33_ACCESS(0x76)
|
||||
#define P3_WVD_CON0 P33_ACCESS(0x77)
|
||||
#define P3_PVD_CON0 P33_ACCESS(0x78)
|
||||
#define P3_EVD_CON0 P33_ACCESS(0x79)
|
||||
#define P3_PMU_CON0 P33_ACCESS(0x7a)
|
||||
|
||||
#define P3_PMU_CON4 P33_ACCESS(0x7e)
|
||||
#define P3_PMU_CON5 P33_ACCESS(0x7f)
|
||||
|
||||
//............. 0X0080 - 0X008F............ for
|
||||
#define P3_PINR_CON P33_ACCESS(0x80)
|
||||
#define P3_PINR_CON1 P33_ACCESS(0x81)
|
||||
#define P3_PINR_SAFE P33_ACCESS(0x82)
|
||||
#define P3_PINR_SAFE1 P33_ACCESS(0x83)
|
||||
#define P3_PINR_PND1 P33_ACCESS(0x84)
|
||||
|
||||
#define P3_RST_SRC0 P33_ACCESS(0x8e)
|
||||
#define P3_RST_SRC1 P33_ACCESS(0x8f)
|
||||
|
||||
//............. 0X0090 - 0X009F............ for
|
||||
#define P3_PSW_CON0 P33_ACCESS(0x90)
|
||||
#define P3_PSW_CON1 P33_ACCESS(0x91)
|
||||
#define P3_PSW_CON2 P33_ACCESS(0x92)
|
||||
#define P3_PMU_ADC0 P33_ACCESS(0x93)
|
||||
#define P3_PMU_ADC1 P33_ACCESS(0x94)
|
||||
#define P3_VBG_CON0 P33_ACCESS(0x95)
|
||||
#define P3_VBG_CON1 P33_ACCESS(0x96)
|
||||
#define P3_IOV_CON0 P33_ACCESS(0x97)
|
||||
#define P3_IOV_CON1 P33_ACCESS(0x98)
|
||||
#define P3_PAVD_CON0 P33_ACCESS(0x99)
|
||||
#define P3_DCV_CON0 P33_ACCESS(0x9a)
|
||||
#define P3_DVD_CON0 P33_ACCESS(0x9b)
|
||||
#define P3_DVD2_CON0 P33_ACCESS(0x9c)
|
||||
#define P3_RVD_CON0 P33_ACCESS(0x9d)
|
||||
#define P3_RVD_CON1 P33_ACCESS(0x9e)
|
||||
#define P3_RVD2_CON0 P33_ACCESS(0x9f)
|
||||
|
||||
//............. 0X00A0 - 0X00AF............
|
||||
#define P3_PR_PWR P33_ACCESS(0xa0)
|
||||
#define P3_VPWR_CON0 P33_ACCESS(0xa1)
|
||||
#define P3_VPWR_CON1 P33_ACCESS(0xa2)
|
||||
#define P3_RTC_ADC0 P33_ACCESS(0xa3)
|
||||
#define P3_LS_P11 P33_ACCESS(0xa4)
|
||||
#define P3_LS_EN P33_ACCESS(0xa5)
|
||||
|
||||
#define P3_EXT_EFUSE_CON P33_ACCESS(0xa6)
|
||||
|
||||
#define P3_WKUP_SRC P33_ACCESS(0xa8)
|
||||
#define P3_ANA_MFIX P33_ACCESS(0xa9)
|
||||
#define P3_DBG_CON0 P33_ACCESS(0xaa)
|
||||
#define P3_DBG_CON1 P33_ACCESS(0xab)
|
||||
#define P3_MFIX_OPT P33_ACCESS(0xac)
|
||||
|
||||
//............. 0X00B0 - 0X00BF............ for EFUSE
|
||||
#define P3_EFUSE_CON0 P33_ACCESS(0xb0)
|
||||
#define P3_EFUSE_CON1 P33_ACCESS(0xb1)
|
||||
#define P3_EFUSE_CON2 P33_ACCESS(0xb2)
|
||||
#define P3_EFUSE_RDAT P33_ACCESS(0xb3)
|
||||
#define P3_EFUSE_PU_DAT0 P33_ACCESS(0xb4)
|
||||
#define P3_EFUSE_PU_DAT1 P33_ACCESS(0xb5)
|
||||
#define P3_EFUSE_PU_DAT2 P33_ACCESS(0xb6)
|
||||
#define P3_EFUSE_PU_DAT3 P33_ACCESS(0xb7)
|
||||
|
||||
#define P3_FUNC_EN P33_ACCESS(0xb8)
|
||||
#define P3_FUNC_CTL0 P33_ACCESS(0xb9)
|
||||
#define P3_FUNC_CTL1 P33_ACCESS(0xba)
|
||||
#define P3_FUNC_CTL2 P33_ACCESS(0xbb)
|
||||
#define P3_EFUSE_ANA0 P33_ACCESS(0xbc)
|
||||
|
||||
//............. 0X00C0 - 0X00CF............ for port input select
|
||||
#define P3_PORT_SEL0 P33_ACCESS(0xc0)
|
||||
#define P3_PORT_SEL1 P33_ACCESS(0xc1)
|
||||
#define P3_PORT_SEL2 P33_ACCESS(0xc2)
|
||||
#define P3_PORT_SEL3 P33_ACCESS(0xc3)
|
||||
#define P3_PORT_SEL4 P33_ACCESS(0xc4)
|
||||
#define P3_PORT_SEL5 P33_ACCESS(0xc5)
|
||||
#define P3_PORT_SEL6 P33_ACCESS(0xc6)
|
||||
#define P3_PORT_SEL7 P33_ACCESS(0xc7)
|
||||
|
||||
//............. 0x00d0 - 0x00df............
|
||||
#define P3_LS_IO_USR P33_ACCESS(0xd0) //TODO: check sync with verilog head file chip_def.v LEVEL_SHIFTER
|
||||
#define P3_LS_IO_ROM P33_ACCESS(0xd1)
|
||||
#define P3_LS_IO_PINR P33_ACCESS(0xd2)
|
||||
#define P3_LS_CTMU P33_ACCESS(0xd3)
|
||||
#define P3_LS_IO_SHA P33_ACCESS(0xd4)
|
||||
#define P3_LS_LRC24M P33_ACCESS(0xd5)
|
||||
#define P3_LS_BT P33_ACCESS(0xd6)
|
||||
#define P3_LS_PLL P33_ACCESS(0xd7)
|
||||
|
||||
//............. 0X00E0 - 0X00FF............ for p33 lp timer
|
||||
#define P3_LP_RSC00 P33_ACCESS(0xe0)
|
||||
#define P3_LP_RSC01 P33_ACCESS(0xe1)
|
||||
#define P3_LP_RSC02 P33_ACCESS(0xe2)
|
||||
#define P3_LP_RSC03 P33_ACCESS(0xe3)
|
||||
#define P3_LP_PRD00 P33_ACCESS(0xe4)
|
||||
#define P3_LP_PRD01 P33_ACCESS(0xe5)
|
||||
#define P3_LP_PRD02 P33_ACCESS(0xe6)
|
||||
#define P3_LP_PRD03 P33_ACCESS(0xe7)
|
||||
#define P3_LP_RSC10 P33_ACCESS(0xe8)
|
||||
#define P3_LP_RSC11 P33_ACCESS(0xe9)
|
||||
#define P3_LP_RSC12 P33_ACCESS(0xea)
|
||||
#define P3_LP_RSC13 P33_ACCESS(0xeb)
|
||||
#define P3_LP_RSC14 P33_ACCESS(0xec)
|
||||
#define P3_LP_RSC15 P33_ACCESS(0xed)
|
||||
#define P3_LP_PRD10 P33_ACCESS(0xee)
|
||||
#define P3_LP_PRD11 P33_ACCESS(0xef)
|
||||
#define P3_LP_PRD12 P33_ACCESS(0xf0)
|
||||
#define P3_LP_PRD13 P33_ACCESS(0xf1)
|
||||
#define P3_LP_PRD14 P33_ACCESS(0xf2)
|
||||
#define P3_LP_PRD15 P33_ACCESS(0xf3)
|
||||
#define P3_LP_TMR0_CLK P33_ACCESS(0xf4)
|
||||
#define P3_LP_TMR1_CLK P33_ACCESS(0xf5)
|
||||
#define P3_LP_TMR0_CON P33_ACCESS(0xf6)
|
||||
#define P3_LP_TMR1_CON P33_ACCESS(0xf7)
|
||||
#define P3_LP_TMR_CFG P33_ACCESS(0xf8)
|
||||
#define P3_LP_CNTRD0 P33_ACCESS(0xf9)
|
||||
#define P3_LP_CNT0 P33_ACCESS(0xfa)
|
||||
#define P3_LP_CNT1 P33_ACCESS(0xfb)
|
||||
#define P3_LP_CNT2 P33_ACCESS(0xfc)
|
||||
#define P3_LP_CNT3 P33_ACCESS(0xfd)
|
||||
#define P3_LP_CNT4 P33_ACCESS(0xfe)
|
||||
#define P3_LP_CNT5 P33_ACCESS(0xff)
|
||||
|
||||
|
||||
|
||||
//===============================================================================//
|
||||
//
|
||||
// P33 RTCVDD
|
||||
//
|
||||
//===============================================================================//
|
||||
|
||||
//............. 0X0080 - 0X008F............ for RTC
|
||||
#define R3_ALM_CON RTC_ACCESS(0x80)
|
||||
|
||||
#define R3_RTC_CON0 RTC_ACCESS(0x84)
|
||||
#define R3_RTC_CON1 RTC_ACCESS(0x85)
|
||||
#define R3_RTC_DAT0 RTC_ACCESS(0x86)
|
||||
#define R3_RTC_DAT1 RTC_ACCESS(0x87)
|
||||
#define R3_RTC_DAT2 RTC_ACCESS(0x88)
|
||||
#define R3_RTC_DAT3 RTC_ACCESS(0x89)
|
||||
#define R3_RTC_DAT4 RTC_ACCESS(0x8a)
|
||||
#define R3_ALM_DAT0 RTC_ACCESS(0x8b)
|
||||
#define R3_ALM_DAT1 RTC_ACCESS(0x8c)
|
||||
#define R3_ALM_DAT2 RTC_ACCESS(0x8d)
|
||||
#define R3_ALM_DAT3 RTC_ACCESS(0x8e)
|
||||
#define R3_ALM_DAT4 RTC_ACCESS(0x8f)
|
||||
|
||||
//............. 0X0090 - 0X009F............ for wake up
|
||||
#define R3_WKUP_EN RTC_ACCESS(0x90)
|
||||
#define R3_WKUP_EDGE RTC_ACCESS(0x91)
|
||||
#define R3_WKUP_CPND RTC_ACCESS(0x92)
|
||||
#define R3_WKUP_PND RTC_ACCESS(0x93)
|
||||
#define R3_WKUP_LEVEL RTC_ACCESS(0x94)
|
||||
|
||||
//............. 0X00A0 - 0X00AF............ for system
|
||||
#define R3_TIME_CON RTC_ACCESS(0xa0)
|
||||
#define R3_TIME_CPND RTC_ACCESS(0xa1)
|
||||
#define R3_TIME_PND RTC_ACCESS(0xa2)
|
||||
|
||||
#define R3_ADC_CON RTC_ACCESS(0xa4)
|
||||
#define R3_OSL_CON RTC_ACCESS(0xa5)
|
||||
|
||||
#define R3_WKUP_SRC RTC_ACCESS(0xa8)
|
||||
#define R3_RST_SRC RTC_ACCESS(0xa9)
|
||||
|
||||
#define R3_RST_CON RTC_ACCESS(0xab)
|
||||
#define R3_CLK_CON RTC_ACCESS(0xac)
|
||||
|
||||
//............. 0X00B0 - 0X00BF............ for PORT control
|
||||
#define R3_PR_IN RTC_ACCESS(0xb0)
|
||||
#define R3_PR_OUT RTC_ACCESS(0xb1)
|
||||
#define R3_PR_DIR RTC_ACCESS(0xb2)
|
||||
#define R3_PR_DIE RTC_ACCESS(0xb3)
|
||||
#define R3_PR_PU0 RTC_ACCESS(0xb4)
|
||||
#define R3_PR_PU1 RTC_ACCESS(0xb5)
|
||||
#define R3_PR_PD0 RTC_ACCESS(0xb6)
|
||||
#define R3_PR_PD1 RTC_ACCESS(0xb7)
|
||||
#define R3_PR_HD0 RTC_ACCESS(0xb8)
|
||||
#define R3_PR_HD1 RTC_ACCESS(0xb9)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,175 @@
|
||||
#ifndef __POWER_API_H__
|
||||
#define __POWER_API_H__
|
||||
|
||||
#define AT_VOLATILE_RAM_POWER AT(.power_driver.data)
|
||||
#define AT_VOLATILE_RAM_BSS_POWER AT(.power_driver.data.bss)
|
||||
#define AT_VOLATILE_RAM_CODE_POWER AT(.power_driver.text.cache.L1)
|
||||
|
||||
#define AT_VOLATILE_RAM_LOWPOWER AT_VOLATILE_RAM_POWER //AT(.power_driver.data.overlay)
|
||||
#define AT_VOLATILE_RAM_BSS_LOWPOWER AT_VOLATILE_RAM_BSS_POWER //AT(.power_driver.data.bss.overlay)
|
||||
#define AT_VOLATILE_RAM_CODE_LOWPOWER AT_VOLATILE_RAM_CODE_POWER //AT(.power_driver.text.cache.L1.overlay)
|
||||
|
||||
//
|
||||
//
|
||||
// platform_data
|
||||
//
|
||||
//
|
||||
//
|
||||
//******************************************************************
|
||||
//config
|
||||
enum LOWPOWER_CONFIG {
|
||||
LOWPOWER_CLOSE,
|
||||
SLEEP_EN,
|
||||
DEEP_SLEEP_EN,
|
||||
};
|
||||
|
||||
//osc_type
|
||||
enum LOWPOWER_OSC_TYPE {
|
||||
OSC_TYPE_LRC,
|
||||
OSC_TYPE_BT_OSC,
|
||||
OSC_TYPE_NULL,
|
||||
};
|
||||
|
||||
struct _power_param {
|
||||
//sleep
|
||||
u32 btosc_hz; //蓝牙晶振频率(默认使用24M)
|
||||
u32 osc_delay_us; //低功耗晶振起振延时，为预留配置。
|
||||
u32 t1; //低功耗参数，预留配置
|
||||
u32 t2; //低功耗参数，预留配置
|
||||
u32 t3; //低功耗参数，预留配置
|
||||
u32 t4; //低功耗参数，预留配置
|
||||
|
||||
//power
|
||||
//vddiom\vddiow在进出低功耗时使用 VDDIO_KEEP_TYPE 配置
|
||||
u8 vddiom_lev; //vddiom，系统工作时使用vddiom ldo(使用enum VDDIOM_VOL配置)
|
||||
u8 vddiow_lev; //vddiow，系统低功耗时使用vddiow ldo(使用enum VDDIOW_VOL配置)
|
||||
|
||||
//sleep
|
||||
u8 config; //低功耗使能，蓝牙&&系统空闲可进入低功耗(使用LOWPOWER_CONFIG配置)
|
||||
u8 osc_type; //低功耗晶振类型(使用enum LOWPOWER_OSC_TYPE配置)
|
||||
u8 lptmr_flow; //低功耗参数由用户配置
|
||||
};
|
||||
|
||||
struct _power_pdata {
|
||||
struct _power_param *power_param_p;
|
||||
struct _wakeup_param *wakeup_param_p;
|
||||
};
|
||||
|
||||
//
|
||||
//
|
||||
// power_api
|
||||
//
|
||||
//
|
||||
//
|
||||
//******************************************************************
|
||||
enum VDDIO_KEEP_TYPE {
|
||||
VDDIO_KEEP_TYPE_NULL, //vddiow使用配置值
|
||||
VDDIO_KEEP_TYPE_NORMAL, //vddiow使用配置值使用vddiom挡位，即vddiom_lev
|
||||
VDDIO_KEEP_TYPE_TRIM, //vddiow使用trim值
|
||||
VDDIO_KEEP_TYPE_PG, //保持vddiom不关闭
|
||||
VDDIO_KEEP_TYPE_CLOSE, //vddio关闭
|
||||
};
|
||||
|
||||
|
||||
//#include "power/low_power.h"
|
||||
|
||||
void power_early_init(u32 arg);
|
||||
|
||||
void power_later_init(u32 arg);
|
||||
|
||||
void power_init(struct _power_pdata *pdata);
|
||||
|
||||
enum PCONTROL_CMD {
|
||||
PCONTROL_POWER_DRIVER_RESERVE = 0,
|
||||
PCONTROL_P_PUTBYTE, //串口调试函数
|
||||
|
||||
//*****************************************************
|
||||
/* power
|
||||
*/
|
||||
PCONTROL_POWER_MODE = 0x100,
|
||||
PCONTROL_DCVDD_CAP_SW, //0：DCVDD上没有外挂电容 1：DCVDD上有外挂电容
|
||||
PCONTROL_FLASH_PG_VDDIO, //0：FLASH电源引脚使用IO 1：FLASH电源引脚没有使用IO
|
||||
PCONTROL_RTC_CLK, //RTC_CLK类型，配置开机、关机晶振流程
|
||||
PCONTROL_POWER_SUPPLY, //供电方式，0：IOVDD供电，1：VPWR供电
|
||||
|
||||
//*****************************************************
|
||||
/* sleep
|
||||
*/
|
||||
PCONTROL_PD_VDDIO_KEEP, //pdown vddio切换流程(使用enum VDDIO_KEEP_TYPE配置)
|
||||
PCONTROL_PD_WDVDD_LEV, //pdown wvdd挡位
|
||||
PCONTROL_PD_DVDD_LEV, //pdown dvdd挡位
|
||||
PCONTROL_PD_KEEP_LPCTMU, //pdown 触摸是否保持 0：不保持 1：保持
|
||||
|
||||
//*****************************************************
|
||||
/* soff
|
||||
*/
|
||||
PCONTROL_SF_KEEP_LRC, //soff lrc是否保持 0：不保持 1：保持
|
||||
PCONTROL_SF_VDDIO_KEEP, //soff vddio切换流程(使用enum VDDIO_KEEP_TYPE配置)
|
||||
PCONTROL_SF_KEEP_NVDD, //soff nvdd是否保持 0：不保持 1：保持
|
||||
PCONTROL_SF_KEEP_PVDD, //soff pvdd是否保持 0：不保持 1：保持
|
||||
|
||||
|
||||
//*****************************************************
|
||||
/* 以下配置为对应子模块的预留配置
|
||||
*/
|
||||
PCONTROL_PHW_RESERVE = 0x100, //使用enum POWER_MODE配置
|
||||
PCONTROL_P33_RESERVE = 0x200, //使用PCONTROL_P33_CMD配置
|
||||
PCONTROL_P11_RESERVE = 0x300, //使用PCONTROL_P11_CMD配置
|
||||
PCONTROL_LP_FLOW_IC_RESERVE = 0x400, //使用PCONTROL_IC_CMD配置
|
||||
};
|
||||
|
||||
u32 power_control(enum PCONTROL_CMD cmd, u32 arg);
|
||||
|
||||
void dvdd2_bypass_en(u8 mode);
|
||||
|
||||
//
|
||||
//
|
||||
// lowpower
|
||||
//
|
||||
//
|
||||
//
|
||||
//******************************************************************
|
||||
void pmu_trim(u32 force_trim, u32 vddio_tieup_vbat);
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
// soff
|
||||
//
|
||||
//
|
||||
//
|
||||
//******************************************************************
|
||||
|
||||
//p33 soft flag
|
||||
enum soft_flag_io_stage {
|
||||
SOFTFLAG_HIGH_RESISTANCE,
|
||||
SOFTFLAG_PU,
|
||||
SOFTFLAG_PD,
|
||||
|
||||
SOFTFLAG_OUT0,
|
||||
SOFTFLAG_OUT0_HD0,
|
||||
SOFTFLAG_OUT0_HD,
|
||||
SOFTFLAG_OUT0_HD0_HD,
|
||||
|
||||
SOFTFLAG_OUT1,
|
||||
SOFTFLAG_OUT1_HD0,
|
||||
SOFTFLAG_OUT1_HD,
|
||||
SOFTFLAG_OUT1_HD0_HD,
|
||||
|
||||
SOFTFLAG_PU100K,
|
||||
SOFTFLAG_PU1M,
|
||||
SOFTFLAG_PD100K,
|
||||
SOFTFLAG_PD1M,
|
||||
};
|
||||
|
||||
struct app_soft_flag_t {
|
||||
u8 sfc_fast_boot;
|
||||
u8 flash_stable_delay_sel;
|
||||
u8 usbdp;
|
||||
u8 usbdm;
|
||||
u8 pp0;
|
||||
};
|
||||
|
||||
void mask_softflag_config(struct app_soft_flag_t *softflag);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,13 @@
|
||||
#ifndef __POWER_COMPAT_H__
|
||||
#define __POWER_COMPAT_H__
|
||||
|
||||
int cpu_reset_by_soft();
|
||||
|
||||
void wdt_close();
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,54 @@
|
||||
#ifndef __POWER_GATE_H__
|
||||
#define __POWER_GATE_H__
|
||||
|
||||
|
||||
#include "typedef.h"
|
||||
|
||||
//STPG define bit
|
||||
#define STPG_A 0 //STPG output bit
|
||||
#define STPG_HD0 2 //STPG HD0
|
||||
#define STPG_HD1 3 //STPG HD1
|
||||
#define STPG_OE 4 //STPG output enable bit
|
||||
#define STPG_PD 5 //STPG pull down enable bit
|
||||
#define STPG_PD1 6 //STPG pull down enable bit
|
||||
|
||||
/*
|
||||
*@brief 初始化pg_io送出高阻+低电平的pwm
|
||||
*@param pg_io : 可选IO_LCD_PG, IO_MT_PG
|
||||
*@param freq : pwm的频率
|
||||
*@param duty : pwm的低电平的占空比，0~10000对应0%~100%
|
||||
*@return 0:成功 非0:失败
|
||||
*/
|
||||
int power_gate_pwm_init(u32 pg_io, u32 freq, u32 duty);
|
||||
|
||||
/*
|
||||
*@brief 设置pg_io的pwm的低电平占空比
|
||||
*@param pg_io : 可选IO_LCD_PG, IO_MT_PG
|
||||
*@param duty : pwm的低电平的占空比，0~10000对应0%~100%
|
||||
*/
|
||||
void power_gate_pwm_set_duty(u32 pg_io, u32 duty);
|
||||
|
||||
/*
|
||||
*@brief 关闭pwm, pg_io为高阻
|
||||
*@param pg_io : 可选IO_LCD_PG, IO_MT_PG
|
||||
*/
|
||||
void power_gate_pwm_close(u32 pg_io);
|
||||
|
||||
/*
|
||||
*@brief 设置pg_io的开漏输出
|
||||
*@param pg_io : 可选IO_LCD_PG, IO_MT_PG
|
||||
*@param value : 0,输出低电平 1,则高阻
|
||||
*/
|
||||
void power_gate_open_drain_output(u32 pg_io, u32 value);
|
||||
|
||||
|
||||
/*
|
||||
*@brief 初始化stpg供电给psram
|
||||
*@param udly_time : us延时
|
||||
*@param mdly_time : ms延时
|
||||
*@param *custom_udelay :us延时回调函数
|
||||
*@param *custom_mdelay :ms延时回调函数
|
||||
*/
|
||||
void power_gate_psram_base(u32 udly_time, u32 mdly_time, void (*custom_udelay)(u32), void (*custom_mdelay)(u32));
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,134 @@
|
||||
#ifndef __POWER_PORT_H__
|
||||
#define __POWER_PORT_H__
|
||||
|
||||
//
|
||||
//
|
||||
// FLASH PIN
|
||||
//
|
||||
//
|
||||
//
|
||||
//*****************************************************************************/
|
||||
#define GET_SFC_PORT() ((JL_SFC_IOMC->IOMC0 & BIT(1)) ? 1:0)
|
||||
|
||||
/******************************************************************************/
|
||||
#define _PORT(p) JL_PORT##p
|
||||
#define _PORT_IN(p,b) P##p##b##_IN
|
||||
#define _PORT_OUT(p,b) JL_OMAP->P##p##b##_OUT
|
||||
|
||||
/****************************spi boot *****************************************/
|
||||
#define SPI_PORT(p) _PORT(p)
|
||||
#define SPI0_FUNC_OUT(p,b) _PORT_OUT(p,b)
|
||||
#define SPI0_FUNC_IN(p,b) _PORT_IN(p,b)
|
||||
// | func\port | A | B |
|
||||
// |-----------|------|------|
|
||||
// | VCC | FSPG | |
|
||||
// | CS | PD3 | |
|
||||
// | CLK | PD0 | |
|
||||
// | DO(D0) | PD1 | |
|
||||
// | DI(D1) | PD2 | |
|
||||
// | WP(D2) | PA5 | |
|
||||
// | HOLD(D3) | PA6 | |
|
||||
|
||||
|
||||
//FSPG define bit
|
||||
#define FSPG_A 0 //FSPG output bit
|
||||
#define FSPG_CS_EN 1 //FSPG CS connect enable bit
|
||||
#define FSPG_HD0 2 //FSPG HD0
|
||||
#define FSPG_HD1 3 //FSPG HD1
|
||||
#define FSPG_OE 4 //FSPG output enable bit
|
||||
#define FSPG_PD 5 //FSPG pull down enable bit
|
||||
#define FSPG_PD1 6 //FSPG pull down enable bit
|
||||
#define FSPG_18V 7 //flash supply power domain 1: DCVDD 1.8V; 0: IOVDD;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//group a
|
||||
#define PORT_SPI0_CSA F
|
||||
#define SPI0_CSA 0
|
||||
|
||||
#define PORT_SPI0_CLKA F
|
||||
#define SPI0_CLKA 4
|
||||
|
||||
#define PORT_SPI0_DOA F
|
||||
#define SPI0_DOA 5
|
||||
|
||||
#define PORT_SPI0_DIA F
|
||||
#define SPI0_DIA 1
|
||||
|
||||
#define PORT_SPI0_D2A F
|
||||
#define SPI0_D2A 2
|
||||
|
||||
#define PORT_SPI0_D3A F
|
||||
#define SPI0_D3A 3
|
||||
|
||||
|
||||
//#define SPI0_PWR_A IO_PORTD_04
|
||||
#define SPI0_CS_A IO_PORTF_00
|
||||
#define SPI0_CLK_A IO_PORTF_04
|
||||
#define SPI0_DO_D0_A IO_PORTF_05
|
||||
#define SPI0_DI_D1_A IO_PORTF_01
|
||||
#define SPI0_WP_D2_A IO_PORTF_02
|
||||
#define SPI0_HOLD_D3_A IO_PORTF_03
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//group b
|
||||
#define PORT_SPI0_CSB F
|
||||
#define SPI0_CSB 3
|
||||
|
||||
#define PORT_SPI0_CLKB F
|
||||
#define SPI0_CLKB 1
|
||||
|
||||
#define PORT_SPI0_DOB F
|
||||
#define SPI0_DOB 0
|
||||
|
||||
#define PORT_SPI0_DIB F
|
||||
#define SPI0_DIB 4
|
||||
|
||||
#define PORT_SPI0_D2B F
|
||||
#define SPI0_D2B 5
|
||||
|
||||
#define PORT_SPI0_D3B F
|
||||
#define SPI0_D3B 2
|
||||
|
||||
//#define SPI0_PWR_B IO_PORTD_04
|
||||
#define SPI0_CS_B IO_PORTF_03
|
||||
#define SPI0_CLK_B IO_PORTF_01
|
||||
#define SPI0_DO_D0_B IO_PORTF_00
|
||||
#define SPI0_DI_D1_B IO_PORTF_04
|
||||
#define SPI0_WP_D2_B IO_PORTF_05
|
||||
#define SPI0_HOLD_D3_B IO_PORTF_02
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
//
|
||||
//
|
||||
// PSRAM
|
||||
//
|
||||
//
|
||||
//
|
||||
//*****************************************************************************/
|
||||
#define PSRAM_CS IO_PORTC_06
|
||||
#define PSRAM_CLK IO_PORTC_05
|
||||
#define PSRAM_D0A IO_PORTC_09
|
||||
#define PSRAM_D1A IO_PORTC_07
|
||||
#define PSRAM_D2A IO_PORTC_08
|
||||
#define PSRAM_D3A IO_PORTC_04
|
||||
|
||||
#define PINR_DEFAULT_IO IO_PORTB_01
|
||||
|
||||
#define MCLR_PORT IO_PORTB_06
|
||||
|
||||
//A B C F P USB
|
||||
#define PORT_TABLE(arg) u32 gpio_confi##arg[6] = {0xffff, 0xffff,0xffff, 0xffff, 0xffff, 0xffff}
|
||||
|
||||
void port_protect(u32 *gpio_config, u32 gpio);
|
||||
|
||||
#define PORT_PROTECT(gpio) port_protect(gpio_config, gpio)
|
||||
|
||||
void init_boot_rom();
|
||||
u8 get_boot_rom();
|
||||
|
||||
void *__port_init(u32 arg);
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,42 @@
|
||||
#ifndef __POWER_INTERFACE_H__
|
||||
#define __POWER_INTERFACE_H__
|
||||
|
||||
#include "generic/typedef.h"
|
||||
#include "gpio.h"
|
||||
|
||||
//-------------------------------------------------------
|
||||
/* p33
|
||||
*/
|
||||
#include "power/p33/p33_sfr.h"
|
||||
#include "power/p33/p33_access.h"
|
||||
#include "power/p33/charge_hw.h"
|
||||
#include "power/p33/p33_api.h"
|
||||
//#include "power/wdt.h"
|
||||
|
||||
//-------------------------------------------------------
|
||||
/* p11
|
||||
*/
|
||||
#include "power/p11/p11_csfr.h"
|
||||
#include "power/p11/p11_sfr.h"
|
||||
#include "power/p11/p11_mmap.h"
|
||||
#include "power/p11/p11_api.h"
|
||||
#include "power/p11/lp_ipc.h"
|
||||
#include "power/p11/ipc_spin_lock.h"
|
||||
|
||||
|
||||
//-------------------------------------------------------
|
||||
/* power
|
||||
*/
|
||||
#include "power/power_api.h"
|
||||
//#include "power/power_wakeup.h"
|
||||
//#include "power/power_reset.h"
|
||||
#include "power/power_port.h"
|
||||
#include "power/power_gate.h"
|
||||
|
||||
//-------------------------------------------------------
|
||||
/* other
|
||||
*/
|
||||
//#include "power/power_app.h"
|
||||
#include "power/power_compat.h"
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,35 @@
|
||||
#ifndef _RDEC_HW_H
|
||||
#define _RDEC_HW_H
|
||||
|
||||
#include "typedef.h"
|
||||
|
||||
typedef JL_QDEC_TypeDef RDEC;
|
||||
#define RDEC0 JL_QDEC0
|
||||
|
||||
#define RDEC_MAX_NUM 1
|
||||
#define RDEC_REG_BASE_ADDR JL_QDEC0
|
||||
#define RDEC_REG_OFFSET 0
|
||||
#define IRQ_RDECx_IDX_LIST IRQ_QDEC0_IDX
|
||||
|
||||
|
||||
//RDECx_CON reg
|
||||
#define RDEC_SPND 16 //bit16~bit31
|
||||
// #define RDEC_RESERVED 11 //bit11~bit15
|
||||
#define RDEC_INT_MODE 10
|
||||
#define RDEC_MODE 8 //bit8~bit9
|
||||
#define RDEC_PND 7
|
||||
#define RDEC_CPND 6
|
||||
// #define RDEC_RESERVED 2 //bit2~bit5
|
||||
#define RDEC_POL 1
|
||||
#define RDEC_EN 0
|
||||
|
||||
//RDECx_SMP 8bit
|
||||
//RDECx_DAT 8bit
|
||||
//RDECx_DBE 8bit
|
||||
|
||||
typedef enum : u8 {
|
||||
RDEC_0 = 0,
|
||||
RDEC_x,
|
||||
} rdec_dev;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,48 @@
|
||||
#ifndef ARCH_SDMMC_H
|
||||
#define ARCH_SDMMC_H
|
||||
|
||||
|
||||
#include "device/sdmmc/sdmmc.h"
|
||||
|
||||
struct sdmmc_platform_data {
|
||||
char port[6];
|
||||
u8 irq;
|
||||
u8 data_width;
|
||||
u8 priority;
|
||||
u8 detect_mode;
|
||||
u8 detect_io;
|
||||
u8 detect_io_level;
|
||||
u8 detect_time_interval;
|
||||
u32 detect_timeout;
|
||||
u32 speed;
|
||||
volatile u16 *sfr;
|
||||
int (*detect_func)(const struct sdmmc_platform_data *);
|
||||
void (*port_init)(const struct sdmmc_platform_data *, int mode);
|
||||
void (*power)(u8 on);
|
||||
};
|
||||
|
||||
#define SD0_PLATFORM_DATA_BEGIN(data) \
|
||||
static const struct sdmmc_platform_data data
|
||||
|
||||
|
||||
#define SD0_PLATFORM_DATA_END() \
|
||||
.irq = IRQ_SD0_IDX, \
|
||||
.sfr = (volatile u16 *)JL_SD0, \
|
||||
.port_init = sdmmc_0_port_init, \
|
||||
.detect_time_interval = 250, \
|
||||
.detect_timeout = 1000, \
|
||||
|
||||
extern const struct device_operations sd_dev_ops;
|
||||
|
||||
void sdmmc_0_port_init(const struct sdmmc_platform_data *, int mode);
|
||||
|
||||
int sdmmc_0_clk_detect(const struct sdmmc_platform_data *);
|
||||
int sdmmc_0_io_detect(const struct sdmmc_platform_data *);
|
||||
int sdmmc_0_cmd_detect(const struct sdmmc_platform_data *);
|
||||
int sdmmc_cmd_detect(const struct sdmmc_platform_data *data);
|
||||
|
||||
void sd_set_power(u8 enable);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,22 @@
|
||||
#ifndef __SFC_NORFLASH_API_H__
|
||||
#define __SFC_NORFLASH_API_H__
|
||||
|
||||
#include "typedef.h"
|
||||
#include "device.h"
|
||||
|
||||
int sfc_norflash_init(const struct dev_node *node, void *arg);
|
||||
int sfc_norflash_open(const char *name, struct device **device, void *arg);
|
||||
int sfc_norflash_read(struct device *device, void *buf, u32 len, u32 offset);
|
||||
int sfc_norflash_write(struct device *device, void *buf, u32 len, u32 offset);
|
||||
int sfc_norflash_ioctl(struct device *device, u32 cmd, u32 arg);
|
||||
|
||||
u32 sfc0_flash_addr2cpu_addr(u32 offset);
|
||||
u32 sfc_norflash_read_uuid(u8 *uuid);
|
||||
u8 *sfc_norflash_get_uuid(void);
|
||||
u32 sfc_norflash_erase_otp();
|
||||
u32 sfc_norflash_read_otp(void *buf, u32 len, u32 addr);
|
||||
u32 sfc_norflash_write_otp(const u8 *buf, u32 len, u32 addr);
|
||||
|
||||
void sfc_norflash_set_early_unenc_zone(void *_arg);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,49 @@
|
||||
#ifndef _SFC1_INTERFACE_H_
|
||||
#define _SFC1_INTERFACE_H_
|
||||
#include "typedef.h"
|
||||
#include "generic/ioctl.h"
|
||||
|
||||
enum SFC_DATA_WIDTH {
|
||||
SFC_DATA_WIDTH_2 = 2,
|
||||
SFC_DATA_WIDTH_4 = 4,
|
||||
};
|
||||
|
||||
enum SFC_READ_MODE {
|
||||
SFC_RD_OUTPUT = 0,
|
||||
SFC_RD_IO,
|
||||
SFC_RD_IO_CONTINUE,
|
||||
};
|
||||
|
||||
struct sfc_spi_platform_data {
|
||||
u8 spi_hw_index;
|
||||
enum SFC_DATA_WIDTH sfc_data_width;
|
||||
enum SFC_READ_MODE sfc_read_mode;
|
||||
u8 sfc_encry; //是否加密
|
||||
u16 sfc_clk_div; //时钟分频: sfc_fre = sys_clk / div;
|
||||
u32 unencry_start_addr; //不加密起始地址
|
||||
u32 unencry_size; //不加密大小
|
||||
};
|
||||
|
||||
#define SFC_SPI_PLATFORM_DATA_BEGIN(data) \
|
||||
const struct sfc_spi_platform_data data = {
|
||||
|
||||
#define SFC_SPI_PLATFORM_DATA_END() \
|
||||
};
|
||||
|
||||
|
||||
//sfc1 API:
|
||||
int sfc_spi_init(struct sfc_spi_platform_data *sfc_spi_data);
|
||||
int sfc_spi_open(void *sfc_spi_data);
|
||||
int sfc_spi_close(void);
|
||||
u32 sfc_spi_read_id(void);
|
||||
int sfc_spi_read(u32 addr, void *buf, u32 len);
|
||||
int sfc_spi_write_pages(u32 addr, void *buf, u32 len);
|
||||
int sfc_spi_eraser(u32 cmd, u32 addr);
|
||||
u32 sfc1_flash_addr2cpu_addr(u32 offset);
|
||||
u32 sfc1_cpu_addr2flash_addr(u32 offset);
|
||||
|
||||
void sfc_suspend(u32 enable_spi);
|
||||
void sfc_resume(u32 disable_spi);
|
||||
|
||||
void sfc1_suspend();
|
||||
#endif /* #ifndef _SFC1_INTERFACE_H_ */
|
||||
@@ -0,0 +1,28 @@
|
||||
#ifndef _SPI_HW_H_
|
||||
#define _SPI_HW_H_
|
||||
|
||||
#include "typedef.h"
|
||||
#include "generic/ioctl.h"
|
||||
|
||||
#define SUPPORT_SPI0 0 //是否使能SPI0
|
||||
#define SUPPORT_SPI1 1 //是否使能SPI1
|
||||
#define SPI1_SUPPORT_UNIDIR_4BIT 1 //spi 4bit
|
||||
#define SUPPORT_SPI2 1 //是否使能spi2
|
||||
#define SPI2_SUPPORT_UNIDIR_4BIT 1 //spi 4bit
|
||||
|
||||
typedef enum spi_index {
|
||||
HW_SPI0, //SPI0系统已使用
|
||||
HW_SPI1,
|
||||
HW_SPI2,
|
||||
HW_SPI_MAX_NUM,
|
||||
} hw_spi_dev;
|
||||
|
||||
enum spi_bit_mode {
|
||||
SPI_FIRST_BIT_MSB, //7,6,5,4,3,2,1,0
|
||||
SPI_FIRST_BIT_LSB, //0,1,2,3,4,5,6,7
|
||||
SPI_FIRST_BIT_BIT3, //3,2,1,0,7,6,5,4
|
||||
SPI_FIRST_BIT_BIT4, //4,5,6,7,0,1,2,3
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,28 @@
|
||||
#ifndef ASM_SPIFLASH_H
|
||||
#define ASM_SPIFLASH_H
|
||||
|
||||
|
||||
|
||||
#include "device/device.h"
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
extern const struct device_operations spiflash_dev_ops;
|
||||
extern const struct device_operations sfcflash_dev_ops;
|
||||
extern const struct device_operations sdfile_dev_ops;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,176 @@
|
||||
#ifndef _UART_DEV_H_
|
||||
#define _UART_DEV_H_
|
||||
|
||||
#include "typedef.h"
|
||||
#include "os/os_api.h"
|
||||
#include "jiffies.h"
|
||||
#include "irq.h"
|
||||
/* #include "jtime.h" */
|
||||
|
||||
#define CONFIG_ENABLE_UART_SEM 1
|
||||
#define SET_INTERRUPT ___interrupt
|
||||
#define irq_disable(x) bit_clr_ie(x)
|
||||
#define irq_enable(x) bit_set_ie(x)
|
||||
|
||||
#ifndef time_after
|
||||
#define time_after(a,b) (((long)(b) - (long)(a)) < 0)
|
||||
#endif
|
||||
|
||||
#ifndef time_before
|
||||
#define time_before(a,b) time_after(b,a)
|
||||
#endif
|
||||
|
||||
#ifndef MIN
|
||||
#define MIN(a, b) ((a) < (b) ? (a) : (b))
|
||||
#endif
|
||||
|
||||
#ifndef MAX
|
||||
#define MAX(a, b) ((a) > (b) ? (a) : (b))
|
||||
#endif
|
||||
|
||||
static inline u32 ut_get_jiffies(void)
|
||||
{
|
||||
#if 1
|
||||
return jiffies;
|
||||
#endif
|
||||
#if 0
|
||||
return Jtime_updata_jiffies();
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline u32 ut_msecs_to_jiffies(u32 msecs)
|
||||
{
|
||||
if (msecs >= 10) {
|
||||
msecs /= 10;
|
||||
} else if (msecs) {
|
||||
msecs = 1;
|
||||
}
|
||||
return msecs;
|
||||
}
|
||||
|
||||
#if CONFIG_ENABLE_UART_SEM
|
||||
typedef OS_SEM UT_Semaphore ;
|
||||
static inline void UT_OSSemCreate(UT_Semaphore *sem, u32 count)
|
||||
{
|
||||
os_sem_create(sem, count);
|
||||
}
|
||||
static inline void UT_OSSemPost(UT_Semaphore *sem)
|
||||
{
|
||||
os_sem_post(sem);
|
||||
}
|
||||
static inline u32 UT_OSSemPend(UT_Semaphore *sem, u32 timeout)
|
||||
{
|
||||
return os_sem_pend(sem, timeout);
|
||||
}
|
||||
static inline void UT_OSSemSet(UT_Semaphore *sem, u32 count)
|
||||
{
|
||||
os_sem_set(sem, count);
|
||||
}
|
||||
static inline void UT_OSSemClose(UT_Semaphore *sem)
|
||||
{
|
||||
|
||||
}
|
||||
static inline void ut_sleep()
|
||||
{
|
||||
os_time_dly(1);
|
||||
}
|
||||
|
||||
#else
|
||||
typedef volatile u32 UT_Semaphore;
|
||||
static inline void UT_OSSemCreate(UT_Semaphore *sem, u32 count)
|
||||
{
|
||||
*sem = count;
|
||||
}
|
||||
static inline void UT_OSSemPost(UT_Semaphore *sem)
|
||||
{
|
||||
(*sem)++;
|
||||
}
|
||||
static inline u32 UT_OSSemPend(UT_Semaphore *sem, u32 timeout)
|
||||
{
|
||||
u32 _timeout = timeout + ut_get_jiffies();
|
||||
extern void clr_wdt();
|
||||
while (1) {
|
||||
if (*sem) {
|
||||
(*sem) --;
|
||||
break;
|
||||
}
|
||||
if ((timeout != 0) && time_before(_timeout, ut_get_jiffies())) {
|
||||
return -1;
|
||||
}
|
||||
clr_wdt();
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
static inline void UT_OSSemSet(UT_Semaphore *sem, u32 count)
|
||||
{
|
||||
*sem = count;
|
||||
}
|
||||
static inline void UT_OSSemClose(UT_Semaphore *sem)
|
||||
{
|
||||
|
||||
}
|
||||
static inline void ut_sleep()
|
||||
{
|
||||
extern void clr_wdt();
|
||||
clr_wdt();
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
typedef void (*ut_isr_cbfun)(void *ut_bus, u32 status);
|
||||
struct uart_platform_data_t {
|
||||
u8 tx_pin; ///< 作为发送引脚的引脚号，可从参考gpio.h枚举中选，当引脚为空时，则填 -1
|
||||
u8 rx_pin; ///< 作为接收引脚的引脚号，可从参考gpio.h枚举中选，当引脚为空时，则填 -1
|
||||
void *rx_cbuf; ///< 如果使用中断DMA接收，则写入循环buf的首地址，ut中断使能；如果不使用，则写入NULL，无中断
|
||||
u32 rx_cbuf_size; ///< 循环buf的大小,必须为2的多少几次幂，如果不用循环buf，该值无效，可写NULL
|
||||
u32 frame_length; ///< 产生RT中断的字节数，如无中断，该值无效
|
||||
u32 rx_timeout; ///< 产生OT中断的时间值，单位ms，如无中断，该值无效
|
||||
ut_isr_cbfun isr_cbfun; ///< ut中断的回调函数句柄，不用回调函数则写入NULL，如无中断，句柄无效
|
||||
void *argv; ///< ut中断的回调函数的一个扩展形参，可供用户设定，如无回调函数，此参数无效
|
||||
u32 is_9bit: 1; ///< ut九位模式使能位，0：关闭；1：使能
|
||||
u32 baud: 24; ///< ut的波特率
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief 循环buf结构体类型定义
|
||||
*/
|
||||
typedef struct {
|
||||
u8 *buffer; ///<循环buf的首地址
|
||||
u32 buf_size; ///<循环buf的大小
|
||||
u32 buf_in; ///<循环buf的写偏移量
|
||||
u32 buf_out; ///<循环buf的读偏移量
|
||||
} KFIFO;
|
||||
|
||||
enum {
|
||||
UT_TX = 1,
|
||||
UT_RX,
|
||||
UT_RX_OT
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief ut初始化函数的返回结构体，含各函数指针，供外部使用
|
||||
*/
|
||||
typedef struct {
|
||||
ut_isr_cbfun isr_cbfun; ///< ut中断的回调函数句柄，不用回调函数则写入NULL，如无中断，句柄无效
|
||||
void *argv; ///< ut中断的回调函数的一个扩展形参,在此返回
|
||||
void (*putbyte)(char a); ///< ut发送一个byte
|
||||
u8(*getbyte)(u8 *buf, u32 timeout); ///< ut接收一个byte，buf：字节存放地址；timeout：超时时间，单位ms；返回0：失败；返回1：成功
|
||||
u32(*read)(u8 *inbuf, u32 len, u32 timeout); ///< ut接收一个字符串，inbuf：字符串存放首地址；len：预接收长度；timeout：超时时间，单位ms；返回实际接收的长度
|
||||
void (*write)(const u8 *outbuf, u32 len); ///< ut发送一个字符串，outbuf：字符串首地址；len：发送的字符串长度；
|
||||
void (*set_baud)(u32 baud); ///< ut设置波特率，baud：波特率值
|
||||
u32 frame_length;
|
||||
u32 rx_timeout;
|
||||
KFIFO kfifo; ///< ut用的循环buf结构体的指针
|
||||
UT_Semaphore sem_rx;
|
||||
UT_Semaphore sem_tx;
|
||||
u32(*get_data_len)(void);
|
||||
} uart_bus_t;
|
||||
|
||||
|
||||
uart_bus_t *uart_dev_open(const struct uart_platform_data_t *arg);
|
||||
u32 uart_dev_close(uart_bus_t *ut);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif
|
||||
|
||||
|
||||
@@ -0,0 +1,73 @@
|
||||
#ifndef _USB_HW_H_
|
||||
#define _USB_HW_H_
|
||||
#include "typedef.h"
|
||||
#include "generic/ioctl.h"
|
||||
|
||||
|
||||
#define USB_MAX_HW_EPNUM 5
|
||||
|
||||
/* #define ep_regs JL_USB_EP_TypeDef */
|
||||
typedef struct {
|
||||
volatile u32 TXMAXP;
|
||||
volatile u32 TXCSR1;
|
||||
volatile u32 TXCSR2;
|
||||
volatile u32 RXMAXP;
|
||||
volatile u32 RXCSR1;
|
||||
volatile u32 RXCSR2;
|
||||
volatile const u32 RXCOUNT1;
|
||||
volatile const u32 RXCOUNT2;
|
||||
volatile u32 TXTYPE;
|
||||
volatile u32 TXINTERVAL;
|
||||
volatile u32 RXTYPE;
|
||||
volatile u32 RXINTERVAL;
|
||||
u32 RESERVED[0xd0 / 4];
|
||||
} ep_regs;
|
||||
|
||||
|
||||
|
||||
#define PHY_ON 0
|
||||
#define LOW_SPEED 1
|
||||
#define USB_NRST 2
|
||||
#define TM1 3
|
||||
#define CID 4
|
||||
#define VBUS 5
|
||||
#define USB_TEST 6
|
||||
#define PDCHKDP 9
|
||||
#define SOFIE 10
|
||||
#define SIEIE 11
|
||||
#define CLR_SOF_PND 12
|
||||
#define SOF_PND 13
|
||||
#define SIE_PND 14
|
||||
#define CHKDPO 15
|
||||
#define DM_SE 16
|
||||
#define DP_SE 17
|
||||
|
||||
#define MC_RNW 14
|
||||
#define MACK 15
|
||||
|
||||
#define DPOUT 0
|
||||
#define DMOUT 1
|
||||
#define DPIE 2
|
||||
#define DMIE 3
|
||||
#define DPPU 4
|
||||
#define DMPU 5
|
||||
#define DPPD 6
|
||||
#define DMPD 7
|
||||
#define DPDIE 8
|
||||
#define DMDIE 9
|
||||
#define DPDIEH 10
|
||||
#define DMDIEH 11
|
||||
#define IO_MODE 12
|
||||
#define SR 13
|
||||
#define IO_PU_MODE 14
|
||||
|
||||
|
||||
|
||||
enum {
|
||||
USB0,
|
||||
};
|
||||
#define USB_MAX_HW_NUM 1
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,6 @@
|
||||
#ifndef ___WDT_H__
|
||||
#define ___WDT_H__
|
||||
|
||||
#include "asm/power_interface.h"
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user