huxi
90 lines
2.1 KiB
C
90 lines
2.1 KiB
C
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//===============================================================================//
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//
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// input IO define
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//
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//===============================================================================//
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#define PA0_IN 1
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#define PA1_IN 2
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#define PA2_IN 3
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#define PA3_IN 4
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#define PA4_IN 5
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#define PA5_IN 6
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#define PA6_IN 7
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#define PA7_IN 8
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#define PA8_IN 9
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#define PA9_IN 10
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#define PA10_IN 11
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#define PA11_IN 12
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#define PA12_IN 13
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#define PA13_IN 14
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#define PB0_IN 15
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#define PB1_IN 16
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#define PB2_IN 17
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#define PB3_IN 18
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#define PB4_IN 19
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#define PB5_IN 20
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#define PB6_IN 21
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#define PB7_IN 22
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#define PB8_IN 23
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#define PC0_IN 24
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#define PC1_IN 25
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#define PC2_IN 26
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#define PC3_IN 27
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#define PC4_IN 28
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#define PC5_IN 29
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#define PC6_IN 30
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#define PC7_IN 31
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#define PC8_IN 32
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#define PC9_IN 33
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#define PC10_IN 34
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#define PC11_IN 35
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#define USBDP_IN 36
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#define USBDM_IN 37
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#define PP0_IN 38
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//===============================================================================//
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//
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// function input select sfr
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//
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//===============================================================================//
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typedef struct {
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__RW __u8 FI_GP_ICH0;
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__RW __u8 FI_GP_ICH1;
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__RW __u8 FI_GP_ICH2;
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__RW __u8 FI_GP_ICH3;
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__RW __u8 FI_GP_ICH4;
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__RW __u8 FI_GP_ICH5;
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__RW __u8 FI_SD0_CMD;
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__RW __u8 FI_SD0_DA0;
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__RW __u8 FI_SD0_DA1;
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__RW __u8 FI_SD0_DA2;
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__RW __u8 FI_SD0_DA3;
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__RW __u8 FI_SPI1_CLK;
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__RW __u8 FI_SPI1_DA0;
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__RW __u8 FI_SPI1_DA1;
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__RW __u8 FI_SPI1_DA2;
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__RW __u8 FI_SPI1_DA3;
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__RW __u8 FI_SPI2_CLK;
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__RW __u8 FI_SPI2_DA0;
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__RW __u8 FI_SPI2_DA1;
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__RW __u8 FI_SPI2_DA2;
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__RW __u8 FI_SPI2_DA3;
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__RW __u8 FI_IIC0_SCL;
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__RW __u8 FI_IIC0_SDA;
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__RW __u8 FI_UART0_RX;
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__RW __u8 FI_UART1_RX;
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__RW __u8 FI_UART2_RX;
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__RW __u8 FI_QDEC0_A;
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__RW __u8 FI_QDEC0_B;
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__RW __u8 FI_CHAIN_IN0;
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__RW __u8 FI_CHAIN_IN1;
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__RW __u8 FI_CHAIN_IN2;
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__RW __u8 FI_CHAIN_IN3;
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__RW __u8 FI_CHAIN_RST;
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__RW __u8 FI_TOTAL;
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} JL_IMAP_TypeDef;
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#define JL_IMAP_BASE (ls_base + map_adr(0x3a, 0x00))
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#define JL_IMAP ((JL_IMAP_TypeDef *)JL_IMAP_BASE)
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