huxi
746 lines
20 KiB
C
746 lines
20 KiB
C
// *INDENT-OFF*
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#include "app_config.h"
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#include "audio_config_def.h"
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/* ================================== BR35 SDK memory ============================================
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_______________
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| update |
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|_______________|___ RAM_LIMIT_H
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| HEAP |
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|_______________|___ data_code_pc_limit_H
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| audio overlay |
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|_______________|
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| data_code |
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|_______________|___ data_code_pc_limit_L
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| bss |
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|_______________|
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| data |
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|_______________|
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| TLB |
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|_______________|
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| irq_stack |
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|_______________|
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| boot info |
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|_______________|___ RAM_LIMIT_L
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|rom export ram |
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|_______________|___ 0x100200
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| isr base |
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|_______________|___ 0x100000
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=============================================================================================== */
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#include "maskrom_stubs.ld"
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EXTERN(
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_start
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#include "sdk_used_list.c"
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);
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UPDATA_SIZE = 0x200;
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UPDATA_BEG = _RAM_LIMIT_H - UPDATA_SIZE;
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UPDATA_BREDR_BASE_BEG = 0x4000000;
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RAM_LIMIT_L = _MASK_EXPORT_MEM_BEGIN + _MASK_EXPORT_MEM_SIZE;
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RAM_LIMIT_H = UPDATA_BEG;
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PHY_RAM_SIZE = RAM_LIMIT_H - RAM_LIMIT_L;
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//from mask export
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ISR_BASE = _IRQ_MEM_ADDR;
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ROM_RAM_SIZE = _MASK_EXPORT_MEM_SIZE;// _MASK_MEM_SIZE;
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ROM_RAM_BEG = _MASK_EXPORT_MEM_BEGIN;//_MASK_MEM_BEGIN;
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RAM0_BEG = RAM_LIMIT_L;
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RAM0_END = RAM_LIMIT_H;
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RAM0_SIZE = RAM0_END - RAM0_BEG;
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RAM1_BEG = RAM_LIMIT_L;
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RAM1_END = RAM0_BEG;
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RAM1_SIZE = RAM1_END - RAM1_BEG;
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CODE_BEG = 0xC000100;
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PSRAM_BEGIN = 0x8000000;
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#if !TCFG_PSRAM_DEV_ENABLE
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FREE_DACHE_WAY = TCFG_FREE_DCACHE_WAY;
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FREE_IACHE_WAY = TCFG_FREE_ICACHE_WAY;
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DCACHE_RAM_SIZE = FREE_DACHE_WAY*8K;
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ICACHE_RAM_SIZE = FREE_IACHE_WAY*8K;
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PSRAM_SIZE = 0;
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#else
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// 使能psram时,默认不将cache当ram用
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FREE_DACHE_WAY = 0;
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FREE_IACHE_WAY = 0;
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DCACHE_RAM_SIZE = 0;
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ICACHE_RAM_SIZE = 0;
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PSRAM_SIZE = TCFG_PSRAM_SIZE;
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#endif
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PSRAM_END = PSRAM_BEGIN + PSRAM_SIZE;
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//=============== About BT RAM ===================
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//CONFIG_BT_RX_BUFF_SIZE = (1024 * 18);
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MEMORY
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{
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code0(rx) : ORIGIN = CODE_BEG, LENGTH = CONFIG_FLASH_SIZE
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ram0(rwx) : ORIGIN = RAM0_BEG, LENGTH = RAM0_SIZE
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//ram1 - 用于volatile-heap
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//ram1(rwx) : ORIGIN = RAM1_BEG, LENGTH = RAM1_SIZE
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psram(rwx) : ORIGIN = PSRAM_BEGIN, LENGTH = PSRAM_SIZE
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dcache_ram(rw) : ORIGIN = 0x370000+((4-FREE_DACHE_WAY)*8K), LENGTH = DCACHE_RAM_SIZE
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icache_ram(rw) : ORIGIN = 0x3C0000+((4-FREE_IACHE_WAY)*8K), LENGTH = ICACHE_RAM_SIZE
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}
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ENTRY(_start)
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SECTIONS
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{
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. = ORIGIN(ram0);
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.boot_info ALIGN(32):
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{
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*(.boot_info)
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. = ALIGN(256);
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// 需要避免与uboot和maskrom冲突
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*(.debug_record)
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. = ALIGN(4);
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} > ram0
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.irq_stack ALIGN(32):
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{
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_cpu0_sstack_begin = .;
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*(.cpu0_stack)
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_cpu0_sstack_end = .;
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. = ALIGN(4);
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} > ram0
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// os bss依然存放在bss段
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//.os_data_bss ALIGN(4):
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//{
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// *(.os.data.bss)
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//} > ram0
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//TLB 起始需要4K 对齐；
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.mmu_tlb ALIGN(0x1000):
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{
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*(.mmu_tlb_segment);
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} > ram0
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.bss ALIGN(32):SUBALIGN(4)
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{
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. = ALIGN(4);
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/* #include "system/system_lib_bss.ld" */
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. = ALIGN(4);
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*(.bss)
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. = ALIGN(4);
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*(.volatile_ram)
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*(.btstack_pool)
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*(.mem_heap)
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#if !TCFG_PSRAM_DEV_ENABLE
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*(.memp_memory_x)
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#endif
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. = ALIGN(4);
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lp_data_save_bss_begin = .;
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*(.power_driver.data.bss.overlay)
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#if DAC_OBUF_OVERLAY_LP_BSS_EN
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lp_data_save_bss_src_end = .;
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. = (lp_data_save_bss_begin + 4800); // 可以在dac_overlay_malloc()中打印获取size
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#endif
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lp_data_save_bss_end = .;
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lp_data_save_bss_size = lp_data_save_bss_end - lp_data_save_bss_begin;
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. = ALIGN(4);
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*(.usb.data.bss.exchange)
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. = ALIGN(4);
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*(.non_volatile_ram)
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. = ALIGN(4);
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#if ((!TCFG_ICACHE_RUN_BT_STATIC_RAM) && (!TCFG_DCACHE_RUN_BT_STATIC_RAM))
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#include "btctrler/btctler_lib_bss.ld"
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#endif
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#include "btctrler/crypto/bss.ld"
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. = ALIGN(32);
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} > ram0
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.data ALIGN(32):SUBALIGN(4)
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{
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//common bank code addr
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common_code_run_addr = .;
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//cpu start
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. = ALIGN(4);
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*(.data_magic)
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. = ALIGN(4);
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__a2dp_movable_slot_start = .;
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*(.movable.slot.1);
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__a2dp_movable_slot_end = .;
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. = ALIGN(4);
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app_mode_begin = .;
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KEEP(*(.app_mode))
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app_mode_end = .;
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. = ALIGN(4);
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/* #include "system/system_lib_data.ld" */
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#include "btctrler/crypto/data.ld"
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. = ALIGN(4);
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#include "btctrler/btctler_lib_data.ld"
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. = ALIGN(4);
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} > ram0
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.data_code ALIGN(32):SUBALIGN(4)
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{
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data_code_pc_limit_begin = .;
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*(.must_ram_code)
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*(.cache)
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*(.flushinv_icache)
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#if (!TCFG_ICACHE_RUN_DATA_CODE)
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#include "sdk_ram_code.ld"
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#endif
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. = ALIGN(4);
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} > ram0
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__report_overlay_begin = .;
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#include "app_overlay.ld"
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//bank code addr
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bank_code_run_addr = .;
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OVERLAY : AT(0x300000) SUBALIGN(4)
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{
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.overlay_bank0
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{
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*(.bank.code.0*)
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*(.bank.const.0*)
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. = ALIGN(4);
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}
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.overlay_bank1
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{
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*(.bank.code.1*)
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*(.bank.const.1*)
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. = ALIGN(4);
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}
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.overlay_bank2
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{
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*(.bank.code.2*)
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*(.bank.const.2*)
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*(.bank.ecdh.*)
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. = ALIGN(4);
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}
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.overlay_bank3
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{
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*(.bank.code.3*)
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*(.bank.const.3*)
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*(.bank.enc.*)
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. = ALIGN(4);
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}
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.overlay_bank4
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{
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*(.bank.code.4*)
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*(.bank.const.4*)
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. = ALIGN(4);
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}
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.overlay_bank5
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{
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*(.bank.code.5*)
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*(.bank.const.5*)
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. = ALIGN(4);
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}
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.overlay_bank6
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{
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*(.bank.code.6*)
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*(.bank.const.6*)
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. = ALIGN(4);
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}
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.overlay_bank7
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{
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*(.bank.code.7*)
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*(.bank.const.7*)
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. = ALIGN(4);
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}
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.overlay_bank8
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{
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*(.bank.code.8*)
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*(.bank.const.8*)
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. = ALIGN(4);
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}
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.overlay_bank9
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{
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*(.bank.code.9*)
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*(.bank.const.9*)
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. = ALIGN(4);
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}
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} > ram0
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data_code_pc_limit_end = .;
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__report_overlay_end = .;
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_HEAP_BEGIN = . ;
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#if CONFIG_LCD_BUF_STATIC_RAM_LEN
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_HEAP_END = RAM0_END - CONFIG_LCD_BUF_STATIC_RAM_LEN;
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#else
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_HEAP_END = RAM0_END;
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#endif
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_LCD_BUF_STATIC_START = _HEAP_END;
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_LCD_BUF_STATIC_END = RAM0_END;
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. = ORIGIN(psram);
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.ps_ram_data_code ALIGN(32):
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{
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*(.psram_data)
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*(.psram_code)
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. = ALIGN(4);
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} > psram
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.ps_ram_bss ALIGN(32):
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{
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*(.psram_bss)
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#if TCFG_PSRAM_DEV_ENABLE
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*(.memp_memory_x)
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#endif
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. = ALIGN(4);
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} > psram
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.ps_ram_noinit ALIGN(32):
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{
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*(.psram_noinit)
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. = ALIGN(4);
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} > psram
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_PSRAM_HEAP_BEGIN = .;
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_PSRAM_HEAP_END = PSRAM_END;
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. = ORIGIN(code0);
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.text ALIGN(4):SUBALIGN(4)
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{
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PROVIDE(text_rodata_begin = .);
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*(.startup.text)
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*(.text)
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. = ALIGN(4);
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update_target_begin = .;
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PROVIDE(update_target_begin = .);
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KEEP(*(.update_target))
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update_target_end = .;
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PROVIDE(update_target_end = .);
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. = ALIGN(4); // must at tail, make rom_code size align 4
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PROVIDE(text_rodata_end = .);
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. = ALIGN(4);
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_SPI_CODE_CORE_START = . ;
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*(.spi_code_core)
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. = ALIGN(4);
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_SPI_CODE_CORE_END = . ;
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. = ALIGN(4);
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_SPI_CODE_FLASH_START = . ;
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*(.spi_code_flash)
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. = ALIGN(4);
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_SPI_CODE_FLASH_END = . ;
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. = ALIGN(4);
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_SPI_CODE_OTP_START = . ;
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*(.spi_code_otp)
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. = ALIGN(4);
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_SPI_CODE_OTP_END = . ;
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. = ALIGN(4);
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_SFC_DTR_CODE_START = . ;
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*(.sfc_dtr_code)
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. = ALIGN(4);
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_SFC_DTR_CODE_END = . ;
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clock_critical_handler_begin = .;
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KEEP(*(.clock_critical_txt))
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clock_critical_handler_end = .;
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hsb_critical_handler_begin = .;
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KEEP(*(.hsb_critical_txt))
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hsb_critical_handler_end = .;
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lsb_critical_handler_begin = .;
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KEEP(*(.lsb_critical_txt))
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lsb_critical_handler_end = .;
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chargestore_handler_begin = .;
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KEEP(*(.chargestore_callback_txt))
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chargestore_handler_end = .;
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. = ALIGN(4);
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app_msg_handler_begin = .;
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KEEP(*(.app_msg_handler))
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app_msg_handler_end = .;
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. = ALIGN(4);
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app_msg_prob_handler_begin = .;
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KEEP(*(.app_msg_prob_handler))
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app_msg_prob_handler_end = .;
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. = ALIGN(4);
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app_charge_handler_begin = .;
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KEEP(*(.app_charge_handler.0))
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KEEP(*(.app_charge_handler.1))
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app_charge_handler_end = .;
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. = ALIGN(4);
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scene_ability_begin = .;
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KEEP(*(.scene_ability))
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scene_ability_end = .;
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#include "media/framework/section_text.ld"
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. = ALIGN(4);
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tool_interface_begin = .;
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KEEP(*(.tool_interface))
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tool_interface_end = .;
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. = ALIGN(4);
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effects_online_adjust_begin = .;
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KEEP(*(.effects_online_adjust))
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effects_online_adjust_end = .;
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. = ALIGN(4);
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tws_tone_cb_begin = .;
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KEEP(*(.tws_tone_callback))
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tws_tone_cb_end = .;
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. = ALIGN(4);
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vm_reg_id_begin = .;
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KEEP(*(.vm_manage_id_text))
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vm_reg_id_end = .;
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. = ALIGN(4);
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*(.gpio.text.cache.L2)
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*(.LED_code)
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*(.LED_const)
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. = ALIGN(4);
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__fm_movable_region_start = .;
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*(.movable.region.1)
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__fm_movable_region_end = .;
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__fm_movable_region_size = ABSOLUTE(__fm_movable_region_end - __fm_movable_region_start);
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. = ALIGN(4);
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__bt_movable_region_start = .;
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*(.movable.region.2)
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__bt_movable_region_end = .;
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__bt_movable_region_size = ABSOLUTE(__bt_movable_region_end - __bt_movable_region_start);
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. = ALIGN(4);
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__aac_movable_region_start = .;
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*(.movable.region.3)
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__aac_movable_region_end = .;
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__aac_movable_region_size = ABSOLUTE(__aac_movable_region_end - __aac_movable_region_start);
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. = ALIGN(4);
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*(.bt_aac_dec_const)
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*(.bt_aac_dec_sparse_const)
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. = ALIGN(4);
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__aec_movable_region_start = .;
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*(.movable.region.4)
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__aec_movable_region_end = .;
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__aec_movable_region_size = ABSOLUTE(__aec_movable_region_end - __aec_movable_region_start);
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. = ALIGN(4);
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__mic_eff_movable_region_start = .;
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*(.movable.region.5)
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__mic_eff_movable_region_end = .;
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__mic_eff_movable_region_size = ABSOLUTE(__mic_eff_movable_region_end - __mic_eff_movable_region_start);
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/********maskrom arithmetic ****/
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*(.opcore_table_maskrom)
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*(.bfilt_table_maskroom)
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*(.bfilt_code)
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*(.bfilt_const)
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/********maskrom arithmetic end****/
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. = ALIGN(4);
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__VERSION_BEGIN = .;
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KEEP(*(.sys.version))
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__VERSION_END = .;
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*(.noop_version)
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. = ALIGN(4);
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__a2dp_text_cache_L2_start = .;
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*(.movable.region.1);
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. = ALIGN(4);
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__a2dp_text_cache_L2_end = .;
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. = ALIGN(4);
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/* #include "system/system_lib_text.ld" */
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#include "btctrler/crypto/text.ld"
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#include "btctrler/btctler_lib_text.ld"
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. = ALIGN(4);
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_record_handle_begin = .;
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PROVIDE(record_handle_begin = .);
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KEEP(*(.debug_record_handle_ops))
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_record_handle_end = .;
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PROVIDE(record_handle_end = .);
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. = ALIGN(32);
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} > code0
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#if defined CONFIG_CXX_SUPPORT
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PROVIDE(ctors_count = _ctors_end - _ctors_begin);
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#endif
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. = ORIGIN(dcache_ram);
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.dcache_ram_data ALIGN(32):SUBALIGN(4)
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{
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*(.dch_ram_data)
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. = ALIGN(4);
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} > dcache_ram
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.dcache_ram_bss ALIGN(32):SUBALIGN(4)
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{
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#if (TCFG_DCACHE_RUN_BT_STATIC_RAM)
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#include "btctrler/btctler_lib_bss.ld"
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#endif
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*(.dcache_bss)
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*(.dch_ram_bss)
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. = ALIGN(4);
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// 放最后面
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dcache_ram_bss_remain_begin = .;
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. = ORIGIN(dcache_ram) + LENGTH(dcache_ram);
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dcache_ram_bss_remain_end = .;
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. = ALIGN(4);
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} > dcache_ram
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|
|
. = ORIGIN(icache_ram);
|
|
.icache_ram_data_code ALIGN(32):SUBALIGN(4)
|
|
{
|
|
icache_ram_data_code_pc_limit_begin = .;
|
|
*(.ich_ram_code)
|
|
#if (TCFG_ICACHE_RUN_DATA_CODE)
|
|
#include "sdk_ram_code.ld"
|
|
*(.power_driver.text.cache.L1)
|
|
#endif
|
|
. = ALIGN(4);
|
|
*(.icache_code)
|
|
. = ALIGN(4);
|
|
icache_ram_data_code_pc_limit_end = .;
|
|
} > icache_ram
|
|
.icache_ram_bss ALIGN(32):SUBALIGN(4)
|
|
{
|
|
*(.ich_ram_bss)
|
|
#if (TCFG_ICACHE_RUN_BT_STATIC_RAM)
|
|
#include "btctrler/btctler_lib_bss.ld"
|
|
#endif
|
|
. = ALIGN(4);
|
|
|
|
// 放最后面
|
|
icache_ram_bss_remain_begin = .;
|
|
. = ORIGIN(icache_ram) + LENGTH(icache_ram);
|
|
icache_ram_bss_remain_end = .;
|
|
. = ALIGN(4);
|
|
} > icache_ram
|
|
}
|
|
|
|
#include "app.ld"
|
|
#include "update/update.ld"
|
|
#include "btstack/btstack_lib.ld"
|
|
#include "driver/cpu/br35/driver_lib.ld"
|
|
#include "utils/utils_lib.ld"
|
|
#include "ui/ui.ld"
|
|
#ifdef CONFIG_AUDIO_ENABLE
|
|
#include "cvp/audio_cvp_lib.ld"
|
|
#include "media/media_lib.c"
|
|
#endif
|
|
|
|
#if CONFIG_JL_UI_ENABLE
|
|
/* #include "jlui/ui.ld" */
|
|
#endif
|
|
|
|
#include "system/port/br35/system_lib.ld" //Note: 为保证各段对齐, 系统ld文件必须放在最后include位置
|
|
|
|
//================== mmu tlb addr check ======================
|
|
// mmu tlb的位置不合理,可能会由于对齐产生较大的内存空隙(空隙无法使用)
|
|
ASSERT(ADDR(.mmu_tlb) <= 0x101000,"mmu tlb location unreasonable !!!");
|
|
|
|
//================== cache ram size check ======================
|
|
spi_code_size = _SPI_CODE_FLASH_END - _SPI_CODE_CORE_START;
|
|
ASSERT(FREE_DACHE_WAY <= 3,"cache ram size config err !!!");
|
|
ASSERT(FREE_IACHE_WAY <= 3,"cache ram size config err !!!");
|
|
// 不能关闭太多icache,否则会导致无法使用spi code load to cache功能(icache空间不够装spi代码)
|
|
ASSERT(spi_code_size <= ((4 - FREE_IACHE_WAY) * 8K),"icache size less than spi code size !!!");
|
|
|
|
//================== Section Info Export ====================//
|
|
text_begin = ADDR(.text);
|
|
text_size = SIZEOF(.text);
|
|
text_end = text_begin + text_size;
|
|
ASSERT((text_size % 4) == 0,"!!! text_size Not Align 4 Bytes !!!");
|
|
|
|
bss_begin = ADDR(.bss);
|
|
bss_size = SIZEOF(.bss);
|
|
bss_end = bss_begin + bss_size;
|
|
ASSERT((bss_size % 4) == 0,"!!! bss_size Not Align 4 Bytes !!!");
|
|
|
|
boot_info_addr = ADDR(.boot_info);
|
|
boot_info_size = SIZEOF(.boot_info);
|
|
ASSERT(boot_info_size >= 128,"!!! boot_info_size must larger than 128 Bytes !!!");
|
|
|
|
data_addr = ADDR(.data);
|
|
data_begin = text_begin + text_size;
|
|
data_size = SIZEOF(.data);
|
|
ASSERT((data_size % 4) == 0,"!!! data_size Not Align 4 Bytes !!!");
|
|
|
|
data_code_addr = ADDR(.data_code);
|
|
data_code_begin = data_begin + data_size;
|
|
data_code_size = SIZEOF(.data_code);
|
|
ASSERT((data_code_size % 4) == 0,"!!! data_code_size Not Align 4 Bytes !!!");
|
|
|
|
//================ OVERLAY Code Info Export ==================//
|
|
#ifndef CONFIG_CODE_MOVABLE_ENABLE
|
|
aec_addr = ADDR(.overlay_aec);
|
|
aec_begin = data_code_begin + data_code_size;
|
|
aec_size = SIZEOF(.overlay_aec);
|
|
|
|
aac_addr = ADDR(.overlay_aac);
|
|
aac_begin = aec_begin + aec_size;
|
|
aac_size = SIZEOF(.overlay_aac);
|
|
#endif
|
|
|
|
/*
|
|
lc3_addr = ADDR(.overlay_lc3);
|
|
lc3_begin = aac_begin + aac_size;
|
|
lc3_size = SIZEOF(.overlay_lc3);
|
|
*/
|
|
|
|
//================ psram ==================//
|
|
#ifndef CONFIG_CODE_MOVABLE_ENABLE
|
|
ps_ram_data_code_begin = aac_begin + aac_size;
|
|
#else
|
|
ps_ram_data_code_begin = data_code_begin + data_code_size;
|
|
#endif
|
|
ps_ram_data_code_addr = ADDR(.ps_ram_data_code);
|
|
ps_ram_data_code_size = SIZEOF(.ps_ram_data_code);
|
|
|
|
//================ dcache ==================//
|
|
dcache_ram_bss_begin = ADDR(.dcache_ram_bss);
|
|
dcache_ram_bss_size = SIZEOF(.dcache_ram_bss);
|
|
dcache_ram_bss_end = dcache_ram_bss_begin + dcache_ram_bss_size;
|
|
ASSERT((dcache_ram_bss_size % 4) == 0,"!!! dcache_ram_bss_size Not Align 4 Bytes !!!");
|
|
|
|
dcache_ram_data_addr = ADDR(.dcache_ram_data);
|
|
dcache_ram_data_begin = ps_ram_data_code_begin + ps_ram_data_code_size;
|
|
dcache_ram_data_size = SIZEOF(.dcache_ram_data);
|
|
ASSERT((dcache_ram_data_size % 4) == 0,"!!! dcache_ram_data_size Not Align 4 Bytes !!!");
|
|
|
|
//================ icache ==================//
|
|
icache_ram_bss_begin = ADDR(.icache_ram_bss);
|
|
icache_ram_bss_size = SIZEOF(.icache_ram_bss);
|
|
icache_ram_bss_end = icache_ram_bss_begin + icache_ram_bss_size;
|
|
ASSERT((icache_ram_bss_size % 4) == 0,"!!! icache_ram_bss_size Not Align 4 Bytes !!!");
|
|
|
|
icache_ram_data_code_addr = ADDR(.icache_ram_data_code);
|
|
icache_ram_data_code_begin = dcache_ram_data_begin + dcache_ram_data_size;
|
|
icache_ram_data_code_size = SIZEOF(.icache_ram_data_code);
|
|
ASSERT((icache_ram_data_code_size % 4) == 0,"!!! icache_ram_data_code_size Not Align 4 Bytes !!!");
|
|
|
|
|
|
//================ BANK ==================//
|
|
bank_code_load_addr = icache_ram_data_code_begin + icache_ram_data_code_size;
|
|
|
|
/* moveable_addr = ADDR(.overlay_moveable) ; */
|
|
/* moveable_size = SIZEOF(.overlay_moveable) ; */
|
|
//===================== HEAP Info Export =====================//
|
|
|
|
ASSERT(CONFIG_FLASH_SIZE > text_size,"check sdk_config.h CONFIG_FLASH_SIZE < text_size");
|
|
ASSERT(_HEAP_BEGIN >= bss_begin,"_HEAP_BEGIN < bss_begin");
|
|
ASSERT(_HEAP_BEGIN >= data_addr,"_HEAP_BEGIN < data_addr");
|
|
ASSERT(_HEAP_BEGIN >= data_code_addr,"_HEAP_BEGIN < data_code_addr");
|
|
//ASSERT(_HEAP_BEGIN >= moveable_slot_addr,"_HEAP_BEGIN < moveable_slot_addr");
|
|
//ASSERT(_HEAP_BEGIN >= __report_overlay_begin,"_HEAP_BEGIN < __report_overlay_begin");
|
|
|
|
PROVIDE(HEAP_BEGIN = _HEAP_BEGIN);
|
|
PROVIDE(HEAP_END = _HEAP_END);
|
|
_MALLOC_SIZE = _HEAP_END - _HEAP_BEGIN;
|
|
PROVIDE(MALLOC_SIZE = _HEAP_END - _HEAP_BEGIN);
|
|
|
|
ASSERT(MALLOC_SIZE >= 0x8000, "heap space too small !")
|
|
|
|
//============================================================//
|
|
//=== report section info begin:
|
|
//============================================================//
|
|
report_text_beign = ADDR(.text);
|
|
report_text_size = SIZEOF(.text);
|
|
report_text_end = report_text_beign + report_text_size;
|
|
|
|
report_mmu_tlb_begin = ADDR(.mmu_tlb);
|
|
report_mmu_tlb_size = SIZEOF(.mmu_tlb);
|
|
report_mmu_tlb_end = report_mmu_tlb_begin + report_mmu_tlb_size;
|
|
|
|
report_boot_info_begin = ADDR(.boot_info);
|
|
report_boot_info_size = SIZEOF(.boot_info);
|
|
report_boot_info_end = report_boot_info_begin + report_boot_info_size;
|
|
|
|
report_irq_stack_begin = ADDR(.irq_stack);
|
|
report_irq_stack_size = SIZEOF(.irq_stack);
|
|
report_irq_stack_end = report_irq_stack_begin + report_irq_stack_size;
|
|
|
|
report_data_begin = ADDR(.data);
|
|
report_data_size = SIZEOF(.data);
|
|
report_data_end = report_data_begin + report_data_size;
|
|
|
|
report_bss_begin = ADDR(.bss);
|
|
report_bss_size = SIZEOF(.bss);
|
|
report_bss_end = report_bss_begin + report_bss_size;
|
|
|
|
report_data_code_begin = ADDR(.data_code);
|
|
report_data_code_size = SIZEOF(.data_code);
|
|
report_data_code_end = report_data_code_begin + report_data_code_size;
|
|
|
|
report_overlay_begin = __report_overlay_begin;
|
|
report_overlay_size = __report_overlay_end - __report_overlay_begin;
|
|
report_overlay_end = __report_overlay_end;
|
|
|
|
report_heap_beign = _HEAP_BEGIN;
|
|
report_heap_size = _HEAP_END - _HEAP_BEGIN;
|
|
report_heap_end = _HEAP_END;
|
|
|
|
ps_ram_bss_addr = ADDR(.ps_ram_bss);
|
|
ps_ram_bss_size = SIZEOF(.ps_ram_bss);
|
|
|
|
ps_ram_noinit_addr = ADDR(.ps_ram_noinit);
|
|
ps_ram_noinit_size = SIZEOF(.ps_ram_noinit);
|
|
|
|
ps_ram_size = PSRAM_SIZE;
|
|
|
|
PROVIDE(PSRAM_HEAP_BEGIN = _PSRAM_HEAP_BEGIN);
|
|
PROVIDE(PSRAM_HEAP_END = _PSRAM_HEAP_END);
|
|
_PSRAM_MALLOC_SIZE = _PSRAM_HEAP_END - _PSRAM_HEAP_BEGIN;
|
|
PROVIDE(PSRAM_MALLOC_SIZE = _PSRAM_HEAP_END - _PSRAM_HEAP_BEGIN);
|
|
|
|
|
|
br35_PHY_RAM_SIZE = PHY_RAM_SIZE;
|
|
br35_SDK_RAM_SIZE = report_mmu_tlb_size + \
|
|
report_boot_info_size + \
|
|
report_irq_stack_size + \
|
|
report_data_size + \
|
|
report_bss_size + \
|
|
report_overlay_size + \
|
|
report_data_code_size + \
|
|
report_heap_size;
|
|
//============================================================//
|
|
//=== report section info end
|
|
//============================================================//
|
|
|